Table of Contents
7.4.2
I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt or an A/D converter conversion
end interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 7.6 indicates the register functions in I/O mode.
Table 7.6
Register Functions in I/O Mode
Register
23
MAR
23
7
All 1s
IOAR
15
ETCR
Legend
MAR:
Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Function
Activated by
SCI0 Receive-
Data-Full
Interrupt or
A/D Converter
Conversion
End Interrupt
0
Destination
address
register
0
Source
address
register
0
Transfer counter
Other
Activation
Initial Setting
Source
Destination or
address
source address
register
Destination
Source or
address
destination
register
address
Number of
transfers
Operation
Incremented or
decremented
once per
transfer
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
205
Table of Contents
