Page 1 OMC942723169 Hitachi Microcomputer H8/3032 Series Hardware Manual Downloaded from Elcodis.com electronic components distributor...
Page 2 Downloaded from Elcodis.com electronic components distributor...
Page 3 The three operating modes offer a choice of expanded mode and single-chip mode, enabling the H8/3032 Series to adapt quickly and flexibly to a variety of conditions. This manual describes the H8/3032 Series hardware. For details of the instruction set, refer to the H8/300H Programming Manual.
Page 4 Downloaded from Elcodis.com electronic components distributor...
Page 5: Table Of Contents
Contents Section 1 Overview ..................... Overview ........................Block Diagram........................ Pin Description ....................... 1.3.1 Pin Arrangement..................... 1.3.2 Pin Functions ....................Pin Functions ........................10 Section 2 ....................... 15 Overview ........................15 2.1.1 Features......................15 2.1.2 Differences from H8/300 CPU ............... 16 CPU Operating Modes....................
Page 6 Basic Operational Timing ....................51 2.9.1 Overview......................51 2.9.2 On-Chip Memory Access Timing..............51 2.9.3 On-Chip Supporting Module Access Timing ..........53 2.9.4 Access to External Address Space..............54 Section 3 MCU Operating Modes ................55 Overview ........................55 3.1.1 Operating Mode Selection ................
Page 7 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ........79 5.2.3 IRQ Status Register (ISR) ................85 5.2.4 IRQ Enable Register (IER)................86 5.2.5 IRQ Sense Control Register (ISCR) ............... 87 Interrupt Sources......................88 5.3.1 External Interrupts ..................88 5.3.2 Internal Interrupts ...................
Page 8 Port 2 ........................126 7.3.1 Overview......................126 7.3.2 Register Descriptions..................127 7.3.3 Pin Functions in Each Mode................128 7.3.4 Input Pull-Up Transistors................130 Port 3 ........................131 7.4.1 Overview......................131 7.4.2 Register Descriptions..................131 7.4.3 Pin Functions in Each Mode................133 Port 5 ........................
Page 9 Section 8 16-Bit Integrated Timer Unit (ITU) ............. 169 Overview ........................169 8.1.1 Features......................169 8.1.2 Block Diagrams ....................172 8.1.3 Input/Output Pins.................... 177 8.1.4 Register Configuration..................178 Register Descriptions...................... 181 8.2.1 Timer Start Register (TSTR) ................181 8.2.2 Timer Synchro Register (TSNC) ..............182 8.2.3 Timer Mode Register (TMDR)...............
Page 10 Section 9 Programmable Timing Pattern Controller ......... 269 Overview ........................269 9.1.1 Features......................269 9.1.2 Block Diagram....................270 9.1.3 TPC Pins ......................271 9.1.4 Registers ......................272 Register Descriptions...................... 273 9.2.1 Port A Data Direction Register (PADDR) ............273 9.2.2 Port A Data Register (PADR) .................
Page 11 10.3.3 Timing of Setting of Overflow Flag (OVF)............ 307 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ......308 10.4 Interrupts ........................309 10.5 Usage Notes ........................309 Section 11 Serial Communication Interface ............311 11.1 Overview ........................311 11.1.1 Features......................
Page 12 12.4.2 Scan Mode (SCAN = 1).................. 383 12.4.3 Input Sampling and A/D Conversion Time ............ 385 12.4.4 External Trigger Input Timing................ 386 12.5 Interrupts ........................387 12.6 Usage Notes ........................387 Section 13 ......................389 13.1 Overview ........................389 13.1.1 Block Diagram....................
Page 13 16.3.2 Exit from Sleep Mode..................414 16.4 Software Standby Mode ....................415 16.4.1 Transition to Software Standby Mode ............415 16.4.2 Exit from Software Standby Mode ..............415 16.4.3 Selection of Waiting Time for Exit from Software Standby Mode ....416 16.4.4 Sample Application of Software Standby Mode ..........
Page 14 Port 7 Block Diagram ..................... 538 Port 8 Block Diagram ..................... 539 Port 9 Block Diagram ..................... 540 Port A Block Diagram ....................543 C.10 Port B Block Diagram ....................546 Appendix D Pin States ..................... 550 Port States in Each Mode....................550 Pin States at Reset......................
Page 15 Downloaded from Elcodis.com electronic components distributor...
Page 16: Overview
(SCI), an A/D converter, I/O ports, and other facilities. The three members of the H8/3032 Series are the H8/3032, the H8/3031, and the H8/3030. The H8/3032 has 64 kbytes of ROM and 2 kbytes of RAM. The H8/3031 has 32 kbytes of ROM and 1 kbyte of RAM.
Page 17 Table 1-1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 16 MHz • Add/subtract: 125 ns •...
Page 18 Table 1-1 Features (cont) Feature Description 16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 timer unit (ITU) pulse inputs • 16-bit timer counter (channels 0 to 4) • Two multiplexed output compare/input capture pins (channels 0 to 4) •...
Page 19 Table 1-1 Features (cont) Feature Description Operating modes Three MCU operating modes Address Address Mode Space Pins Width Mode 1 1 Mbyte to A 8 bits Mode 2 64 kbytes — — Mode 3 1 Mbyte — — Power-down • Sleep mode state •...
Page 20: Block Diagram
(SCI) × 1 channel (ITU) /IRQ Programmable A/D converter timing pattern /SCK/IRQ controller (TPC) /RxD /TxD Port B Port A Port 7 Note: PROM version is available only in the H8/3032 Series. Figure 1-1 Block Diagram Downloaded from Elcodis.com electronic components distributor...
Page 21: Pin Description
1.3 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3032 Series, FP-80A and TFP-80C package. /TIOCA /TIOCB /TIOCA RESO /TIOCB /TOCXA /TOCXB /ADTRG /TxD XTAL /RxD EXTAL Top view /SCK/IRQ (FP-80A, TFP-80C) STBY ø /WAIT...
Page 22: Pin Functions
1.3.2 Pin Functions Pin Assignments in Each Mode: Table 1-2 lists the FP-80A and TFP-80C pin assignments in each mode. Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode Pin Name Mode 1 Mode 2 Mode 3 PROM Mode /TIOCA /TIOCA /TIOCA...
Page 23 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name Mode 1 Mode 2 Mode 3 PROM Mode /WAIT ø ø ø STBY STBY STBY EXTAL EXTAL EXTAL XTAL XTAL XTAL Downloaded from Elcodis.com electronic components distributor...
Page 24 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name Mode 1 Mode 2 Mode 3 PROM Mode RESO RESO RESO /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /TCLKA /TCLKA /TCLKA /TCLKB /TCLKB /TCLKB /TIOCA...
Page 25: Pin Functions
1.4 Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Type Symbol Pin No. Name and Function Power 21, 53 Input Power: For connection to the power supply (+5 V). Connect all V pins to the +5-V system power supply.
Page 26 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function Interrupts Input Nonmaskable interrupt: Requests a nonmaskable interrupt Input Interrupt request 4 to 0: Maskable interrupt 72 to 69 request pins Address bus to A 42 to 31, Output Address bus: Outputs address signals to A 29 to 22...
Page 27 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function Serial com- Output Transmit data: SCI data output munication interface (SCI) Input Receive data: SCI data input Input/ Serial clock: SCI clock input/output output to AN 66 to 59 Input Analog 7 to 0: Analog input pins converter...
Page 28 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function I/O ports , P9 11 to 9 Input/ Port 9: Three input/output pins. The direction output of each pin can be selected in the port 9 data direction register (P9DDR). to PA 80 to 73 Input/...
Page 29 Downloaded from Elcodis.com electronic components distributor...
Page 30: Cpu
— Memory indirect [@@aa:8] • 1-Mbyte* linear address space Note: * The CPU, if used alone, can access a maximum address space of 16 Mbytes. However, the maximum address space of the H8/3032 Series is 1 Mbyte. Downloaded from Elcodis.com electronic components distributor...
Page 31: Differences From H8/300 Cpu
• High-speed operation — All frequently-used instructions execute in two to four states — Maximum clock frequency: 16 MHz — 8/16/32-bit register-register add/subtract: 125 ns — 8 × 8-bit register-register multiply: 875 ns — 16 ÷ 8-bit register-register divide: 875 ns —...
Page 32: Cpu Operating Modes
2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 1 Mbytes. See figure 2-1. Maximum 64 kbytes, program Normal mode and data areas combined CPU operating modes Maximum 1 Mbyte, program Advanced mode...
Page 33: Address Space
2.3 Address Space Figure 2-2 shows a simple memory map for the H8/3032 Series. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
Page 34: Register Configuration
2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
Page 35: General Registers
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 36: Control Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR).
Page 37: Initial Cpu Register Values
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
Page 38: Data Formats
2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 39: Memory Data Formats
General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (2) 2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory.
Page 40 Data Type Address Data Format 1-bit data Address Byte data Address Word data Address 2m Address 2m + 1 Address 2n Longword data Address 2n + 1 Address 2n + 2 Address 2n + 3 Figure 2-8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Page 41: Instruction Set
2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2-1. Table 2-1 Instruction Classification Function Instruction Types Data transfer MOV, PUSH , POP , MOVTPE , MOVFPE Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU Logic operations...
Page 42: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ @ (d:8, (d:16, @@ Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 PC) aa:8 Implied BWL BWL BWL...
Page 43: Tables Of Instructions Classified By Function
2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand (EAs)
Page 44 Table 2-3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3032.
Page 45 Table 2-4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 46 Table 2-4 Arithmetic Operation Instructions (cont) Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 47 Table 2-5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 48 Table 2-7 Bit Manipulation Instructions Instruction Size* Function 1 → ( of ) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 49 Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* Function C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ [¬ ( of )] → C BIOR ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
Page 50 Table 2-8 Branching Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 51 Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 52 Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — repeat @ER5+ → @ER6+, R4L – 1 → R4L until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — repeat @ER5+ → @ER6+, R4 – 1 → R4 until R4 = 0 else next;...
Page 53: Basic Instruction Formats
2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Page 54: Notes On Use Of Bit Manipulation Instructions
2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports.
Page 55 1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Page 56 Table 2-12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 64-kbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF H'FF00 to H'FFFF (1048320 to 1048575) (65280 to 65535) 16 bits (@aa:16) H'00000 to H'07FFF, H'0000 to H'FFFF H'F8000 to H'FFFFF (0 to 65535) (0 to 32767, 1015808 to 1048575) 24 bits (@aa:24) H'00000 to H'FFFFF...
Page 57: Effective Address Calculation
Specified by @aa:8 Reserved Branch address Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address.
Page 58 Table 2-13 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Effective Address Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) General register contents Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) General register contents disp Sign extension disp...
Page 59 Table 2-13 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Effective Address Absolute address @aa:8 H'FFFF 16 15 @aa:16 Sign extension @aa:24 Immediate Operand is immediate data #xx:8, #xx:16, or #xx:32 Program-counter relative @(d:8, PC) or @(d:16, PC) PC contents Sign disp...
Page 60 Table 2-13 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Effective Address Memory indirect @@aa:8 Normal mode H'0000 16 15 Memory contents H'00 Advanced mode H'0000 Memory contents Legend r, rm, rn: Register field Operation field disp: Displacement IMM:...
Page 61: Processing States
2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states.
Page 62: Program Execution State
2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 63 Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2-12 Classification of Exception Sources Program execution state SLEEP instruction with SSBY = 0 Exception End of exception Sleep mode handling SLEEP instruction Interrupt with SSBY = 1 NMI, IRQ , IRQ , or IRQ interrupt Exception-handling state...
Page 64: Exception-Handling Sequences
2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
Page 65: Reset State
2.8.5 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high.
Page 66: Basic Operational Timing
2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
Page 67 ø Address bus Address RD WR High High impedance to D Figure 2-16 Pin States during On-Chip Memory Access Downloaded from Elcodis.com electronic components distributor...
Page 68: On-Chip Supporting Module Access Timing
2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed. Figure 2-17 shows the on-chip supporting module access timing. Figure 2-18 indicates the pin states. Bus cycle T state T state...
Page 69: Access To External Address Space
ø Address bus Address RD HWR LWR High High impedance to D Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states.
Page 70: Mcu Operating Modes
64 kbytes. The H8/3032 Series can only be used in modes 1 to 3. The inputs at the mode pins must select one of these three modes. The inputs at the mode pins must not be changed during operation.
Page 71: Register Configuration
3.1.2 Register Configuration The H8/3032 Series has a mode control register (MDCR) that indicates the inputs at the mode pins (MD to MD ), and a system control register (SYSCR). Table 3-2 summarizes these registers. Table 3-2 Registers Address* Name...
Page 72: Mode Control Register (Mdcr)
3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3032 Series. — — — — — — MDS1 MDS0 Initial value — — Read/Write — — — — — — Reserved bits Mode select 1 and 0 Bits indicating the current...
Page 73: System Control Register (Syscr)
3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3032 Series. SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select...
Page 74 Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at least 8 ms at the system clock rate.
Page 75: Operating Mode Descriptions
3.4 Operating Mode Descriptions 3.4.1 Mode 1 1-Mbyte address space can be accessed including the on-chip ROM addresses. Port 3 pins function as data pins D to D and port 1, 2, and 5 pins function as address pins A to A .
Page 76: Pin Functions In Each Operating Mode
3.5 Pin Functions in Each Operating Mode The pin functions of ports 1, 2, 3, 5, and 6 vary depending on the operating mode. Table 3-3 indicates their functions in each operating mode. Table 3-3 Pin Functions in Each Mode Port Mode 1 Modes 2, 3...
Page 77 Mode 1 Mode 2 Mode 3 (expanded mode with on-chip ROM) (single-chip normal mode) (single-chip advanced mode) H'00000 H'0000 H'00000 Vector table Vector table Vector table H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'07FFF H'0FFFF H'F70F H'0FFFF H'10000 H'F710 Area 0...
Page 78 Mode 1 Mode 2 Mode 3 (expanded mode with on-chip ROM) (single-chip normal mode) (single-chip advanced mode) H'00000 H'0000 H'00000 Vector table Vector table Vector table H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'07FFF Reserved H'0FFFF H'7FFF H'10000 Area 0 H'1FFFF...
Page 79 Mode 1 Mode 2 Mode 3 (with on-chip ROM) (single-chip normal mode) (single-chip advanced mode) H'00000 H'0000 H'00000 Vector table Vector table Vector table H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'03FFF H'03FFF Reserved H'0FFFF H'3FFF H'10000 Area 0 H'1FFFF H'FD10 H'20000...
Page 80: Exception Handling
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 81: Exception Vector Table
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 82: Reset
The H8/3032 Series enters the reset state when the RES pin goes low. To ensure that the H8/3032 Series is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8/3032 Series during operation, hold the RES pin low for at least 10 system clock (ø) cycles.
Page 83 Prefetch of Internal first program Vector fetch processing instruction ø Address Internal read signal Internal write signal On chip data (1), (3) Address of reset vector: (1) = H'00000, (3) = H'00002 (2), (4) Start address (contents of reset vector) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 84: Interrupts After Reset
Internal Vector fetch processing Prefetch of first program instruction ø Address bus High to D (1), (3) Address of reset vector: (1) = H'00000, (3) = H'00002 (2), (4) Start address (contents of reset vector) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 85 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ to IRQ ) and 21 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit integrated timer unit (ITU), serial communication interface (SCI), and A/D converter.
Page 86: Trap Instruction
4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code.
Page 87: Stack Status After Exception Handling
4.5 Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP-4 SP (ER7) SP-3 SP+1 SP-2 SP+2 SP-1 SP+3 SP (ER7) → SP+4 Even address Stack area Before exception handling After exception handling Save on stack...
Page 88: Notes On Stack Usage
4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3032 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @–SP)
Page 89 Downloaded from Elcodis.com electronic components distributor...
Page 90: Interrupt Controller
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
Page 91: Block Diagram
5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number ADIE Interrupt controller SYSCR Legend Interrupt mask bit IER: IRQ enable register IPRA: Interrupt priority register A IPRB:...
Page 92: Pin Configuration
5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable External interrupt request 4 to 0 IRQ to IRQ Input Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration Table 5-2 lists the registers of the interrupt controller.
Page 93: Register Descriptions
5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR).
Page 94: Interrupt Priority Registers A And B (Ipra, Iprb)
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 95 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of ITU channel 2 interrupt requests Priority level A1...
Page 96 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 97 Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT interrupt requests. Bit 3 IPRA3 Description WDT interrupt requests have priority level 0 (low priority) (Initial value) WDT interrupt requests have priority level 1 (high priority) Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2 IPRA2 Description...
Page 98 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 — IPRB1 — Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Reserved bit Priority level B3...
Page 99 Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7 IPRB7 Description ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 3 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Page 100: Irq Status Register (Isr)
5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ to IRQ interrupt requests. — — — IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write R/(W) R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *...
Page 101: Irq Enable Register (Ier)
5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests. — — — IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write Reserved bits IRQ to IRQ enable These bits enable or disable to IRQ interrupts IER is initialized to H'00 by a reset and in hardware standby mode.
Page 102: Irq Sense Control Register (Iscr)
5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ — — — IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write Reserved bit IRQ to IRQ sense control These bits select level sensing or falling-edge sensing for IRQ...
Page 103: Interrupt Sources
5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 21 internal interrupts. 5.3.1 External Interrupts There are six external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and IRQ can be used to exit software standby mode.
Page 104: Internal Interrupts
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø IRQn input pin IRQnF Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 16. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 105 Table 5-3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority External pins H'001C to H'001F H'000E to H'000F — High H'0030 to H'0033 H'0018 to H'0019 IPRA7 H'0034 to H0037 H'001A to H'001B IPRA6 H'0038 to H'003B H'001C to H'001D IPRA5...
Page 106 Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority IMIA3 (compare match/ ITU channel 3 H'0090 to H'0093 H'0048 to H'0049 IPRB7 input capture A3) IMIB3 (compare match/ H'0094 to H'0097 H'004A to H'004B input capture B3)
Page 107: Interrupt Operation
5.4.1 Interrupt Handling Process The H8/3032 Series handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 108 Program execution state Interrupt requested? Pending Priority level 1? I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1 Downloaded from Elcodis.com electronic components distributor...
Page 109 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 110 Figure 5-5 shows the transitions among the above states. ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example)
Page 111 Program execution state Interrupt requested? Pending Priority level 1? I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0 Downloaded from Elcodis.com electronic components distributor...
Page 112: Interrupt Sequence
Interrupt accepted Prefetch of Interrupt level interrupt decision and wait Instruction Internal Internal service routine for end of instruction prefetch processing Stack Vector fetch processing instruction ø Interrupt request signal to A (11) (13) Internal read signal Internal High write signal (10) (12) (14)
Page 113: Interrupt Response Time
5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory 8-Bit Bus On-Chip Item Memory 2 States 3 States...
Page 114: Usage Notes
5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 115: Instructions That Inhibit Interrupts
5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 116: Bus Controller
Section 6 Bus Controller 6.1 Overview The H8/3032 Series has an on-chip bus controller that divides the external address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily.
Page 117: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. Internal ASTCR address bus Area WCER decoder Internal signals Bus control circuit Access state control signal Wait request signal Wait-state WAIT controller Legend ASTCR: Access state control register WCER: Wait state controller enable register WCR:...
Page 118: Input/Output Pins
6.1.3 Input/Output Pins Table 6-1 summarizes the bus controller’s input/output pins. Table 6-1 Bus Controller Pins Name Abbreviation Function Address strobe Output Strobe signal indicating valid address output on the address bus Read Output Strobe signal indicating reading from the external address space Write Output...
Page 119: Register Descriptions
6.2 Register Descriptions 6.2.1 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
Page 120: Wait Control Register (Wcr)
6.2.2 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. — — — — WMS1 WMS2 Initial value Read/Write — — — —...
Page 121: Wait State Controller Enable Register (Wcer)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 Bit 0 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 6.2.3 Wait State Controller Enable Register (WCER)
Page 122: Operation
6.3 Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte mode. Figure 6-2 shows a general view of the memory map. H'00000 On-chip ROM Area 0 (128 kbytes) H'1FFFF H'20000...
Page 123 The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ASTCR WCER Bus Specifications Access ASTn WCEn WMS1 WMS0 Width States Wait Mode — — — Disabled —...
Page 124: Bus Control Signal Timing
6.3.2 Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8-bit, three-state-access area. Wait states can be inserted. Bus cycle ø Address bus External address Read access Valid to D Write access Valid to D...
Page 125 8-Bit, Two-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, two-state-access area. Wait status cannot be inserted. Bus cycle ø Address bus External address Read access to D Valid Write access to D Valid Figure 6-4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area Downloaded from Elcodis.com electronic components distributor...
Page 126: Wait Modes
6.3.3 Wait Modes Four wait modes can be selected for each area as shown in table 6-4. Table 6-4 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode — — — Disabled No wait states —...
Page 127 Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall ) is inserted. If the WAIT pin remains low, of the system clock (ø) in the T state, a wait state (T wait states continue to be inserted until the WAIT signal goes high.
Page 128 Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states ) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high.
Page 129 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T state, the number of wait states (T ) selected by bits WC1 and WC0 are inserted.
Page 130 Programmable Wait Mode: The number of wait states (T ) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6-8 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø...
Page 131 Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings. Figure 6-9 shows an example of wait mode settings.
Page 132: Interconnections With Memory (Example)
Figure 6-10 shows an example of interconnections between the H8/3032 Series and memory. Figure 6-10 shows a memory map for this example.
Page 133: Usage Notes
6.4 Usage Notes 6.4.1 Register Write Timing ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from the next bus cycle. Figure 6-11 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. ø...
Page 134: I/O Ports
7.1 Overview The H8/3032 Series has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 7-1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7-1.
Page 135 Table 7-1 Port Functions (1) Port Description Pins Mode 1 Mode 2 Mode 3 Port 1 • 8-bit I/O port to P1 Address output (A Generic input/output • Can drive LEDs to A ) and generic input DDR = 0: generic input DDR = 1: address output...
Page 136 Table 7-1 Port Functions (1) Port Description Pins Mode 1 Mode 2 Mode 3 Port A • 8-bit I/O port /TIOCB TPC output (TP to TP ), ITU input and output (TCLKD, • Schmitt inputs /TIOCA TCLKC, TCLKB, TCLKA, TIOCB , TIOCA , TIOCB , TIOCA...
Page 137: Port 1
7.2 Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ depending on the operating mode. In mode 1, they are address bus output pins (A to A In modes 2 and 3, port 1 is a generic input/output port.
Page 138: Register Descriptions
7.2.2 Register Descriptions Table 7-2 summarizes the registers of port 1. Table 7-2 Port 1 Registers Address* Name Abbreviation Initial Value H'FFC0 Port 1 data direction register P1DDR H'00 H'FFC2 Port 1 data register P1DR H'00 Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1.
Page 139: Pin Functions In Each Mode
Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores data for pins to P1 Initial value Read/Write Port 1 data 7 to 0 These bits store data for port 1 pins When a bit in P1DDR is set to 1, if port 1 is read the value of the corresponding P1DR bit is returned directly, regardless of the actual state of the pin.
Page 140 Mode 1: Address output or generic input can be selected for each pin in port 1. A pin becomes an address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared to 0.
Page 141: Port 2
7.3 Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-4. The pin functions differ depending on the operating mode. In mode 1, settings in the port 1 data direction register (P1DDR) can designate pins for address bus output (A to A ) or generic input.
Page 142: Register Descriptions
7.3.2 Register Descriptions Table 7-3 summarizes the registers of port 2. Table 7-3 Port 2 Registers Address* Name Abbreviation Initial Value H'FFC1 Port 2 data direction register P2DDR H'00 H'FFC3 Port 2 data register P2DR H'00 H'FFD8 Port 2 input pull-up control register P2PCR H'00 Note: * Lower 16 bits of the address.
Page 143: Pin Functions In Each Mode
Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores data for pins to P2 Initial value Read/Write Port 2 data 7 to 0 These bits store data for port 2 pins When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned directly, regardless of the actual state of the pin.
Page 144 Mode 1: Address output or generic input can be selected for each pin in port 2. A pin becomes an address output pin if the corresponding P2DDR bit is set to 1, and a generic input pin if this bit is cleared to 0.
Page 145: Input Pull-Up Transistors
7.3.4 Input Pull-Up Transistors Port 2 has built-in MOS input pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually. When a P2PCR bit is set to 1 and the corresponding P2DDR bit is cleared to 0, the input pull-up transistor is turned on.
Page 146: Port 3
7.4 Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7-7. Port 3 is a data bus in mode 1 and a generic input/output port in modes 2 and 3. Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair.
Page 147 Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 data direction 7 to 0...
Page 148: Pin Functions In Each Mode
7.4.3 Pin Functions in Each Mode The pin functions of port 3 differ between modes 1 and modes 2 and 3. The pin functions in each mode are described below. Mode 1: All pins of port 3 automatically become data input/output pins. Figure 7-8 shows the pin functions in mode 1.
Page 149: Port 5
7.5 Port 5 7.5.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7-10. The pin functions differ depending on the operating mode. In mode 1, settings in the port 5 data direction register (P5DDR) designate pins for address bus output (A to A ) or generic input.
Page 150 Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. — — — — P5 DDR P5 DDR P5 DDR P5 DDR Initial value Read/Write — —...
Page 151 Bits P5 to P5 are reserved. They can be written and read, but they cannot be used for port input or output. P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
Page 152: Pin Functions In Each Mode
7.5.3 Pin Functions in Each Mode The functions of port 5 differ depending on the operating mode. The pin functions in each mode are described below. Mode 1: Address output or generic input can be selected for each pin in port 5. A pin becomes an address output pin if the corresponding P5DDR bit is set to 1, and a generic input pin if this bit is cleared to 0.
Page 153: Input Pull-Up Transistors
7.5.4 Input Pull-Up Transistors Port 5 has built-in MOS pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually. When a P5PCR bit is set to 1 and the corresponding P5DDR bit is cleared to 0, the input pull-up transistor is turned on.
Page 154: Port 6
7.6 Port 6 7.6.1 Overview Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals (WR, RD, AS, and WAIT). Figure 7-13 shows the pin configuration of port 6. In mode 1, the pin functions are WR, RD, AS, and P6 /WAIT.
Page 155 Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. — — P6 DDR P6 DDR P6 DDR — — P6 DDR Initial value Read/Write — Reserved bit Port 6 data direction 6 to 0 These bits select input or output for port 6 pins...
Page 156: Pin Functions In Each Mode
When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin level is read.
Page 157 Table 7-9 Port 6 Pin Functions in Mode 1 Pin Functions and Selection Method Functions as follows regardless of P6 WR output Pin function Functions as follows regardless of P6 RD output Pin function Functions as follows regardless of P6 AS output Pin function /WAIT...
Page 158 Modes 2 and 3: Input or output can be selected separately for each pin in port 6. A pin becomes an output pin if the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7-15 shows the pin functions in modes 2 and 3.
Page 159: Port 7
7.7 Port 7 7.7.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin functions are the same in all operating modes. Figure 7-16 shows the pin configuration of port 7. Port 7 pins P7 (input)/AN (input) P7 (input)/AN (input)
Page 160: Register Description
7.7.2 Register Description Table 7-10 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction register. Table 7-10 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFCE Port 7 data register P7DR Undetermined Note: * Lower 16 bits of the address.
Page 161: Port 8
7.8 Port 8 7.8.1 Overview Port 8 is a 4-bit input/output port that is also used for IRQ to IRQ input. Figure 7-17 shows the pin configuration of port 8. Pin P8 functions as input/output pin or as an IRQ input pin.
Page 162: Register Descriptions
7.8.2 Register Descriptions Table 7-11 summarizes the registers of port 8. Table 7-11 Port 8 Registers Address* Name Abbreviation Initial Value H'FFCD Port 8 data direction P8DDR H'E0 register H'FFCF Port 8 data register P8DR H'E0 Note: * Lower 16 bits of the address. Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
Page 163: Pin Functions
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores data for pins to P8 — — — — Initial value Read/Write — — — Reserved bits Port 8 data 4 to 0 These bits store data for port 8 pins When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned directly.
Page 164 Table 7-12 Port 8 Pin Functions Pin Functions and Selection Method /IRQ Bit P8 DDR selects the pin function as follows Mode 1 Modes 2 and 3 Pin function input Illegal setting output input /IRQ Bit P8 DDR selects the pin function as follows Mode 1 Modes 2 and 3 Pin function...
Page 165: Port 9
7.9 Port 9 7.9.1 Overview Port 9 is a 3-bit input/output port that is also used for input and output (TxD, RxD, SCK) by serial communication interface (SCI), and for IRQ input. Port 9 has the same set of pin functions in all operating modes.
Page 166 Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. — — — P9 DDR — P9 DDR — P9 DDR Initial value Read/Write — — Reserved bits Port 9 data direction 4, 2, 0 These bits select input or...
Page 167: Pin Functions
Bits 7 to 5, 3 and 1 are reserved. Bits 7 and 6 cannot be modified and always read 1. Bits 5, 3, and 1 can be written and read, but they cannot be used for port input or output. If bit 5, 3, or 1 in P9DDR is read while its value is 1, the corresponding bit in P9DR is read directly.
Page 168: Port A
7.10 Port A 7.10.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC) and input and output (TIOCB , TIOCA , TIOCB , TIOCA TIOCB , TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU),...
Page 169: Register Descriptions
7.10.2 Register Descriptions Table 7-15 summarizes the registers of port A. Table 7-15 Port A Registers Address* Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 H'FFD3 Port A data register PADR H'00 Note: * Lower 16 bits of the address. Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select input or output for each pin in port A.
Page 170 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for pins PA to PA Initial value Read/Write Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly.
Page 171: Pin Functions
7.10.3 Pin Functions The port A pins are also used for TPC output (TP to TP ), ITU input/output (TIOCB to TIOCB TIOCA to TIOCA ), and input (TCLKD, TCLKC, TCLKB, TCLKA). Table 7-16 describes the selection of pin functions. Table 7-16 Port A Pin Functions Pin Functions and Selection Method ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in TIOR2), bit...
Page 172 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 TIOCA in NDERA, and bit PA DDR in PADDR select the pin function as follows ITU channel 2 settings 1 in table below...
Page 173 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method ITU channel 1 settings (bit PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 TIOCA in NDERA, and bit PA DDR in PADDR select the pin function as follows ITU channel 1 settings 1 in table below...
Page 174 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TPSC2 TIOCA to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA DDR in PADDR select TCLKC the pin function as follows...
Page 175 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method Bit NDER1 in NDERA and bit PA DDR in PADDR select the pin function as follows TCLKB NDER1 — Pin function input output output TCLKB input* Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0.
Page 176: Port B
7.11 Port B 7.11.1 Overview Port B is an 8-bit input/output port that is also used for TPC output (TP to TP ), ITU input/output ), and ADTRG input (TIOCB , TIOCB , TIOCA , TIOCA ) and ITU output (TOCXB , TOCXA to the A/D converter.
Page 177 Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
Page 178: Pin Functions
7.11.3 Pin Functions The port B pins are also used for TPC output (TP to TP ), ITU input/output (TIOCB , TIOCB ), and ADTRG input. Table 7-18 describes the TIOCA , TIOCA ) and output (TOCXB , TOCXA selection of pin functions. Table 7-18 Port B Pin Functions Pin Functions and Selection Method Bit TRGE in ADCR, bit NDER15 in NDERB and bit PB...
Page 179 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB DDR in PBDDR select TIOCB the pin function as follows...
Page 180 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB DDR in PBDDR select TIOCA the pin function as follows...
Page 181 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB DDR in PBDDR select the pin function as follows channel 3...
Page 182 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and TIOCA bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB DDR in PBDDR select the pin function as follows channel 3...
Page 183 Downloaded from Elcodis.com electronic components distributor...
Page 184: 16-Bit Integrated Timer Unit (Itu)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.1 Overview The H8/3032 Series has a built-in 16-bit integrated timer-pulse unit (ITU) with five 16-bit timer channels. 8.1.1 Features ITU features are listed below. • Capability to process up to 12 pulse outputs or 10 pulse inputs •...
Page 185 — PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to five-phase PWM output is possible • Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. • Three additional modes selectable in channels 3 and 4 —...
Page 186 Table 8-1 summarizes the ITU functions. Table 8-1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Clock sources Internal clocks: ø, ø/2, ø/4, ø/8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3...
Page 187: Block Diagrams
8.1.2 Block Diagrams ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU. IMIA0 to IMIA4 TCLKA to TCLKD Clock selector Control logic IMIB0 to IMIB4 OVI0 to OVI4 ø, ø/2, ø/4, ø/8 Counter control and TOCXA , TOCXB pulse I/O control unit TIOCA...
Page 188 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8-2. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 IMIA0 IMIB0 Comparator Control logic OVI0 Module data bus Legend TCNT:...
Page 189 Block Diagram of Channel 2: Figure 8-3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 IMIA2 Comparator Control logic IMIB2 OVI2 Module data bus...
Page 190 Block Diagrams of Channels 3 and 4: Figure 8-4 is a block diagram of channel 3. Figure 8-5 is a block diagram of channel 4. TIOCA TCLKA to TIOCB TCLKD Clock selector ø, ø/2, ø/4, ø/8 IMIA3 Comparator Control logic IMIB3 OVI3 Module data bus...
Page 191 TOCXA TCLKA to TOCXB TCLKD Clock selector ø, ø/2, TIOCA ø/4, ø/8 TIOCB IMIA4 Comparator Control logic IMIB4 OVI4 Module data bus Legend TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) ×...
Page 192: Input/Output Pins
8.1.3 Input/Output Pins Table 8-2 summarizes the ITU pins. Table 8-2 ITU Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input External clock B input pin...
Page 193: Register Configuration
8.1.4 Register Configuration Table 8-3 summarizes the ITU registers. Table 8-3 ITU Registers Abbre- Initial Channel Address Name viation Value Common H'FF60 Timer start register TSTR H'E0 H'FF61 Timer synchro register TSNC H'E0 H'FF62 Timer mode register TMDR H'80 H'FF63 Timer function control register TFCR H'C0...
Page 194 Table 8-3 ITU Registers (cont) Abbre- Initial Channel Address Name viation Value H'FF78 Timer control register 2 TCR2 H'80 H'FF79 Timer I/O control register 2 TIOR2 H'88 H'FF7A Timer interrupt enable register 2 TIER2 H'F8 H'FF7B Timer status register 2 TSR2 R/(W) H'F8...
Page 195 Table 8-3 ITU Registers (cont) Abbre- Initial Channel Address Name viation Value H'FF92 Timer control register 4 TCR4 H'80 H'FF93 Timer I/O control register 4 TIOR4 H'88 H'FF94 Timer interrupt enable register 4 TIER4 H'F8 H'FF95 Timer status register 4 TSR4 R/(W) H'F8...
Page 196: Register Descriptions
8.2 Register Descriptions 8.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — —...
Page 197: Timer Synchro Register (Tsnc)
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1 STR1 Description TCNT1 is halted (Initial value) TCNT1 is counting Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0 STR0 Description TCNT0 is halted (Initial value) TCNT0 is counting...
Page 198 Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or synchronously. Bit 3 SYNC3 Description Channel 3’s timer counter (TCNT3) operates independently (Initial value) TCNT3 is preset and cleared independently of other channels Channel 3 operates synchronously TCNT3 can be synchronously preset and cleared Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously.
Page 199: Timer Mode Register (Tmdr)
8.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. — FDIR PWM4 PWM3 PWM2 PWM1 PWM0...
Page 200 When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
Page 201 Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode. Bit 3 PWM3 Description Channel 3 operates normally (Initial value) Channel 3 operates in PWM mode When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match with general register B3 (GRB3).
Page 202: Timer Function Control Register (Tfcr)
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 Description Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match with general register B0 (GRB0).
Page 203 Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels 3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode. Bit 5 Bit 4 CMD1 CMD0 Description Channels 3 and 4 operate normally (Initial value) Channels 3 and 4 operate together in complementary PWM mode Channels 3 and 4 operate together in reset-synchronized PWM mode...
Page 204: Timer Output Master Enable Register (Toer)
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or whether GRB3 is buffered by BRB3. Bit 1 BFB3 Description GRB3 operates normally (Initial value) GRB3 is buffered by BRB3 Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or whether GRA3 is buffered by BRA3.
Page 205 Bit 5—Master Enable TOCXB (EXB4): Enables or disables ITU output at pin TOCXB Bit 5 EXB4 Description TOCXB output is disabled regardless of TFCR settings (TOCXB operates as a generic input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1. TOCXB is enabled for output according to TFCR settings (Initial value)
Page 206 Bit 2—Master Enable TIOCB (EB4): Enables or disables ITU output at pin TIOCB Bit 2 Description TIOCB output is disabled regardless of TIOR4 and TFCR settings (TIOCB operates as a generic input/output pin). If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1. TIOCB is enabled for output according to TIOR4 and TFCR settings (Initial value)
Page 207: Timer Output Control Register (Tocr)
8.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. — — — XTGD — — OLS4 OLS3 Initial value Read/Write —...
Page 208: Timer Counters (Tcnt)
Bits 3 and 2—Reserved: Read-only bits, always read as 1. Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 Description TIOCA3, TIOCA4, and TIOCB4 outputs are inverted TIOCA3, TIOCA4, and TIOCB4 outputs are not inverted (Initial value) Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and reset-synchronized PWM mode.
Page 209: General Registers (Gra, Grb)
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM mode and up-counters in other modes. TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or by input capture to GRA or GRB (counter clearing function) in the same channel.
Page 210: Buffer Registers (Bra, Brb)
When a general register is used as an input capture register, rising edges, falling edges, or both edges of an external input capture signal are detected and the current TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR.
Page 211: Timer Control Registers (Tcr)
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. 8.2.10 Timer Control Registers (TCR) TCR is an 8-bit register.
Page 212 Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture TCNT is cleared by GRB compare match or input capture Synchronous clear: TCNT is cleared in synchronization with other synchronized timers Notes: 1.
Page 213: Timer I/O Control Register (Tior)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: ø (Initial value) Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input...
Page 214 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins.
Page 215: Timer Status Register (Tsr)
Bit 3—Reserved: Read-only bit, always read as 1. Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 Function GRA is an output No output at compare match (Initial value) compare register 0 output at GRA compare match...
Page 216 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Reserved bits Overflow flag Status flag indicating overflow or underflow Input capture/compare match flag B Status flag indicating GRB compare match or input capture Input capture/compare match flag A Status flag indicating GRA compare match or input capture...
Page 217 Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB compare match or input capture events. Bit 1 IMFB Description [Clearing condition] (Initial value) Read IMFB when IMFB = 1, then write 0 in IMFB [Setting conditions] TCNT = GRB when GRB functions as a compare match register. TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register.
Page 218: Timer Interrupt Enable Register (Tier)
8.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel Abbreviation Function TIER0 Enables or disables interrupt requests. TIER1 TIER2 TIER3 TIER4 — — — — — OVIE IMIEB IMIEA Initial value Read/Write...
Page 219 Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the overflow flag (OVF) in TSR when OVF is set to 1. Bit 2 OVIE Description OVI interrupt requested by OVF is disabled (Initial value) OVI interrupt requested by OVF is enabled Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Page 220: Cpu Interface
8.3 CPU Interface 8.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus.
Page 221 On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 8-8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 8-9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) On-chip data bus Module Bus interface...
Page 222: 8-Bit Accessible Registers
On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 8-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 8-12 and 8-13 show examples of byte read and write access to a TCR.
Page 223 On-chip data bus Module Bus interface data bus Figure 8-13 TCR Access (CPU Reads TCR) Downloaded from Elcodis.com electronic components distributor...
Page 224: Operation
8.4 Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
Page 225: Basic Functions
Buffering • If the general register is an output compare register When compare match occurs the buffer register value is transferred to the general register. • If the general register is an input capture register When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register.
Page 226 Counter setup Select counter clock Type of counting? Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 8-14 Counter Setup Procedure (Example) Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal.
Page 227 • Free-running and periodic counter operation A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer status register (TSR).
Page 228 TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 8-16 Periodic Counter Operation • Count timing — Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock sources obtained by prescaling the system clock (ø/2, ø/4, ø/8).
Page 229 — External clock source Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected.
Page 230 Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
Page 231 TCNT value H'FFFF Time TIOCB No change No change 1 output No change No change 0 output TIOCA Figure 8-20 0 and 1 Output (Examples) Figure 8-21 shows examples of toggle output. TCNT operates as a periodic counter, cleared by compare match B. Toggle output is selected for both compare match A and B. TCNT value Counter cleared by compare match with GRB Time...
Page 232 • Output compare timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 233 Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the port data direction bit to 0 before making these TIOR settings. Select input-capture input Start counter Set the STR bit to 1 in TSTR to start the timer...
Page 234 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8-25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 235: Synchronization
8.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 236 Example of Synchronization: Figure 8-27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
Page 237: Pwm Mode
8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
Page 238 Sample Setup Procedure for PWM Mode: Figure 8-28 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to Select counter clock select the desired edge(s) of the...
Page 239 Examples of PWM Mode: Figure 8-29 shows examples of operation in PWM mode. The PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, TCNT is cleared by compare match with GRA or GRB.
Page 240 Figure 8-30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
Page 241: Reset-Synchronized Pwm Mode
8.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an up- counter.
Page 242 Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 8-31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted.
Page 243 Example of Reset-Synchronized PWM Mode: Figure 8-32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM outputs toggle at compare match with GRB3, GRA4, GRB4, and TCNT3 respectively, and all toggle when the counter is cleared.
Page 244: Complementary Pwm Mode
8.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA , TIOCB and TOCXB automatically become PWM output pins, and TCNT3 and TCNT4 function as up/down-counters.
Page 245 Setup Procedure for Complementary PWM Mode: Figure 8-33 shows a sample procedure for setting up complementary PWM mode. Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are Stop counting halted.
Page 246 Clearing Complementary PWM Mode: Figure 8-34 shows a sample procedure for clearing complementary PWM mode. Complementary PWM mode Clear bit CMD1 in TFCR to 0, and set channels 3 and 4 to normal operating Clear complementary mode mode. After setting channels 3 and 4 to normal operating mode, wait at least one clock count before clearing bits STR3 and Stop counting...
Page 247 Examples of Complementary PWM Mode: Figure 8-35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows. During each up-and-down counting cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4, and GRB4.
Page 248 Figure 8-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3.
Page 249 In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ.
Page 250 Underflow Overflow TCNT4 H'0001 H'0000 H'FFFF H'0000 Flag not set Set to 1 Buffer transfer signal (BR to GR) Buffer transfer No buffer transfer Figure 8-38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs.
Page 251 GRA3 H'0000 Not allowed Figure 8-39 Changing a General Register Setting by Buffer Transfer (Example 1) — Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a buffer register value outside this range.
Page 252 — Buffer transfer at transition from down-counting to up-counting If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer register value outside this range. Conversely, when a general register value is outside this range, do not transfer a value within this range.
Page 253 — General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range. When a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times.
Page 254: Phase Counting Mode
8.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2.
Page 255 Example of Phase Counting Mode: Figure 8-44 shows an example of operations in phase counting mode. Table 8-9 lists the up-counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 256: Buffering
8.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next.
Page 257 • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times: — When TCNT3 matches GRA3 — When TCNT4 underflows • Reset-synchronized PWM mode The buffer register value is transferred to the general register at compare match A3.
Page 258 Examples of Buffering: Figure 8-49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA.
Page 259 ø TCNT n + 1 Compare match signal Buffer transfer signal Figure 8-50 Compare Match and Buffer Transfer Timing (Example) Downloaded from Elcodis.com electronic components distributor...
Page 260 Figure 8-51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous GRA value is simultaneously transferred to BRA.
Page 261 ø TIOC pin Input capture signal TCNT n + 1 N + 1 Figure 8-52 Input Capture and Buffer Transfer Timing (Example) Downloaded from Elcodis.com electronic components distributor...
Page 262 Figure 8-53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows.
Page 263: Itu Output Timing
8.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER.
Page 264 Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output.
Page 265: Interrupts
8.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 266 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 8-58 shows the timing. ø Input capture signal TCNT Figure 8-58 Timing of Setting of IMFA and IMFB by Input Capture...
Page 267: Clearing Of Status Flags
ø TCNT H'FFFF H'0000 Overflow signal Figure 8-59 Timing of Setting of OVF 8.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared.
Page 268: Interrupt Sources
8.5.3 Interrupt Sources Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1.
Page 269: Usage Notes
8.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8-61.
Page 270 Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 8-62. TCNT word write cycle ø Address TCNT address Internal write signal TCNT input clock TCNT...
Page 271 Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 8-63, which shows an increment pulse occurring in the T state of a byte write to TCNTH.
Page 272 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8-64. General register write cycle ø...
Page 273 Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 8-65. TCNT write cycle ø...
Page 274 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8-66. General register read cycle ø Address GR address Internal read signal Input capture signal...
Page 275 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 276 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8-68. General register write cycle ø...
Page 277 Contention between Buffer Register Write and Input Capture: If a buffer register is used for input capture buffering and an input capture signal occurs in the T state of a write cycle, input capture takes priority and the write to the buffer register is not performed. See figure 8-69.
Page 278 Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized •...
Page 279 ITU Operating Modes Table 8-11 (a) ITU Operating Modes (Channel 0) Register Settings TSNC TMDR TFCR TOCR TOER TIOR0 TCR0 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset...
Page 280 Table 8-11 (b) ITU Operating Modes (Channel 1) Register Settings TSNC TMDR TFCR TOCR TOER TIOR1 TCR1 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset SYNC1 = 1 —...
Page 281 Table 8-11 (c) ITU Operating Modes (Channel 2) Register Settings TSNC TMDR TFCR TOCR TOER TIOR2 TCR2 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset SYNC2 = 1 —...
Page 282 Table 8-11 (d) ITU Operating Modes (Channel 3) Register Settings TSNC TMDR TFCR TOCR TOER TIOR3 TCR3 Comple- Reset- Output Synchro- mentary Synchro- Level Master Clear Clock Operating Mode nization FDIR PWM nized PWM Buffering XTGD Select Enable Select Select Synchronous preset SYNC3 = 1 —...
Page 283 Table 8-11 (e) ITU Operating Modes (Channel 4) Register Settings TSNC TMDR TFCR TOCR TOER TIOR4 TCR4 Comple- Reset- Output Synchro- mentary Synchro- Level Master Clear Clock Operating Mode nization FDIR PWM nized PWM Buffering XTGD Select Enable Select Select Synchronous preset SYNC4 = 1 —...
Page 284: Programmable Timing Pattern Controller
Section 9 Programmable Timing Pattern Controller 9.1 Overview The H8/3032 Series has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 285: Block Diagram
9.1.2 Block Diagram Figure 9-1 shows a block diagram of the TPC. ITU compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR NDRA...
Page 286: Tpc Pins
9.1.3 TPC Pins Table 9-1 summarizes the TPC output pins. Table 9-1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 287: Registers
9.1.4 Registers Table 9-2 summarizes the TPC registers. Table 9-2 TPC Registers Address Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 H'FFD3 Port A data register PADR R/(W) H'00 H'FFD4 Port B data direction register PBDDR H'00 H'FFD6 Port B data register...
Page 288: Register Descriptions
9.2 Register Descriptions 9.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
Page 289: Port B Data Direction Register (Pbddr)
9.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
Page 290: Next Data Register A (Ndra)
9.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 291 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Page 292: Next Data Register B (Ndrb)
9.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 293 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.
Page 294: Next Data Enable Register A (Ndera)
9.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
Page 295: Next Data Enable Register B (Nderb)
9.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
Page 296: Tpc Output Control Register (Tpcr)
9.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Page 297 Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit 6 G3CMS1 G3CMS0 Description TPC output group 3 (TP to TP ) is triggered by compare match in ITU channel 0...
Page 298 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit 2 G1CMS1 G1CMS0 Description TPC output group 1 (TP to TP ) is triggered by compare match in ITU channel 0...
Page 299: Tpc Output Mode Register (Tpmr)
9.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP to TP )
Page 300 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected ITU channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
Page 301: Operation
9.3 Operation 9.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 302: Output Timing
9.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 9-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 303: Normal Tpc Output
9.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 9-4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited). Set the TPC output trigger period.
Page 304 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9-5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT Time H'0000 NDRB PBDR • The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 305: Non-Overlapping Tpc Output
9.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 9-6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set the TPC output trigger period in GRB Set GR values and the non-overlap margin in GRA.
Page 306 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin • The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B.
Page 307: Tpc Output Triggering By Input Capture
9.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 308: Usage Notes
9.4 Usage Notes 9.4.1 Operation of TPC Output Pins to TP are multiplexed with ITU pin functions. When ITU output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 309 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC.
Page 310: Watchdog Timer
As a watchdog timer, it generates a reset signal for the H8/3032 Series chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow.
Page 311: Block Diagram
10.1.2 Block Diagram Figure 10-1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources ø/2 RSTCSR ø/32 ø/64 Reset Reset control Clock ø/128 (internal, external) Clock selector ø/256...
Page 312: Register Configuration
10.1.4 Register Configuration Table 10-2 summarizes the WDT registers. Table 10-2 WDT Registers Address Write Read Name Abbreviation Initial Value H'FFA8 H'FFA8 Timer control/status register TCSR R/(W) H'18 H'FFA9 Timer counter TCNT H'00 H'FFAA H'FFAB Reset control/status register RSTCSR R/(W) H'3F Notes: 1.
Page 313: Register Descriptions
10.2 Register Descriptions 10.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable* up-counter. Initial value Read/Write When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR.
Page 314: Timer Control/Status Register (Tcsr)
10.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Page 315 Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00 Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer.
Page 316: Reset Control/Status Register (Rstcsr)
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (ø), for input to TCNT. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description ø/2 (Initial value) ø/32 ø/64...
Page 317 Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3003 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Page 318: Notes On Register Access
10.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions.
Page 319 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 10-3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 320: Operation
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3032 Series is internally reset for a duration of 518 states.
Page 321: Interval Timer Operation
10.3.2 Interval Timer Operation Figure 10-5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow.
Page 322: Timing Of Setting Of Overflow Flag (Ovf)
10.3.3 Timing of Setting of Overflow Flag (OVF) Figure 10-6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 323: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3032 Series chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
Page 324: Interrupts
10.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 10.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 325 Downloaded from Elcodis.com electronic components distributor...
Page 326: Serial Communication Interface
Section 11 Serial Communication Interface 11.1 Overview The H8/3032 Series has a serial communication interface (SCI). The SCI can communicate in asynchronous mode or synchronous mode, and has a multiprocessor communication function for serial communication among two or more processors.
Page 327 • Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. • Built-in baud rate generator with selectable bit rates •...
Page 328: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the SCI. Internal data bus Module data bus ø Baud rate ø/4 generator Transmit/ ø/16 receive control ø/64 Parity generate Clock Parity check External clock Legend RSR: Receive shift register RDR: Receive data register TSR:...
Page 329: Input/Output Pins
11.1.3 Input/Output Pins The SCI has serial pins for each channel as listed in table 11-1. Table 11-1 SCI Pins Name Abbreviation Function Serial clock pin Input/output SCI clock input/output Receive data pin Input SCI receive data input Transmit data pin Output SCI transmit data output 11.1.4 Register Configuration...
Page 330: Register Descriptions
11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. Initial value Read/Write — — — — — — — — The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 331: Transmit Shift Register (Tsr)
11.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Initial value Read/Write — — — — — — — — The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 332: Serial Mode Register (Smr)
11.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator’s clock source Multiprocessor mode...
Page 333 Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 Description Asynchronous mode (Initial value) Synchronous mode Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 Description 8-bit data...
Page 334 Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit. The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled in asynchronous mode.
Page 335 Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 11.3.3, Multiprocessor Communication Function.
Page 336: Serial Control Register (Scr)
11.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0 These bits select the SCI clock source Transmit end interrupt enable...
Page 337 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value) Transmit-data-empty interrupt request (TXI) is enabled Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then...
Page 338 Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled (Initial value) Receiving enabled Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 339 Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2 TEIE Description Transmit-end interrupt requests (TEI) are disabled* (Initial value) Transmit-end interrupt requests (TEI) are enabled* Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0;...
Page 340: Serial Status Register (Ssr)
11.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer Value of multi- processor bit to be transmitted Multiprocessor bit...
Page 341 The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written.
Page 342 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads ORER while it is set to 1, then writes 0. A receive overrun error occurred [Setting condition] Reception of the next serial data ends when RDRF = 1.
Page 343 Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 Description Receiving is in progress or has ended normally (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0.
Page 344: Bit Rate Register (Brr)
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1 Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its...
Page 345 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode ø (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.16 0.16 0.21 0.16 0.16 0.21 0.16 1200 0.16 –0.70 0.16 2400 0.16 1.14...
Page 346 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800 0.16 0.16...
Page 347 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 14.7456 Bit Rate Error Error Error (bits/s) –0.17 0.70 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800 0.16 0.16 9600 –0.93 0.16...
Page 348 Table 11-4 Examples of Bit Rates and BRR Settings in Synchronous Mode ø (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k —...
Page 349 SMR Settings Clock Source CKS1 CKS0 ø ø/4 ø/16 ø/64 The bit rate error in asynchronous mode is calculated as follows. ø × 10 –1 × 100 Error (%) = (N + 1) × B × 64 × 2 2n–1 Downloaded from Elcodis.com electronic components distributor...
Page 350 Table 11-5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 11-6 and 11-7 indicate the maximum bit rates with external clock input. Table 11-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings ø (MHz) Maximum Bit Rate (bits/s) 62500 2.097152...
Page 351 Table 11-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 352 Table 11-7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 Downloaded from Elcodis.com electronic components distributor...
Page 353: Operation
11.3 Operation 11.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 11-8.
Page 354 Table 11-8 SMR Settings and Serial Communication Formats SCI Communication Format SMR Settings Multi- Stop Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity CHR MP STOP Mode Length Length Asynchronous 8-bit data Absent Absent 1 bit mode 2 bits Present...
Page 355: Operation In Asynchronous Mode
11.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 356 Communication Formats: Table 11-10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 11-10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data...
Page 357 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 11-9. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate.
Page 358 Start of initialization Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after Clear TE and RE bits the setting is made in SCR. to 0 in SCR Select the communication format in SMR.
Page 359 Transmitting Serial Data (Asynchronous Mode): Figure 11-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, Start transmitting check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0.
Page 360 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 361 Receiving Serial Data (Asynchronous Mode): Figure 11-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling and break Start receiving detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify...
Page 362 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 11-7 Sample Flowchart for Receiving Serial Data (2) Downloaded from Elcodis.com electronic components distributor...
Page 363 In receiving, the SCI operates as follows. • The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 364: Multiprocessor Communication
Figure 11-8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt handler request reads data in RDR and Framing error, clears RDRF flag to 0 ERI request 1 frame Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
Page 365 Communication Formats: Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 11-8. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01)
Page 366 Transmitting and Receiving Data Transmitting Multiprocessor Serial Data: Figure 11-10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE...
Page 367 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 368 Receiving Multiprocessor Serial Data: Figure 11-12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read Set MPIE bit to 1 in SCR...
Page 369 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER, PER, and FER flags to 0 in SSR Figure 11-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Downloaded from Elcodis.com electronic components distributor...
Page 370 Figure 11-13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI request RXI handler reads Not own ID, so No RXI request, (multiprocessor RDR data and clears MPIE bit is set...
Page 371: Synchronous Operation
11.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
Page 372 Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 373 Transmitting Serial Data (Synchronous Mode): Figure 11-16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit Start transmitting data in TDR and clear the TDRE flag to 0.
Page 374 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 375 Figure 11-17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt handler request writes data in TDR request request and clears TDRE flag to 0...
Page 376 Receiving Serial Data: Figure 11-18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 377 Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 11-18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. • The SCI synchronizes with serial clock input or output and initializes internally. •...
Page 378 Figure 11-19 shows an example of SCI receive operation. Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt handler request reads data in RDR and request Overrun error, clears RDRF flag to 0...
Page 379 SCI initialization: the transmit data output function of the TxD pin and Initialize receive data input function of the RxD pin are selected, enabling Start transmitting and receiving simultaneous transmitting and receiving. SCI status check and transmit data write: read SSR, check that Read TDRE flag in SSR the TDRE flag is 1, then write transmit data in TDR and clear...
Page 380: Sci Interrupts
11.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11-12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, TEIE, and RIE bits in SCR.
Page 381: Usage Notes
11.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 382 Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Page 383 16 clocks 8 clocks 15 0 15 0 Internal base clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as in equation (1). | D –...
Page 384 Restrictions in Synchronous Mode: When an external clock source is used in synchronous mode, after TDR is reset, wait at least 5 clock counts (5ø) before inputting the transmit clock. If the clock is input four states after the reset of TDR or earlier, an operation error may occur (figure 11-22).
Page 385 Downloaded from Elcodis.com electronic components distributor...
Page 386: A/D Converter
Section 12 A/D Converter 12.1 Overview The H8/3032 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. 12.1.1 Features A/D converter features are listed below. • 10-bit resolution • Eight input channels •...
Page 387: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the A/D converter. On-chip Module data bus data bus 10-bit D/A – ø/8 Comparator Analog Control circuit multi- plexer Sample-and- ø/16 hold circuit ADTRG Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A...
Page 388: Input Pins
12.1.3 Input Pins Table 12-1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter. V is the A/D conversion reference voltage.
Page 389: Register Configuration
12.1.4 Register Configuration Table 12-2 summarizes the A/D converter’s registers. Table 12-2 A/D Converter Registers Address Name Abbreviation Initial Value H'FFE0 A/D data register A (high) ADDRAH H'00 H'FFE1 A/D data register A (low) ADDRAL H'00 H'FFE2 A/D data register B (high) ADDRBH H'00 H'FFE3...
Page 390: Register Descriptions
12.2 Register Descriptions 12.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ADDRn — — — — — — Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 391: A/D Control/Status Register (Adcsr)
12.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts...
Page 392 Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 Description [Clearing condition] (Initial value) Cleared by reading ADF while ADF = 1, then writing 0 in ADF [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Page 393 Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 12.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description Single mode (Initial value) Scan mode Bit 3—Clock Select (CKS): Selects the A/D conversion time.
Page 394: A/D Control Register (Adcr)
12.2.3 A/D Control Register (ADCR) TRGE — — — — — — — Initial value Read/Write — — — — — — — Reserved bits Trigger enable Enables or disables external triggering of A/D conversion ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion.
Page 395: Cpu Interface
12.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
Page 396: Operation
12.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 12.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 397 ADIE A/D conversion starts ADST Clear Clear State of channel 0 Idle (AN ) State of channel 1 Idle A/D conversion Idle A/D conversion Idle (AN ) State of channel 2 Idle (AN ) State of channel 3 Idle (AN ) ADDRA Read conversion result Read conversion result...
Page 398: Scan Mode (Scan = 1)
12.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 399 Continuous A/D conversion Clear ADST Clear A/D conversion time State of channel 0 Idle Idle A/D conversion Idle A/D conversion (AN ) State of channel 1 Idle A/D conversion Idle A/D conversion Idle (AN ) State of channel 2 Idle A/D conversion Idle (AN )
Page 400: Input Sampling And A/D Conversion Time
12.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 12-5 shows the A/D conversion timing.
Page 401: External Trigger Input Timing
Table 12-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 12.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 402: Interrupts
12.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 12.6 Usage Notes When using the A/D converter, note the following points: Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ≤...
Page 403 Downloaded from Elcodis.com electronic components distributor...
Page 404: Ram
Section 13 RAM 13.1 Overview The H8/3032 has 2 kbytes of on-chip static RAM, the H8/3031 has 1 kbyte, and the H8/3030 has 512 bytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable for rapid data transfer.
Page 405: Register Configuration
13.1.2 Register Configuration The on-chip RAM is controlled by the system control register (SYSCR). Table 13-1 gives the address and initial value of SYSCR. Table 13-1 RAM Control Register Address* Name Abbreviation Initial Value H'FFF2 System control register SYSCR H'0B Note: * Lower 16 bits of the address Downloaded from Elcodis.com...
Page 406: System Control Register (Syscr)
13.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable bit Enables or disables on-chip RAM Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 407: Operation
13.3 Operation 13.3.1 Mode 1 When the RAME bit is set to 1 in mode 1, accesses to addresses H'FF710 to H'FFF0F of the H8/3032, to addresses H'FFB10 to H'FFF0F of the H8/3031, and to addresses H'FFD10 to H'FFF0F of the H8/3030 are directed to the on-chip RAM space. When the RAME bit is cleared to 0, accesses to such addresses are directed to the off-chip address space.
Page 408: Rom
Section 14 ROM 14.1 Overview The H8/3030 has 16 kbytes of on-chip ROM, the H8/3031 has 32 kbytes, and the H8/3032 has 64 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling rapid data transfer.
Page 409: Prom Mode
14.2 PROM Mode 14.2.1 PROM Mode Setting In PROM mode, the H8/3032 version with on-chip PROM suspends its microcontroller functions, enabling the on-chip PROM to be programmed. The programming method is the same as for the HN27C101, except that page programming is not supported. Table 14-1 indicates how to select PROM mode.
Page 410 H8/3032 PROM Socket FP-80A, TFP-80C HN27C101 (32 pins) RESO STBY Legend Programming voltage (12.5 V) EO to EO : Data input/output to EA : Address input Output enable Chip enable Note: Pins not shown in this diagram should be left open. PGM: Program Figure 14-2 Socket Adapter Pin Assignments...
Page 411 Address in Address in MCU mode PROM mode H'0000 H'0000 On-chip PROM H'FFFF H'FFFF Missing area H'1FFFF H'1FFFF Note: If read in PROM mode, this area returns H'FF output data. Figure 14-3 H8/3032 Memory Map in PROM Mode Downloaded from Elcodis.com electronic components distributor...
Page 412: Programming
14.3 Programming Table 14-3 indicates how to select the program, verify, and other modes in PROM mode. Table 14-3 Mode Selection in PROM Mode Pins Mode to EO to EA Program Data input Address input Verify Data output Address input Program inhibited High impedance Address input...
Page 413 Start Set programming/verification mode = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V Address = 0 n = 0 → n + 1 < Program with t = 0.2 ms ±5% → Address + 1 address Verification OK? Program with t = 0.2n ms Last address?
Page 414 Table 14-4 DC Characteristics —Preliminary— (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Test Conditions Input high to EO — + 0.3 voltage to EA OE, CE, PGM Input low to EO...
Page 415 Table 14-5 AC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) Item Symbol Unit Test Conditions Address setup time — — µs Figure 14-5 OE setup time — — µs Data setup time —...
Page 416 Program Verify Address Data Input data Output data Note: is defined by the value given in the flowchart. Figure 14-5 PROM Program/Verify Timing Downloaded from Elcodis.com electronic components distributor...
Page 417: Programming Precautions
) in PROM mode is 12.5 V. Applied voltages in excess of the rated values can permanently destroy the chip. Be particularly careful about the PROM programmer’s overshoot characteristics. If the PROM programmer is set to Hitachi HN27C101 specifications, V will be 12.5 V. •...
Page 418: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 419 Downloaded from Elcodis.com electronic components distributor...
Page 420: Clock Pulse Generator
Section 15 Clock Pulse Generator 15.1 Overview The H8/3032 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø) and other internal clock signals (ø/2 to ø/4096). The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, and prescalers.
Page 421: Oscillator Circuit
15.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 15.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 15-2. The damping resistance Rd should be selected according to table 15-1.
Page 422 When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8/3032 Series XTAL EXTAL Figure 15-4 Example of Incorrect Board Design Downloaded from Elcodis.com...
Page 423: External Clock Input
15.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 15-5. In example b, the clock should be held high in standby mode. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. EXTAL External clock input XTAL...
Page 424 External Clock: The external clock frequency should be equal to the system clock frequency (ø). Table 15-3 and figure 15-6 indicate the clock timing. Table 15-3 Clock Timing 2.7 V to 5.5 V = 5.0 V ± 10% Item Symbol Unit Test Conditions External clock rise —...
Page 425: Duty Adjustment Circuit
15.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (ø). 15.4 Prescalers The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096). Downloaded from Elcodis.com electronic components distributor...
Page 426: Power-Down State
Section 16 Power-Down State 16.1 Overview The H8/3032 Series has a power-down state that greatly reduces power consumption by halting CPU functions. The power-down state includes the following three modes: • Sleep mode • Software standby mode • Hardware standby mode Table 16-1 indicates the methods of entering and exiting these power-down modes and the status of the CPU and on-chip supporting modules in each mode.
Page 427: Register Configuration
16.2 Register Configuration The H8/3032 Series’ system control register (SYSCR) controls the power-down state. Table 16-2 summarizes this register. Table 16-2 Control Register Address* Name Abbreviation Initial Value H'FFF2 System control register SYSCR H'0B Note: * Lower 16 bits of the address.
Page 428 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description SLEEP instruction causes transition to sleep mode...
Page 429: Sleep Mode
16.3 Sleep Mode 16.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained.
Page 430: Software Standby Mode
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire H8/3032 Series chip. The RES signal must be held low long enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Page 431: Selection Of Waiting Time For Exit From Software Standby Mode
16.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR should be set as follows. Crystal Resonator: Set STS2 to STS0 so that the waiting time (for the clock to stabilize) is at least 8 ms.
Page 432: Sample Application Of Software Standby Mode
16.4.4 Sample Application of Software Standby Mode Figure 16-1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 433: Hardware Standby Mode
16.5 Hardware Standby Mode 16.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained.
Page 434: Electrical Characteristics
Section 17 Electrical Characteristics 17.1 Absolute Maximum Ratings Table 17-1 lists the absolute maximum ratings. Table 17-1 Absolute Maximum Ratings —Preliminary— Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.5 Input voltage (except port 7) –0.3 to V +0.3 Input voltage (port 7)
Page 435: Electrical Characteristics
17.2 Electrical Characteristics 17.2.1 DC Characteristics Table 17-2 lists the DC characteristics. Table 17-3 lists the permissible output currents. Table 17-2 DC Characteristics Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications),...
Page 436 Table 17-2 DC Characteristics (cont) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 437 Table 17-2 DC Characteristics (cont) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 438 Table 17-2 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 439 Table 17-2 DC Characteristics (cont) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 440 Table 17-2 DC Characteristics (cont) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 441 Table 17-2 DC Characteristics (cont) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 442 Table 17-2 DC Characteristics (cont) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 443 Table 17-3 Permissible Output Currents (1) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 444 H8/3032 Series 2 kΩ Port Darlington pair Figure 17-1 Darlington Pair Drive Circuit (Example) H8/3032 Series Ports 5 and B 600 Ω Figure 17-2 LED Drive Circuit (Example) Downloaded from Elcodis.com electronic components distributor...
Page 445: Ac Characteristics
17.2.2 AC Characteristics Bus timing parameters are listed in table 17-4. Control signal timing parameters are listed in table 17-5. Timing parameters of the on-chip supporting modules are listed in table 17-6. Table 17-4 Bus Timing (1) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV...
Page 446 Table 17-4 Bus Timing (cont) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 447 Note: At 8 MHz, the times below depend as indicated on the clock cycle time. = 1.5 × t = 1.0 × t – 78 (ns) – 40 (ns) ACC1 WSW1 = 2.5 × t = 1.5 × t – 83 (ns) –...
Page 448 Table 17-5 Control Signal Timing Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Condition B: V = 3.0 V to 5.5 V, AV...
Page 449 Table 17-6 Timing of On-Chip Supporting Modules Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 450 Table 17-6 Timing of On-Chip Supporting Modules (cont) Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Condition B: V...
Page 451 C = 90 pF: ports 5, 6, 8, to A to D AS RD WR ø, H8/3032 Series C = 30 pF: ports 9, A, B output pin Ω R = 2.4 k Ω R = 12 k Input/output timing measurement levels •...
Page 452: A/D Conversion Characteristics
17.2.3 A/D Conversion Characteristics Table 17-7 lists the A/D conversion characteristics. Table 17-7 A/D Converter Characteristics Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø...
Page 453: Operational Timing
17.3 Operational Timing This section shows timing diagrams. 17.3.1 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 17-4 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 17-5 shows the timing of the external three-state access cycle.
Page 454 ø to A ACC3 ACC3 (read) ACC1 to D (read) WR (write) WSW1 WDS1 to D (write) Figure 17-4 Basic Bus Cycle: Two-State Access Downloaded from Elcodis.com electronic components distributor...
Page 455 ø to A ACC4 ACC4 RD (read) ACC2 to D (read) WSW2 WR (write) WDS2 to D (write) Figure 17-5 Basic Bus Cycle: Three-State Access Downloaded from Elcodis.com electronic components distributor...
Page 456 ø to A RD (read) to D (read) WR (write) to D (write) WAIT Figure 17-6 Basic Bus Cycle: Three-State Access with One Wait State Downloaded from Elcodis.com electronic components distributor...
Page 457: Control Signal Timing
17.3.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 17-7 shows the reset input timing. • Reset output timing Figure 17-8 shows the reset output timing. • Interrupt input timing Figure 17-9 shows the input timing for NMI and IRQ to IRQ ø...
Page 458 ø NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (I = 0 to 4) NMIW (J = 0 to 2) Figure 17-9 Interrupt Input Timing Downloaded from Elcodis.com electronic components distributor...
Page 459: Clock Timing
17.3.3 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 17-10 shows the oscillator settling timing. ø STBY OSC1 OSC1 Figure 17-10 Oscillator Settling Timing 17.3.4 TPC and I/O Port Timing TPC and I/O port timing is shown as follows. ø...
Page 460: Itu Timing
17.3.5 ITU Timing ITU timing is shown as follows: • ITU input/output timing Figure 17-12 shows the ITU input/output timing. • ITU external clock input timing Figure 17-13 shows the ITU external clock input timing. ø TOCD Output compare TICS Input capture Notes: 1.
Page 461: Sci Input/Output Timing
17.3.6 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 17-14 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 17-15 shows the SCI input/output timing in synchronous mode. SCKW SCKR SCKR SCYC...
Page 462: Appendix A Instruction Set
Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 463 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Downloaded from Elcodis.com electronic components distributor...
Page 464 Table A-1 Instruction Set Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — Rs8 → Rd8 MOV.B Rs, Rd — — 0 —...
Page 465 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W @aa:24 → Rd16 MOV.W @aa:24, Rd — — 0 — W Rs16 → @ERd MOV.W Rs, @ERd — — 0 —...
Page 466 4 — — 0 — ERn32 → @SP MOVFPE @aa:16, Cannot be used in the Cannot be used in the H8/3032 H8/3032 Series Series MOVTPE Rs, Cannot be used in the Cannot be used in the H8/3032 @aa:16 H8/3032 Series...
Page 467 able A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — DAA Rd Rd8 decimal adjust —...
Page 468 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W ERd32 ÷ Rs16 →ERd32 DIVXU. W Rs, ERd — — 6 7 — — (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷...
Page 469 Table A-1 Instruction Set (cont) Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — 0 — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — 0 —...
Page 470 Table A-1 Instruction Set (cont) Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd —...
Page 471 Table A-1 Instruction Set (cont) Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 472 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 —...
Page 473 Table A-1 Instruction Set (cont) Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z BRA d:8 (BT d:8) — Always — — — — — — If condition is true then BRA d:16 (BT d:16) —...
Page 474 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z Z ∨ (N⊕V) BLE d:8 — If condition — — — — — — is true then BLE d:16 —...
Page 475 Table A-1 Instruction Set (cont) System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z — PC → @–SP TRAPA #x:2 2 — — — — — — CCR → @–SP ...
Page 476 Table A-1 Instruction Set (cont) Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z — if R4L ≠ 0 then EEPMOV. B 4 — — — — — — repeat @R5 → @R6 4n *2 R5+1 →...
Page 477: Operating Code Maps
A.2 Operation Code Maps Table A-2 Operation Code Map (1) Instruction code: 1st byte 2nd byte Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. Table A.2 Table A.2 Table A.2 Table A.2 XORC ANDC...
Page 478 Table A-2 Operation Code Map (2) Instruction code: 1st byte 2nd byte AH AL Table A.2 Table A.2 Table A.2 LDC/STC SLEEP ADDS ADDS SHLL SHLL SHAL SHAL SHLR SHLR SHAR SHAR ROTXL ROTXL ROTL ROTL ROTXR ROTR ROTXR ROTR EXTU EXTU EXTS...
Page 479 Table A-2 Operation Code Map (3) 1st byte 2nd byte 3rd byte 4th byte Instruction code: Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. ALBH BLCH 01406 01C05 MULXS MULXS 01D05 DIVXS DIVXS...
Page 480: Number Of States Required For Execution
A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A-3 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-2 indicates the number of states required per cycle according to the bus size.
Page 481 Table A-2 Number of States per Cycle Access Conditions External Device On-Chip Sup- porting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read Stack operation Byte data access...
Page 482 Table A-3 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd ADDX...
Page 483 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
Page 484 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd...
Page 485 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd...
Page 486 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd 2 MOV.B @(d:24, ERs), Rd 4 MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd...
Page 487 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOVFPE MOVFPE @aa:16, Rd MOVTPE MOVTPE Rs, @aa:16 MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd...
Page 488 XORC XORC #xx:8, CCR Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. Not available in the H8/3032 Series. Downloaded from Elcodis.com electronic components distributor...
Page 489: Appendix B Register Field
Appendix B Register Field B.1 Register Addresses and Bit Names Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'1C H'1D H'1E H'1F H'20 —...
Page 490 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'3B — — — — — — — — — H'3C —...
Page 491 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'60 TSTR — — — STR4 STR3 STR2 STR1 STR0 (all channels) H'61 TSNC...
Page 492 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'82 TCR3 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU channel 3 H'83 TIOR3...
Page 493 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'A0 TPMR — — — — G3NOV G2NOV G1NOV G0NOV H'A1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0...
Page 494 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'B8 — — — — — — — — — H'B9 —...
Page 495 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'D8 P2PCR PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2...
Page 496 (Continued from preceding page) Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'F0 — — — — — — — — — H'F1 MDCR —...
Page 497: Register Descriptions
B.2 Register Descriptions Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR Timer Start Register H'60 ITU (all channels) numbers Initial bit — — — STR4 STR3 STR2 STR1 STR0 values Initial value Names of the Read/Write —...
Page 498 TSTR—Timer Start Register H'60 ITU (all channels) — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — — Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting...
Page 499 TSNC—Timer Synchro Register H'61 ITU (all channels) — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized...
Page 500 TMDR—Timer Mode Register H'62 ITU (all channels) — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value Read/Write — PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally...
Page 501 TFCR—Timer Function Control Register H'63 ITU (all channels) — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — — Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally...
Page 502 TCR0—Timer Control Register 0 H'64 ITU0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 TCNT Clock Source Internal clock: ø Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input...
Page 503 TIOR0—Timer I/O Control Register 0 H'65 ITU0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 GRA Function GRA is an output No output at compare match compare register 0 output at GRA compare match...
Page 504 TIER0—Timer Interrupt Enable Register 0 H'66 ITU0 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA is disabled 1 IMIA interrupt requested by IMFA is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB is disabled 1 IMIB interrupt requested by IMFB is enabled...
Page 505 TSR0—Timer Status Register 0 H'67 ITU0 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] TCNT = GRA when GRA functions as a compare match register.
Page 506 TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 Initial value Read/Write Output compare or input capture register TCR1—Timer Control Register 1 H'6E...
Page 507 TIOR1—Timer I/O Control Register 1 H'6F ITU1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 H'70 ITU1 — — — — —...
Page 508 GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 H'78 ITU2...
Page 509 TIOR2—Timer I/O Control Register 2 H'79 ITU2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. Downloaded from Elcodis.com electronic components distributor...
Page 510 TIER2—Timer Interrupt Enable Register 2 H'7A ITU2 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Note: Bit functions are the same as for ITU0. TSR2—Timer Status Register 2 H'7B ITU2 — — —...
Page 511 GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR3—Timer Control Register 3 H'82 ITU3...
Page 512 TIER3—Timer Interrupt Enable Register 3 H'84 ITU3 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Note: Bit functions are the same as for ITU0. TSR3—Timer Status Register 3 H'85 ITU3 — — —...
Page 513 GRA3 H/L—General Register A3 H/L H'88, H'89 ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3...
Page 514 TOER—Timer Output Enable Register H'90 ITU (all channels) — — EXB4 EXA4 Initial value Read/Write — — Master enable TIOCA3 0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA4 0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings...
Page 515 TOCR—Timer Output Control Register H'91 ITU (all channels) — — — XTGD — — OLS4 OLS3 Initial value Read/Write — — — — — Output level select 3 0 TIOCB , TOCXA , and TOCXB outputs are inverted 1 TIOCB , TOCXA , and TOCXB outputs are not inverted Output level select 4 0 TIOCA , TIOCA , and TIOCB outputs are inverted 1 TIOCA , TIOCA , and TIOCB outputs are not inverted...
Page 516 TCR4—Timer Control Register 4 H'92 ITU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR4—Timer I/O Control Register 4 H'93 ITU4 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value...
Page 517 TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4...
Page 518 BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. TPMR—TPC Output Mode Register H'A0 — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Group 0 non-overlap 0 Normal TPC output in group 0.
Page 519 TPCR—TPC Output Control Register H'A1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 ITU Channel Selected as Output Trigger TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 0 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 1 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 2 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 3...
Page 520 NDERB—Next Data Enable Register B H'A2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 Description TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP to TP are enabled (NDR15 to NDR8 are transferred to PB to PB )
Page 521 NDRB—Next Data Register B H'A4/H'A6 • Same output trigger for TPC output groups 2 and 3 Address H'FFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Next output data for Next output data for TPC output group 3 TPC output group 2 Address H'FFA6 —...
Page 522 NDRA—Next Data Register A H'A5/H'A7 • Same output trigger for TPC output groups 0 and 1 Address H'FFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Next output data for Next output data for TPC output group 1 TPC output group 0 Address H'FFA7 —...
Page 523 TCSR—Timer Control/Status Register H'A8 — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Timer enable Clock select 2 to 0 0 Timer disabled ø/2 • TCNT is initialized to H'00 and halted ø/32 1 Timer enabled ø/64 • TCNT is counting ø/128 •...
Page 524 TCNT—Timer Counter H'A9 (read), H'A8 (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) WRST RSTOE — — — — — — Initial value Read/Write R/(W) — — — — — — Reset output enable 0 Reset signal is not output externally 1 Reset signal is output externally Watchdog timer reset 0 [Clearing condition]...
Page 525 SMR—Serial Mode Register H'B0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source ø clock Multiprocessor mode ø/4 clock 0 Multiprocessor function disabled ø/16 clock 1 Multiprocessor format selected ø/64 clock Stop bit length 0 One stop bit 1 Two stop bits...
Page 526 BRR—Bit Rate Register H'B1 Initial value Read/Write Serial communication bit rate setting Downloaded from Elcodis.com electronic components distributor...
Page 527 SCR—Serial Control Register H'B2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Bit 1 Bit 2 CKE1 CKE2 Clock Selection and Output Asynchronous mode Internal clock, SCK pin available for generic input Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode Internal clock, SCK pin used for clock output Synchronous mode...
Page 528 TDR—Transmit Data Register H'B3 Initial value Read/Write Serial transmit data Downloaded from Elcodis.com electronic components distributor...
Page 529 SSR—Serial Status Register H'B4 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit Multiprocessor bit transfer Multiprocessor bit value in Multiprocessor bit value in receive data is 0 transmit data is 0 Multiprocessor bit value in Multiprocessor bit value in receive data is 1 transmit data is 1...
Page 530 RDR—Receive Data Register H'B5 Initial value Read/Write Serial receive data P1DDR—Port 1 Data Direction Register H'C0 Port 1 Initial value Read/Write Port 1 input/output select 0 Generic input 1 Generic output P2DDR—Port 2 Data Direction Register H'C1 Port 2 Initial value Read/Write Port 2 input/output select 0 Generic input...
Page 531 P1DR—Port 1 Data Register H'C2 Port 1 Initial value Read/Write Data for port 1 pins P2DR—Port 2 Data Register H'C3 Port 2 Initial value Read/Write Data for port 2 pins P3DDR—Port 3 Data Direction Register H'C4 Port 3 Initial value Read/Write Port 3 input/output select 0 Generic input...
Page 532 P3DR—Port 3 Data Register H'C6 Port 3 Initial value Read/Write Data for port 3 pins P5DDR—Port 5 Data Direction Register H'C8 Port 5 — — — — P5 DDR P5 DDR P5 DDR P5 DDR Initial value Read/Write — — —...
Page 533 P6DDR—Port 6 Data Direction Register H'C9 Port 6 — — — — Initial value Read/Write — Port 6 input/output select 0 Generic input 1 Generic output P5DR—Port 5 Data Register H'CA Port 5 — — — — Initial value Read/Write —...
Page 534 P8DDR—Port 8 Data Direction Register H'CD Port 8 — — — P8 DDR P8 DDR P8 DDR P8 DDR P8 DDR Initial value Read/Write — — — Port 8 input/output select 0 Generic input 1 Generic output P7DR—Port 7 Data Register H'CE Port 7 Initial value...
Page 535 P9DDR—Port 9 Data Direction Register H'D0 Port 9 — — — P9 DDR — P9 DDR — P9 DDR Initial value Read/Write — — Port 9 input/output select 0 Generic input 1 Generic output PADDR—Port A Data Direction Register H'D1 Port A PA DDR PA DDR...
Page 536 PADR—Port A Data Register H'D3 Port A Initial value Read/Write Data for port A pins PBDDR—Port B Data Direction Register H'D4 Port B PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B input/output select 0 Generic input...
Page 537 P2PCR—Port 2 Input Pull-Up Control Register H'D8 Port 2 P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
Page 538 ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 — — — — — — Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 — — — —...
Page 539 ADCR—A/D Control Register H'E9 TRGE — — — — — — — Initial value Read/Write — — — — — — — Trigger enable 0 A/D conversion cannot be externally triggered ADTRG 1 A/D conversion starts at the fall of the external trigger signal ( Downloaded from Elcodis.com electronic components distributor...
Page 540 ADCSR—A/D Control/Status Register H'E8 ADIE ADST SCAN Initial value Read/Write R/(W) Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Selection Selection Description Single Mode Scan Mode Scan mode AN , AN 0 Single mode...
Page 541 ASTCR—Access State Control Register H'ED Bus controller AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Area 7 to 0 access state control Bits 7 to 0 AST7 to AST0 Number of States in Access Cycle Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas WCR—Wait Control Register H'EE...
Page 542 WCER—Wait Controller Enable Register H'EF Bus controller WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0 Initial value Read/Write Wait state controller enable 7 to 0 0 Wait-state control is disabled (pin wait mode 0) 1 Wait-state control is enabled MDCR—Mode Control Register H'F1 System control —...
Page 543 SYSCR—System Control Register H'F2 System control SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit...
Page 544 ISCR—IRQ Sense Control Register H'F4 Interrupt controller — — — IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control 0 Interrupts are requested when IRQ to IRQ inputs are low 1 Interrupts are requested by falling-edge input at IRQ to IRQ IER—IRQ Enable Register H'F5 Interrupt controller...
Page 545 ISR—IRQ Status Register H'F6 Interrupt controller — — — IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * IRQ to IRQ flags Bits 4 to 0 IRQ4F to IRQ0F Setting and Clearing Conditions [Clearing conditions] Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
Page 546 IPRA—Interrupt Priority Register A H'F8 Interrupt controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 547: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Software standby Mode 2/3 Hardware standby Mode 1/2/3 Reset WP1D Mode 2/3 Reset Mode 1 WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 n = 0 to 7 Set priority Figure C-1 Port 1 Block Diagram Downloaded from...
Page 548: Port 2 Block Diagram
C.2 Port 2 Block Diagram Reset Software standby RP2P Mode 2/3 WP2P Hardware standby Mode 1/2/3 Reset WP2D Mode 2/3 Reset Mode 1 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2: Read port 2 n = 0 to 7 Set priority...
Page 549: Port 3 Block Diagram
C.3 Port 3 Block Diagram Reset Hardware Mode 2/3 standby Write to external address WP3D Reset Mode 2/3 Mode 1 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7 Figure C-3 Port 3 Block Diagram Downloaded from Elcodis.com...
Page 550: Port 5 Block Diagram
C.4 Port 5 Block Diagram Reset Software standby Mode 2/3 RP5P Hardware standby WP5P Mode 1 to mode 3 Reset WP5D Mode 2/3 Reset Mode 1 WP5P: Write to P5PCR RP5P: Read P5PC4 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 n = 0 to 3...
Page 551: Port 6 Block Diagram
C.5 Port 6 Block Diagram Reset Bus controller Mode 2/3 WP6D WAIT Reset input enable Bus controller WAIT input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-5 (a) Port 6 Block Diagram (Pin P6 Downloaded from Elcodis.com electronic components distributor...
Page 552 Software standby Mode 2/3 Hardware standby Reset WP6D Reset Mode 2/3 Mode 1 AS output RD output WR output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 5 to 3 Figure C-5 (b) Port 6 Block Diagram (Pins P6 to P6 Downloaded from Elcodis.com...
Page 553: Port 7 Block Diagram
C.6 Port 7 Block Diagram A/D converter Input enable Analog input RP7: Read port 7 n = 0 to 7 Figure C-6 (a) Port 7 Block Diagram Downloaded from Elcodis.com electronic components distributor...
Page 554: Port 8 Block Diagram
C.7 Port 8 Block Diagram Reset WP8D Reset Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C-7 Port 8 Block Diagram (Pin P8 Downloaded from Elcodis.com electronic components distributor...
Page 555: Port 9 Block Diagram
C.8 Port 9 Block Diagram Reset WP9D Reset Output enable Serial data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-8 (a) Port 9 Block Diagram (Pin P9 Downloaded from Elcodis.com electronic components distributor...
Page 556 Reset WP9D Input enable Reset Serial data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-8 (b) Port 9 Block Diagram (Pins P9 , P9 Downloaded from Elcodis.com electronic components distributor...
Page 557 Reset WP9D Clock input enable Reset Clock output enable Clock output Clock input WP9D: Write to P9DDR WP9: Write to port 9 Interrupt controller RP9: Read port 9 n = 4, 5 input Figure C-8 (c) Port 9 Block Diagram (Pin P9 Downloaded from Elcodis.com electronic components distributor...
Page 558: Port A Block Diagram
C.9 Port A Block Diagram Reset WPAD Reset TPC output enable Next data Output trigger Counter input clock WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0, 1 Figure C-9 (a) Port A Block Diagram (Pins PA , PA Downloaded from Elcodis.com...
Page 559 Reset WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input Counter input clock WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 2, 3 Figure C-9 (b) Port A Block Diagram (Pins PA , PA Downloaded from Elcodis.com...
Page 560 Reset WPAD Reset TPC output enable Next data Output trigger Output enable Compare match input Input capture input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 4 to 7 Figure C-9 (c) Port A Block Diagram (Pins PA , PA Downloaded from Elcodis.com...
Page 561: Port B Block Diagram
C.10 Port B Block Diagram Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 0 to 3 Figure C-10 (a) Port B Block Diagram (Pins PB to PB Downloaded from...
Page 562 Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 4 to 5 Figure C-10 (b) Port B Block Diagram (Pins PB , PB Downloaded from Elcodis.com...
Page 563 Reset WPBD Reset TPC output enable Next data Output trigger WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C-10 (c) Port B Block Diagram (Pin PB Downloaded from Elcodis.com electronic components distributor...
Page 564 Reset WPBD Reset TPC output enable Next data Output trigger A/D converter ADTRG input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C-10 (d) Port B Block Diagram (Pin PB Downloaded from Elcodis.com electronic components distributor...
Page 565 Downloaded from Elcodis.com electronic components distributor...
Page 566: Appendix D Pin States
Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Hardware Software Program Reset Standby Standby Sleep Execution Name Mode State Mode Mode Mode Sleep Mode ø — Clock output T Clock output Clock output to P1 keep keep Input port...
Page 567: Pin States At Reset
Table D-1 Port States (cont) Hardware Software Program Reset Standby Standby Sleep Execution Name Mode State Mode Mode Mode Sleep Mode to P7 1 to 3 Input port to P8 1 to 3 keep keep I/O port , P9 1 to 3 keep keep I/O port...
Page 568 D.2 Pin States at Reset State: Figure D-1 is a timing diagram for the case in which RES goes low during the Reset in T state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
Page 569 State: Figure D-2 is a timing diagram for the case in which RES goes low during the Reset in T state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
Page 570 State: Figure D-3 is a timing diagram for the case in which RES goes low during the Reset in T state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus outputs are held during the T state.The same timing applies when a reset occurs in the T...
Page 571: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
Page 572: Appendix F Package Dimensions
Appendix F Package Dimensions Figure F-1 shows the FP-80A package dimensions of the H8/3032 Series, and figure F-2 shows the TFP-80C package dimensions. Unit: mm 17.2 ± 0.3 14.0 0.30 ± 0.10 0.12 M 1.60 0 – 5 ° 0.10 0.80 ±...

Hitachi H8/3032 Series Hardware Manual

Quick Links

Related Manuals for Hitachi H8/3032 Series

Summary of Contents for Hitachi H8/3032 Series