Page 1 Hitachi Single-Chip Microcomputer H8/3035 Series H8/3035, H8/3034, H8/3033 Hardware Manual...
Page 2 Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.
Page 3: Table Of Contents
Contents Contents ......................i Preface ......................1 Section 1 Overview ..................3 1.1 Overview ........................3 1.2 Block Diagram........................ 7 1.3 Pin Description ....................... 8 1.3.1 Pin Arrangement....................8 1.3.2 Pin Functions ..................... 9 1.4 Pin Functions ........................12 Section 2 CPU....................17 2.1 Overview ........................
Page 4 2.8.4 Exception-Handling Sequences................48 2.8.5 Reset State......................49 2.8.6 Power-Down State ..................... 49 2.9 Basic Operational Timing ....................50 2.9.1 Overview ......................50 2.9.2 On-Chip Memory Access Timing ..............50 2.9.3 On-Chip Supporting Module Access Timing............51 2.9.4 Access to External Address Space..............52 Section 3 MCU Operating Modes ..............
Page 5 5.2 Register Descriptions ...................... 72 5.2.1 System Control Register (SYSCR)..............72 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ..........74 5.2.3 IRQ Status Register (ISR) .................. 79 5.2.4 IRQ Enable Register (IER) ................80 5.2.5 IRQ Sense Control Register (ISCR) ..............80 5.3 Interrupt Sources......................
Page 6 Section 7 I/O Ports..................117 7.1 Overview ........................117 7.2 Port 1 ..........................120 7.2.1 Overview ......................120 7.2.2 Register Descriptions..................120 7.2.3 Pin Functions in Each Mode ................122 7.3 Port 2 ..........................123 7.3.1 Overview ......................123 7.3.2 Register Descriptions..................123 7.3.3 Pin Functions in Each Mode ................
Page 7 7.11.3 Pin Functions ....................156 Section 8 16-Bit Integrated Timer Unit (ITU) ..........161 8.1 Overview ........................161 8.1.1 Features ......................161 8.1.2 Block Diagrams ....................164 8.1.3 Input/Output Pins....................169 8.1.4 Register Configuration..................170 8.2 Register Descriptions ...................... 172 8.2.1 Timer Start Register (TSTR)................172 8.2.2 Timer Synchro Register (TSNC)................
Page 8 Section 9 Programmable Timing Pattern Controller ........253 9.1 Overview ........................253 9.1.1 Features ......................253 9.1.2 Block Diagram ....................254 9.1.3 TPC Pins......................255 9.1.4 Registers......................256 9.2 Register Descriptions ...................... 257 9.2.1 Port A Data Direction Register (PADDR) ............257 9.2.2 Port A Data Register (PADR) ................
Page 9 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)........ 286 10.4 Interrupts........................287 10.5 Usage Notes ........................287 Section 11 Serial Communication Interface............289 11.1 Overview ........................289 11.1.1 Features ......................289 11.1.2 Block Diagram....................290 11.1.3 Input/Output Pins..................... 291 11.1.4 Register Configuration..................
Page 10 12.5 Interrupts ........................361 12.6 Usage Notes........................361 Section 13 RAM .................... 363 13.1 Overview ........................363 13.1.1 Block Diagram....................363 13.1.2 Register Configuration..................364 13.2 System Control Register (SYSCR) ................364 13.3 Operation ........................365 13.3.1 Mode 1 ......................365 13.3.2 Mode 2 ......................
Page 11 16.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode. 387 16.4.4 Sample Application of Software Standby Mode ..........387 16.4.5 Usage Note ...................... 388 16.5 Hardware Standby Mode....................388 16.5.1 Transition to Hardware Standby Mode............. 388 16.5.2 Exit from Hardware Standby Mode..............389 16.5.3 Timing for Hardware Standby Mode..............
Page 12 TIER1—Timer Interrupt Enable Register 1 H'70 ITU1..........463 TSR1—Timer Status Register 1 H'71 ITU1 ..............463 TCNT1 H/L—Timer Counter 1 H/L H'72, H'73 ITU1 ..........463 GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 ..........464 GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1..........464 TCR2—Timer Control Register 2 H'78 ITU2 ..............
Page 13 SCR—Serial Control Register H'B2 SCI..............485 TDR—Transmit Data Register H'B3 SCI..............486 SSR—Serial Status Register H'B4 SCI ................ 487 RDR—Receive Data Register H'B5 SCI ..............488 P1DDR—Port 1 Data Direction Register H'C0 Port 1 ..........488 P2DDR—Port 2 Data Direction Register H'C1 Port 2 ..........488 P1DR—Port 1 Data Register H'C2 Port 1 ..............
Page 14 Appendix C I/O Port Block Diagrams ............507 C.1 Port 1 Block Diagram..................... 507 C.2 Port 2 Block Diagram..................... 508 C.3 Port 3 Block Diagram..................... 509 C.4 Port 5 Block Diagram..................... 510 C.5 Port 6 Block Diagram....................511 C.6 Port 7 Block Diagram..................... 513 C.7 Port 8 Block Diagram.....................
Page 15: Preface
Preface...
Page 17: Section 1 Overview
(SCI), an A/D converter, I/O ports, and other facilities. The H8/3035 Series consists of three models: the H8/3035 with 256 kbytes of ROM and 4 kbytes of RAM, the H8/3034 with 192 kbytes of ROM and 4 kbytes of RAM, and the H8/3033 with 128 kbytes of ROM and 4 kbytes of RAM.
Page 18 Address space can be partitioned into eight areas, with independent bus specifications in each area • Two-state or three-state access selectable for each area • Selection of four wait modes Note: * Normal mode cannot be used with the H8/3035 Series.
Page 19 Table 1-1 Features (cont) Feature Description • 16-bit integrated Five 16-bit timer channels, capable of processing up to 12 pulse outputs timer unit (ITU) or 10 pulse inputs • 16-bit timer counter (channels 0 to 4) • Two multiplexed output compare/input capture pins (channels 0 to 4) •...
Page 20 Table 1-1 Features (cont) Feature Description Operating modes Three MCU operating modes Mode Address Space Address Pins Bus Width Mode 1 1 Mbyte to A 8 bits Mode 2 16 Mbytes to A 8 bits Mode 3 1 Mbyte — —...
Page 21: Block Diagram
1.2 Block Diagram Figure 1-1 shows an internal block diagram of the H8/3035 Series. Port 3 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL ø H8/300H CPU STBY RESO Interrupt PROM* controller (or masked ROM) /WAIT Watchdog timer...
Page 22: Pin Description
1.3 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3035 Series. TIOCA TIOCB TIOCA RESO TIOCB TOCXA TOCXB ADTRG/TP TxD/P9 XTAL Top view RxD/P9 EXTAL (FP-80A, TFP-80C) /SCK/P9 STBY ø /WAIT Figure 1-2 Pin Arrangement (FP-80A, TFP-80C Top View)
Page 23: Pin Functions
1.3.2 Pin Functions Pin Assignments in Each Mode: Table 1-2 lists the FP-80A and TFP-80C pin assignments in each mode. Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode Pin Name Mode 1 Mode 2 Mode 3 PROM Mode /TIOCA /TIOCA /TIOCA...
Page 24 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name Mode 1 Mode 2 Mode 3 PROM Mode &( :$,7 :$,7 ø ø ø 67%< 67%< 67%< EXTAL EXTAL EXTAL XTAL XTAL XTAL...
Page 25 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name No. Mode 1 Mode 1 Mode 3 PROM Mode 5(62 5(62 5(62 AVSS AVSS AVSS AVSS P70/AN0 P70/AN0 P70/AN0 P71/AN1 P71/AN1 P71/AN1 P72/AN2 P72/AN2 P72/AN2 P73/AN3 P73/AN3 P73/AN3 P74/AN4 P74/AN4...
Page 26: Pin Functions
1.4 Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Type Symbol Pin No. Name and Function Power 21, 53 Input Power: For connection to the power supply. Connect all V pins to the system power supply. 12, 30, 50 Input Ground: For connection to ground (0 V).
Page 27 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function Interrupts Input Nonmaskable interrupt: Requests a nonmaskable interrupt 11, 72 to Input Interrupt request 4 to 0: Maskable interrupt request pins Address bus to A 80 to 77 Output Address bus: Outputs address signals to A 42 to 31,...
Page 28 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function Serial com- Output Transmit data: SCI data output munication interface (SCI) Input Receive data: SCI data input Input/ Serial clock: SCI clock input/output output to AN 66 to 59 Input Analog 7 to 0: Analog input pins converter...
Page 29 Table 1-3 Pin Functions (cont) Type Symbol Pin No. I/O Name and Function I/O ports , P9 11 to 9 Input/ Port 9: Three input/output pins. The direction of output each pin can be selected in the port 9 data direction register (P9DDR).
Page 31: Section 2 Cpu
Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 32: Differences From H8/300 Cpu
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1. Only advanced mode can be used with the H8/3035 Series. Unless specified otherwise, all descriptions in this manual refer to advanced mode.
Page 33: Address Space
The maximum address space of the H8/300H CPU is 16 Mbytes. This LSI allows selection of the 1-Mbyte mode or 16-Mbyte mode for the address space depending on the MCU operation mode. Figure 2-2 shows the address ranges of the H8/3035 Series. For further details see section 3.6, Memory Map in Each Operating Mode.
Page 34: Register Configuration
2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
Page 35: General Registers
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 36: Control Registers
Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute.
Page 37: Initial Cpu Register Values
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: •...
Page 38: General Register Data Formats
2.5.1 General Register Data Formats Figures 2-6 and 2-7 show the data formats in general registers. General Data Type Register Data Format 1-bit data 6 5 4 3 2 1 0 Don’t care Don’t care 7 6 5 4 3 2 1 0 1-bit data 4-bit BCD data Don’t care...
Page 39 General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats...
Page 40: Memory Data Formats
2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 41: Instruction Set
PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. These instructions are not available on the H8/3035 Series. 3. Bcc is a generic branching instruction.
Page 42: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes @ERn (d:16, (d:24, @– (d:8, (d:16, Function Instruction @ERn ERn) ERn) aa:8 aa:16 aa:24 aa:8 Implied Data —...
Page 43: Tables Of Instructions Classified By Function
2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand (EAs)
Page 44: Movfpe
Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3035 Series. Rs → (EAs) MOVTPE Cannot be used in the H8/3035 Series.
Page 45: Adds, - L
Table 2-4 Arithmetic Operation Instructions Instruction Size* Function B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 46: Divxu B/W
Table 2-4 Arithmetic Operation Instructions (cont) Instruct Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16- bit quotient and 16-bit remainder.
Page 47 Table 2-5 Logic Operation Instructions Instruction Size* Function B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Page 48 Table 2-7 Bit Manipulation Instructions Instruction Size* Function 1 → ( of ) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 49 Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* Function C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ [¬ ( of )] → C BIOR ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
Page 50: Rts
Table 2-8 Branching Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 51: Rte
Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 52: Basic Instruction Formats
Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
Page 53: Notes On Use Of Bit Manipulation Instructions
Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2-9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the...
Page 54 Table 2-11 Addressing Modes Addressing Mode Symbol Register direct Register indirect @ERn Register indirect with displacement @(d:16, ERn)/@d:24, ERn) Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn Absolute address @aa:8/@aa:16/@aa:24 Immediate #xx:8/#xx:16/#xx:32 Program-counter relative @(d:8, PC)/@(d:16, PC) Memory indirect @@aa:8 1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand.
Page 55 5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF).
Page 56: Effective Address Calculation
Reserved Specified by @aa:8 Branch address Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address.
Page 60: Processing States
2.8 Processing States 2.8.1 Overview The H8/300H CPU has four processing states: the program execution state, exception-handling state, power-down state, and reset state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states. Figure 2-13 indicates the state transitions.
Page 61: Program Execution State
2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 62: Exception-Handling Sequences
Program execution state SLEEP instruction with SSBY = 0 Exception End of exception Sleep mode handling SLEEP instruction Interrupt with SSBY = 1 NMI, IRQ , IRQ , or IRQ interrupt Exception-handling state Software standby mode RES high STBY high, RES low Reset state Hardware standby mode Power-down state...
Page 63: Reset State
SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 Stack area SP (ER7) SP+4 Even address Before exception After exception Pushed on stack handling starts handling ends Legend CCR: Condition code register Stack pointer Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine.
Page 64: Basic Operational Timing
Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
Page 65: On-Chip Supporting Module Access Timing
Bus cycle T state T state ø Internal address bus Address Internal read signal Internal data bus Read data (read access) Internal write signal Internal data bus Write data (write access) Figure 2-15 On-Chip Memory Access Cycle ø Address bus Address RD WR High...
Page 66: Access To External Address Space
Bus cycle T state T state T state ø Address Internal address bus Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2-17 Access Cycle for On-Chip Supporting Modules ø...
Page 67: Section 3 Mcu Operating Modes
16 Mbytes. The H8/3035 Series can only be used in mode 1, 2, or 3. The inputs at the mode pins must select one of these three modes. The inputs at the mode pins must not be changed during operation.
Page 68: Mode Control Register (Mdcr)
Table 3-2 Registers Address* Name Abbreviation Initial Value H'FFF1 Mode control register MDCR Undetermined H'FFF2 System control register SYSCR H'0B Note: * The lower 16 bits of the address are indicated. 3.2 Mode Control Register (MDCR) — — — — —...
Page 69: System Control Register (Syscr)
3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3035 Series. SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select...
Page 70 Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at least 8 ms at the system clock rate.
Page 71: Operating Mode Descriptions
3.4 Operating Mode Descriptions 3.4.1 Mode 1 1-Mbyte address space can be accessed including the on-chip ROM addresses. Port 3 pins function as data I/O pins D to D and port 1, 2, and 5 pins function as address pins A to A The address bus width can be selected by setting DDR of ports 1, 2, and 5.
Page 72: Memory Map In Each Operating Mode
3.6 Memory Map in Each Operating Mode Figures 3-1 to 3-3 show memory maps of the H8/3035, H8/3034, and H8/3033. The address space is divided into eight areas. Mode 1 Mode 3 Mode 2 (expanded 1-Mbyte mode with on-chip ROM) (expanded 16-Mbyte mode with on-chip ROM) (single-chip advanced mode) H'00000...
Page 73 Mode 1 Mode 2 Mode 3 (expanded 1-Mbyte mode with on-chip ROM) (expanded 16-Mbyte mode with on-chip ROM) (single-chip advanced mode) H'00000 H'000000 H'00000 Vector table Vector table Vector table H'000FF H'0000FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'007FFF H'07FFF Area 0...
Page 74 Mode 1 Mode 2 Mode 3 (expanded 1-Mbyte mode with on-chip ROM) (expanded 16-Mbyte mode with on-chip ROM) (single-chip advanced mode) H'000000 H'00000 H'00000 Vector table Vector table Vector table H'0000FF H'000FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'007FFF H'07FFF H'07FFF Area 0...
Page 75: Section 4 Exception Handling
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 76: Exception Vector Table
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 77: Reset
A reset is the highest-priority exception. When the pin goes low, all processing halts and the H8/3035 Series enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the changes from low to high.
Page 78: Interrupts After Reset
Prefetch of Internal first program Vector fetch processing instruction ø Internal address bus Internal read signal Internal write signal Internal data bus (16-bit width) (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) Start address First instruction of program Figure 4-2 Reset Sequence (Modes 1 to 3)
Page 79: Trap Instruction
NMI (1) External interrupts IRQ to IRQ (5) Interrupts WDT* (1) ITU (15) SCI (4) Internal interrupts A/D converter (1) Notes: Numbers in parentheses are the number of interrupt sources. When the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow.
Page 80: Stack Status After Exception Handling
Figure 4-4 Stack after Completion of Exception Handling (Advanced Mode) 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3035 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even.
Page 81 Setting SP to an odd value may lead to a malfunction. Figure 4-5 shows an example of what happens when the SP value is odd. H'FFEFA H'FFEFB H'FFEFC H'FFEFD H'FFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFEFF Data saved above SP CCR contents lost Legend...
Page 83: Section 5 Interrupt Controller
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
Page 84: Block Diagram
5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number ADIE Interrupt controller SYSCR Legend Interrupt mask bit IER: IRQ enable register IPRA: Interrupt priority register A IPRB:...
Page 85: Pin Configuration
5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable External interrupt request 4 to 0 IRQ to IRQ Input Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration Table 5-2 lists the registers of the interrupt controller.
Page 86: Register Descriptions
5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR).
Page 87 Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG Description Interrupt is requested at falling edge of NMI input (Initial value) Interrupt is requested at rising edge of NMI input...
Page 88: Interrupt Priority Registers A And B (Ipra, Iprb)
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4...
Page 89 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 90 Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2 IPRA2 Description ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 0 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Page 91 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 — IPRB1 — Initial value Read/Write — — — — Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Reserved bit...
Page 92 Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests. Bit 6 IPRB6 Description ITU channel 4 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 4 interrupt requests have priority level 1 (high priority) Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Page 93: Irq Status Register (Isr)
5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ to IRQ interrupt requests. — — — IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Reserved bits...
Page 94: Irq Enable Register (Ier)
5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests. — — — IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write — — — Reserved bits IRQ to IRQ enable These bits enable or disable to IRQ interrupts...
Page 95: Interrupt Sources
Bits 4 to 0—IRQ to IRQ Sense Control (IRQ4SC to IRQ0SC): These bits selects whether interrupts IRQ to IRQ are requested by level sensing of pins IRQ to IRQ , or by falling-edge sensing. Bits 4 to 0 IRQ4SC to IRQ0SC Description Interrupts are requested when IRQ to IRQ inputs are low...
Page 96: Internal Interrupts
IRQnSC IRQnE IRQnF IRQn interrupt Edge/level request sense circuit IRQn input Clear signal Note: n = 0 to 4 Figure 5-2 Block Diagram of Interrupts IRQ to IRQ Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø...
Page 97: Interrupt Vector Table
5.3.3 Interrupt Vector Table Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5-3.
Page 98 Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Vector Address* Vector Interrupt Source Origin Number Advanced Mode Priority IMIA3 (compare match/ H'0090 to H'0093 IPRB7 ITU channel 3 input capture A3) IMIB3 (compare match/ H'0094 to H'0097 input capture B3) OVI3 (overflow 3) H'0098 to H'009B Reserved...
Page 99: Interrupt Operation
5.4.1 Interrupt Handling Process The H8/3035 Series handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 100 Program execution state Interrupt requested? Pending Priority level 1? I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1...
Page 101 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 102 ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example) Figure 5-6 is a flowchart showing how interrupts are accepted when UE = 0.
Page 103 Program execution state Interrupt requested? Pending Priority level 1? I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0...
Page 104: Interrupt Sequence
5.4.2 Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 1 when the program code and stack are in an on-chip memory area. Figure 5-7 Interrupt Sequence (Mode 1, Stack in On-Chip Memory)
Page 105: Interrupt Response Time
5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory 8-Bit Bus On-Chip Item Memory 2 States 3 States...
Page 106: Contention Between Interrupt And Interrupt-Disabling Instruction
TIER write cycle by CPU IMIA exception handling ø Internal TIER address address bus Internal write signal IMIEA IMIA IMFA interrupt signal Figure 5-8 Contention between Interrupt and Interrupt-Disabling Instruction This type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0.
Page 107: Instructions That Inhibit Interrupts
5.5.3 Interrupts during EEPMOV Instruction Execution The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests. When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even NMI. When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are not accepted until the transfer is completed.
Page 108 However, this inadvertent clearing of the IRQbF flag will not occur if 0 is written to this flag even once between generation conditions (1) and (2). TIER write cycle by CPU IMIA exception handling IRQaF 1 read 0 written 1 read 0 written IRQbF 1 read IRQb...
Page 109 Method 1 When clearing the IRQaF flag, read ISR as a byte unit instead of using a bit-manipulation instruction, and write a byte value that clears the IRQaF flag to 0 and sets the other bits to 1. Example: When a = 0 MOV.B @ISR, R0L MOV.B #HFE, R0L MOV.B R0L, @ISR...
Page 111: Section 6 Bus Controller
Section 6 Bus Controller 6.1 Overview The H8/3035 Series has an on-chip bus controller that divides the external address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily.
Page 112: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. ASTCR Internal WCER address bus Area Internal signals decoder Access state control signal Bus control Wait request signal circuit Wait-state WAIT controller Legend ASTCR: Access state control register WCER: Wait state controller enable register WCR:...
Page 113: Register Configuration
6.1.4 Register Configuration Table 6-2 summarizes the bus controller’s registers. Table 6-2 Bus Controller Registers Address* Name Abbreviation R/W Initial Value H'FFED Access state control register ASTCR R/W H'FF H'FFEE Wait control register R/W H'F3 H'FFEF Wait state controller enable register WCER R/W H'FF H'FFF3 Address control register...
Page 114: Wait Control Register (Wcr)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings. 6.2.2 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states.
Page 115: Wait State Controller Enable Register (Wcer)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 Bit 0 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 6.2.3 Wait State Controller Enable Register (WCER)
Page 116: Address Control Register (Adrcr)
6.2.4 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that enables address output on bus lines A to A — — — — — Initial value Mode Read/Write — — — — — — — Initial value Mode Read/Write —...
Page 117 Bit 5—Address 21 Enable (A E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A address output from PA . In modes other than 2 this bit cannot be modified and PA has its ordinary input/output functions.
Page 118: Operation
6.3 Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte mode and 2 Mbytes in the 16-Mbyte mode. Figure 6-2 shows a general view of the memory map.
Page 119 The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ASTCR WCER Bus Specifications Access ASTn WCEn WMS1 WMS0 Bus Width States Wait Mode — — — Disabled —...
Page 120: Bus Control Signal Timing
6.3.2 Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8- bit, three-state-access area. Wait states can be inserted. Bus cycle ø Address bus External address Read access Valid to D Write access Valid...
Page 121 8-Bit, Two-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, two-state-access area. Wait states cannot be inserted. Bus cycle ø Address bus External address Read access to D Valid Write access to D Valid Figure 6-4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area...
Page 122: Wait Modes
6.3.3 Wait Modes Four wait modes can be selected for each area as shown in table 6-4. Table 6-4 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode — — — Disabled No wait states —...
Page 123 WAIT Inserted by signal ø WAIT Address bus External address Read access Read data Data bus Write access Data bus Write data WAIT Note: Arrows indicate time of sampling of the pin. Figure 6-5 Pin Wait Mode 0 Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states :$,7 ) selected by bits WC1 and WC0 are inserted.
Page 124 Inserted by Inserted by WAIT wait count signal ø WAIT Address bus External address Read access Read data Data bus Write access Data bus Write data Write data WAIT Note: Arrows indicate time of sampling of the pin. Figure 6-6 Pin Wait Mode 1 :$,7 Pin Auto-Wait Mode: If the pin is low, the number of wait states (T...
Page 125 ø WAIT Address bus External address External address Read Read data Read data access Data bus Write access Data bus Write data Write data WAIT Note: Arrows indicate time of sampling of the pin. Figure 6-7 Pin Auto-Wait Mode...
Page 126 Programmable Wait Mode: The number of wait states (T ) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6-8 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø...
Page 127 Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings.
Page 128: Interconnections With Memory (Example)
6.3.4 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices. Figure 6-10 shows a memory map for this example. A 32-kword ×...
Page 129 H'00000 Area 0 and 1 On-chip ROM H'3FFFF H'40000 EPROM H'47FFF Area 2 H'48000 8-bit, three-state-access area Not used H'5FFFF H'60000 SRAM1, 2 Area 3 H'6FFFF 8-bit, two-state-access area H'70000 Not used H'7FFFF Areas 4, 5, 6 H'E0000 SRAM3 H'E7FFF Area 7 Not used 8-bit, three-state-access area...
Page 130: Usage Notes
6.4 Usage Notes 6.4.1 Register Write Timing ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from the next bus cycle. Figure 6-11 shows the timing when an instruction fetched from area 2 changes area 2 from three-state access to two-state access. ø...
Page 131: Section 7 I/O Ports
7.1 Overview The H8/3035 Series has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 7-1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7-1.
Page 132 Table 7-1 Port Functions Port Description Pins Mode 1 Mode 2 Mode 3 • Port 1 to P1 Address output (A to A ) and Generic 8-bit I/O port generic input input/output • to A Can drive DDR = 0: generic input LEDs DDR = 1: address output •...
Page 133 Table 7-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 Mode 3 • Port A PA7/TP7/TIOCB2/A20 TPC output Address output TPC output 8-bit I/O (TP7), ITU input (A20) (TP7), ITU input port and output and output • Schmitt (TIOCB2), and (TIOCB2), and inputs...
Page 134: Port 1
7.2 Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ depending on the operating mode. In modes 1 and 2, settings in the port 1 data direction register (P1DDR) can designate pins for address bus output (A to A ) or generic...
Page 135 Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1. P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR Initial value Read/Write Port 1 data direction 7 to 0...
Page 136: Pin Functions In Each Mode
7.2.3 Pin Functions in Each Mode The pin functions of port 1 differ between modes 1 and 2 and mode 3 (single-chip mode). The pin functions in each mode are described followings. Modes 1 and 2: Address output or generic input can be selected for each pin in port 1. A pin becomes an address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared to 0.
Page 137: Port 2
7.3 Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-4. The pin functions differ depending on the operating mode. In modes 1 and 2, settings in the port 2 data direction register (P2DDR) can designate pins for address bus output (A to A ) or generic input.
Page 138 Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2. P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR Initial value Read/Write Port 2 data direction 7 to 0...
Page 139: Pin Functions In Each Mode
Port 2 Input Pull-Up Control Register (P2PCR): P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 2. P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up control 7 to 0 These bits control input pull-up...
Page 140: Input Pull-Up Transistors
Mode 3: Input or output can be selected separately for each pin in port 2. A pin becomes an output pin if the corresponding P2DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7-6 shows the pin functions in mode 3.
Page 141: Port 3
7.4 Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7-7. Port 3 is a data bus in modes 1 and 2 and a generic input/output port in mode 3. Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair.
Page 142 Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 data direction 7 to 0...
Page 143: Pin Functions In Each Mode
7.4.3 Pin Functions in Each Mode The pin functions of port 3 differ between modes 1 and 2 and mode 3. The pin functions in each mode are described below. Modes 1 and 2: All pins of port 3 automatically become data input/output pins. Figure 7-8 shows the pin functions in modes 1 and 2.
Page 144: Port 5
7.5 Port 5 7.5.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7-10. The pin functions differ depending on the operating mode. In modes 1 and 2, settings in the port 5 data direction register (P5DDR) designate pins for address bus output (A to A ) or generic input.
Page 145 Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. — — — — P5 DDR P5 DDR P5 DDR P5 DDR Initial value Read/Write — —...
Page 146: Pin Functions In Each Mode
Port 5 Input Pull-Up Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. — — — — P5 PCR P5 PCR P5 PCR P5 PCR Initial value Read/Write — — —...
Page 147: Input Pull-Up Transistors
Mode 3: Input or output can be selected separately for each pin in port 5. A pin becomes an output pin if the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7-12 shows the pin functions in mode 3.
Page 148: Port 6
7.6 Port 6 7.6.1 Overview Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals :$,7 , and Figure 7-13 shows the pin configuration of port 6. In modes 1 and 2, the pin functions are :$,7 , and P6 .
Page 149 Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. — — P6 DDR P6 DDR P6 DDR — — P6 DDR Initial value Read/Write — Reserved bits Port 6 data direction 5 to 3, 0 These bits select input or output for port 6 pins...
Page 150: Pin Functions In Each Mode
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores data for pins P6 to P6 and P6 — — — — Initial value Read/Write — — — — Reserved bits Port 6 data 5 to 3, 0 These bits store data for port 6 pins When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is returned directly.
Page 151 Table 7-9 Port 6 Pin Functions in Modes 1 and 2 Pin Functions and Selection Method Functions as follows regardless of P6 Pin function output Functions as follows regardless of P6 Pin function output Functions as follows regardless of P6 Pin function output :$,7...
Page 152: Port 7
7.7 Port 7 7.7.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin functions are the same in all operating modes. Figure 7-16 shows the pin configuration of port 7. Port 7 pins P7 (input)/AN (input) P7 (input)/AN (input)
Page 153: Register Description
7.7.2 Register Description Table 7-10 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction register. Table 7-10 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFCE Port 7 data register P7DR Undetermined Note: * Lower 16 bits of the address.
Page 154: Register Descriptions
Port 8 pins Modes 1 and 2 Mode 3 /IRQ (input)/IRQ (input) (input/output)/IRQ (input) /IRQ (input)/IRQ (input) (input/output)/IRQ (input) Port 8 /IRQ (input)/IRQ (input) (input/output)/IRQ (input) /IRQ (input/output)/IRQ (input) (input/output)/IRQ (input) Figure 7-17 Port 8 Pin Configuration 7.8.2 Register Descriptions Table 7-11 summarizes the registers of port 8.
Page 155 • Modes 1 and 2 Pins P8 to P8 function as input pins. Do not set P8 DDR to P8 DDR to 1. Pin P8 functions as an output pin when P8 DDR is set to 1, and as input pin when P8 DDR is cleared to 0.
Page 156: Pin Functions
7.8.3 Pin Functions The port 8 pins are also used for IRQ to IRQ . Table 7-12 describes the selection of pin functions. Table 7-12 Port 8 Pin Functions Pin Functions and Selection Method /IRQ Bit P8 DDR selects the pin function as follows Modes 1 and 2 Mode 3 Pin function...
Page 157: Port 9
7.9 Port 9 7.9.1 Overview Port 9 is a 3-bit input/output port that is also used for input and output (TxD, RxD, SCK) by the serial communication interface (SCI), and for input. Port 9 has the same set of pin functions in all operating modes.
Page 158 Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. — — — P9 DDR — P9 DDR — P9 DDR Initial value Read/Write — — Reserved bits Port 9 data direction 4, 2, 0 These bits select input or...
Page 159: Pin Functions
Bits 7 to 5, 3 and 1 are reserved. Bits 7 and 6 cannot be modified and always read 1. Bits 5, 3, and 1 cannot be modified and are always read as 0. If bit 5, 3, or 1 in P9DDR is read while its value is 1, the corresponding bit in P9DR is read directly.
Page 160: Port A
7.10 Port A 7.10.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output (TIOCB , TIOCA , TIOCB TIOCA , TIOCB , TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU), and address output (A...
Page 161: Register Descriptions
7.10.2 Register Descriptions Table 7-15 summarizes the registers of port A. Table 7-15 Port A Registers Initial Value Address* Name Abbreviation R/W Modes 1 and 3 Mode 2 H'FFD1 Port A data direction register PADDR H'00 H'80 H'FFD3 Port A data register PADR H'00 H'00...
Page 162 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for pins PA to PA Initial value Read/Write Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly.
Page 163: Pin Functions
7.10.3 Pin Functions The port A pins are also used for TPC output (TP to TP ), ITU input/output (TIOCB TIOCB , TIOCA to TIOCA ) and input (TCLKD, TCLKC, TCLKB, TCLKA), and as address bus pins (A to A ).
Page 164 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method PA6/TP6/T The mode setting, bit A21E in BRCR, ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to IOCA2/A2 IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA6DDR in PADDR select the pin function as follows Mode 1 and 3 A21E...
Page 165 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method The mode setting, bit A E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and /TIOCA bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 166 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TPSC2 to TPSC0 in /TIOCA TCR4 to TCR0, bit NDER2 in NDERA, and bit PA2DDR in PADDR select the pin function as follows /TCLKC ITU channel 0 (1) in table below...
Page 167: Port B
Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method Bit NDER1 in NDERA and bit PA DDR in PADDR select the pin function as follows TCLKB NDER1 — Pin function input output output TCLKB input* Note: *TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0.
Page 168: Register Descriptions
Port B pins PB (input/output)/TP (output)/ADTRG (input) PB (input/output)/TP (output) PB (input/output)/TP (output)/TOCXB (output) PB (input/output)/TP (output)/TOCXA (output) Port B PB (input/output)/TP (output)/TIOCB (input/output) PB (input/output)/TP (output)/TIOCA (input/output) PB (input/output)/TP (output)/TIOCB (input/output) PB (input/output)/TP (output)/TIOCA (input/output) Figure 7-20 Port B Pin Configuration 7.11.2 Register Descriptions Table 7-17 summarizes the registers of port B.
Page 169 PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output state in software standby mode.
Page 170: Pin Functions
7.11.3 Pin Functions The port B pins are also used for TPC output (TP to TP ), ITU input/output (TIOCB $'75* TIOCB , TIOCA , TIOCA ) and output (TOCXB , TOCXA ), and input. Table 7-18 describes the selection of pin functions. Table 7-18 Port B Pin Functions Pin Functions and Selection Method PB7/...
Page 171 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB DDR in TIOCB PBDDR select the pin function as follows...
Page 172 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB DDR in PBDDR TIOCA select the pin function as follows...
Page 173 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel...
Page 174 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, TIOCA and bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel 3...
Page 175: Section 8 16-Bit Integrated Timer Unit (Itu)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.1 Overview The H8/3035 Series has a built-in 16-bit integrated timer-pulse unit (ITU) with five 16-bit timer channels. 8.1.1 Features ITU features are listed below. • Capability to process up to 12 pulse outputs or 10 pulse inputs •...
Page 176 If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of non-overlapping complementary waveforms.  Buffering Input capture registers can be double-buffered. Output compare registers can be updated automatically. • High-speed access via internal 16-bit bus The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed via a 16-bit bus.
Page 177 Table 8-1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Clock sources Internal clocks: ø, ø/2, ø/4, ø/8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers (output GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 compare/input capture...
Page 178: Block Diagrams
8.1.2 Block Diagrams ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU. IMIA0 to IMIA4 TCLKA to TCLKD Clock selector IMIB0 to IMIB4 OVI0 to OVI4 ø, ø/2, ø/4, ø/8 TOCXA , TOCXB Control logic TIOCA to TIOCA TIOCB to TIOCB...
Page 179 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8-2. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 Control logic IMIA0 IMIB0 Comparator OVI0 Module data bus Legend TCNT:...
Page 180 Block Diagram of Channel 2: Figure 8-3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 Control logic IMIA2 IMIB2 Comparator OVI2...
Page 181 Block Diagrams of Channels 3 and 4: Figure 8-4 is a block diagram of channel 3. Figure 8-5 is a block diagram of channel 4. TIOCA TCLKA to TIOCB TCLKD Clock selector ø, ø/2, ø/4, ø/8 Control logic IMIA3 Comparator IMIB3 OVI3 Module data bus...
Page 182 TOCXA TCLKA to TOCXB TCLKD Clock selector ø, ø/2, TIOCA ø/4, ø/8 TIOCB Control logic IMIA4 Comparator IMIB4 OVI4 Module data bus Legend TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) ×...
Page 183: Input/Output Pins
8.1.3 Input/Output Pins Table 8-2 summarizes the ITU pins. Table 8-2 ITU Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input External clock B input pin...
Page 184: Register Configuration
8.1.4 Register Configuration Table 8-3 summarizes the ITU registers. Table 8-3 ITU Registers Abbre- Initial Channel Address Name viation Value Common H'FF60 Timer start register TSTR H'E0 H'FF61 Timer synchro register TSNC H'E0 H'FF62 Timer mode register TMDR H'80 H'FF63 Timer function control register TFCR H'C0...
Page 185 Table 8-3 ITU Registers (cont) Abbre- Initial Channel Address Name viation Value H'FF78 Timer control register 2 TCR2 H'80 H'FF79 Timer I/O control register 2 TIOR2 H'88 H'FF7A Timer interrupt enable register 2 TIER2 H'F8 H'FF7B Timer status register 2 TSR2 R/(W) H'F8...
Page 186: Register Descriptions
Table 8-3 ITU Registers (cont) Abbre- Initial Channel Address Name viation Value H'FF92 Timer control register 4 TCR4 H'80 H'FF93 Timer I/O control register 4 TIOR4 H'88 H'FF94 Timer interrupt enable register 4 TIER4 H'F8 H'FF95 Timer status register 4 TSR4 R/(W) H'F8...
Page 187 Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1. Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4). Bit 4 STR4 Description TCNT4 is halted (Initial value) TCNT4 is counting Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3). Bit 3 STR3 Description...
Page 188: Timer Synchro Register (Tsnc)
8.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write —...
Page 189 Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 Description Channel 2’s timer counter (TCNT2) operates independently (Initial value) TCNT2 is preset and cleared independently of other channels Channel 2 operates synchronously TCNT2 can be synchronously preset and cleared Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously.
Page 190: Timer Mode Register (Tmdr)
8.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. — FDIR PWM4 PWM3 PWM2 PWM1 PWM0...
Page 191 In phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in timer control register 2 (TCR2). Phase counting mode takes precedence over these settings. The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare match/input capture settings and interrupt functions of timer I/O control register 2 (TIOR2), timer interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain...
Page 192 If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes precedence and the PWM3 setting is ignored. Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 Description...
Page 193: Timer Function Control Register (Tfcr)
8.2.4 Timer Function Control Register (TFCR) TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset- synchronized PWM mode, and buffering for channels 3 and 4. — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — —...
Page 194 When these bits select complementary PWM mode or reset-synchronized PWM mode, they take precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in complementary PWM mode and reset-synchronized PWM mode, however.
Page 195: Timer Output Master Enable Register (Toer)
8.2.5 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3 and 4. — — EXB4 EXA4 Initial value Read/Write — — Reserved bits Master enable TOCXA , TOCXB These bits enable or disable output settings for pins TOCXA4 and TOCXB4 Master enable TIOCA...
Page 196 Bit 3—Master Enable TIOCB (EB3): Enables or disables ITU output at pin TIOCB Bit 3 Description TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB operates as a generic input/output pin). If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1. TIOCB is enabled for output according to TIOR3 and TFCR settings (Initial value)
Page 197: Timer Output Control Register (Tocr)
8.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. — — — XTGD — — OLS4 OLS3 Initial value Read/Write —...
Page 198: Timer Counters (Tcnt)
Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 Description TIOCA , TIOCA , and TIOCB pin outputs are inverted TIOCA , TIOCA , and TIOCB pin outputs are not inverted (Initial value) Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and reset-synchronized PWM mode.
Page 199: General Registers (Gra, Grb)
TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or by input capture to GRA or GRB (counter clearing function) in the same channel. When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in the timer status register (TSR) of the corresponding channel.
Page 200: Buffer Registers (Bra, Brb)
the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized PWM mode.
Page 201: Timer Control Registers (Tcr)
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. 8.2.10 Timer Control Registers (TCR) TCR is an 8-bit register.
Page 202 Bits 6 and 5 —Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture TCNT is cleared by GRB compare match or input capture Synchronous clear: TCNT is cleared in synchronization with other synchronized timers Notes: 1.
Page 203: Timer I/O Control Register (Tior)
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in TCR2 are ignored.
Page 204 Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 Function GRB is an No output at compare match (Initial value)
Page 205: Timer Status Register (Tsr)
Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 Function GRA is an No output at compare match (Initial value) output register 0 output at GRA compare match 1 output at GRA compare match Output toggles at GRA compare match (1 output in channel 2) *1, *2 GRA is an input...
Page 206 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Reserved bits Overflow flag Status flag indicating overflow or underflow Input capture/compare match flag B Status flag indicating GRB compare match or input capture Input capture/compare match flag A Status flag indicating GRA compare match or input capture...
Page 207: Timer Interrupt Enable Register (Tier)
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB compare match or input capture events. Bit 1 IMFB Description [Clearing condition] (Initial value) Read IMFB when IMFB = 1, then write 0 in IMFB [Setting conditions] TCNT = GRB when GRB functions as a compare match register. TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register.
Page 208 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Reserved bits Overflow interrupt enable Enables or disables OVF interrupts Input capture/compare match interrupt enable B Enables or disables IMFB interrupts Input capture/compare match interrupt enable A Enables or disables IMFA interrupts...
Page 209: Cpu Interface
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the interrupt requested by the IMFA flag in TSR when IMFA is set to 1. Bit 0 IMIEA Description IMIA interrupt requested by IMFA is disabled (Initial value) IMIA interrupt requested by IMFA is enabled 8.3 CPU Interface 8.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers...
Page 210 Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8-8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8-9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) Internal data bus Module Bus interface...
Page 211: 8-Bit Accessible Registers
Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 8-12 and 8-13 show examples of byte read and write access to a TCR.
Page 212: Operation
8.4 Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
Page 213 Buffering • If the general register is an output compare register When compare match occurs the buffer register value is transferred to the general register. • If the general register is an input capture register When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register.
Page 214: Basic Functions
8.4.2 Basic Functions Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic. • Sample setup procedure for counter Figure 8-14 shows a sample procedure for setting up a counter.
Page 215 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal. 2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare match or GRB compare match.
Page 216 TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 8-16 Periodic Counter Operation • Count timing  Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock sources obtained by prescaling the system clock (ø/2, ø/4, ø/8).
Page 217 ø External clock input TCNT input TCNT N – 1 N + 1 Figure 8-18 Count Timing for External Clock Sources (when Both Edges are Detected) Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle.
Page 218 • Examples of waveform output Figure 8-20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. TCNT value H'FFFF H'0000...
Page 219 • Output compare timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 220 Input Capture Function: The TCNT value can be captured into a general register when a transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take place on the rising edge, falling edge, or both edges. The input capture function can be used to measure pulse width or period.
Page 221: Synchronization
• Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8-25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 222 Sample Setup Procedure for Synchronization: Figure 8-26 shows a sample procedure for setting up synchronization. Setup for synchronization Select synchronization Synchronous preset Synchronous clear Clearing synchronized to this channel? Write to TCNT Select counter clear source Select counter clear source Start counter Start counter Synchronous preset...
Page 223: Pwm Mode
Value of TCNT0 to TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 Time TIOCA TIOCA TIOCA Figure 8-27 Synchronization (Example) 8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1.
Page 224 Sample Setup Procedure for PWM Mode: Figure 8-28 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to Select counter clock select the desired edge(s) of the...
Page 225 TCNT value Counter cleared by compare match with GRA H'0000 Time TIOCA a. Counter cleared by GRA TCNT value Counter cleared by compare match with GRB H'0000 Time TIOCA b. Counter cleared by GRB Figure 8-29 PWM Mode (Example 1) Figure 8-30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
Page 226 TCNT value Counter cleared by compare match with GRB H'0000 Time TIOCA Write to GRA Write to GRA a. 0% duty cycle TCNT value Counter cleared by compare match with GRA H'0000 Time TIOCA Write to GRB Write to GRB b.
Page 227: Reset-Synchronized Pwm Mode
8.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA TIOCB , and TOCXB...
Page 228 Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 8-31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted.
Page 229: Complementary Pwm Mode
TCNT3 value Counter cleared at compare match with GRA3 GRA3 GRB3 GRA4 GRB4 H'0000 Time TIOCA TIOCB TIOCA TOCXA TIOCB TOCXB Figure 8-32 Operation in Reset-Synchronized PWM Mode (Example) (when OLS3 = OLS4 = 1) For the settings and operation when reset-synchronized PWM mode and buffer mode are both selected, see section 8.4.8, Buffering.
Page 230 Table 8-7 Output Pins in Complementary PWM Mode Channel Output Pin Description TIOCA PWM output 1 TIOCB PWM output 1´ (non-overlapping complementary waveform to PWM output 1) TIOCA PWM output 2 TOCXA PWM output 2´ (non-overlapping complementary waveform to PWM output 2) TIOCB PWM output 3...
Page 231 Setup Procedure for Complementary PWM Mode: Figure 8-33 shows a sample procedure for setting up complementary PWM mode. Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are Stop counting halted.
Page 232 Clearing Complementary PWM Mode: Figure 8-34 shows a sample procedure for clearing complementary PWM mode. Complementary PWM mode Clear bit CMD1 in TFCR to 0, and set channels 3 and 4 to normal operating Clear complementary mode mode. After setting channels 3 and 4 to normal operating mode, wait at least one clock count before clearing bits STR3 and Stop counting...
Page 233 TCNT3 and TCNT4 values Down-counting starts at compare match between TCNT3 and GRA3 GRA3 TCNT3 GRB3 GRA4 TCNT4 GRB4 Time H'0000 Up-counting starts when TCNT4 underflows TIOCA TIOCB TIOCA TOCXA TIOCB TOCXB Figure 8-35 Operation in Complementary PWM Mode (Example 1) (when OLS3 = OLS4 = 1) Figure 8-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode.
Page 234 TCNT3 and TCNT4 values GRA3 GRB3 H'0000 Time TIOCA 0% duty cycle TIOCB a. 0% duty cycle TCNT3 and TCNT4 values GRA3 GRB3 H'0000 Time TIOCA TIOCB 100% duty cycle b. 100% duty cycle Figure 8-36 Operation in Complementary PWM Mode (Example 2) (when OLS3 = OLS4 = 1) In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting.
Page 235 Underflow Overflow TCNT4 H'0001 H'0000 H'FFFF H'0000 Flag not set Set to 1 Buffer transfer signal (BR to GR) Buffer transfer No buffer transfer Figure 8-37 Overshoot Timing GRA3 H'0000 Not allowed Figure 8-38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs.
Page 236 General Register Settings in Complementary PWM Mode: When setting up general registers for complementary PWM mode or changing their settings during operation, note the following points. • Initial settings Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the counters start and the first compare match A3 event has occurred, however, settings in this range also become possible.
Page 237  Buffer transfer at transition from down-counting to up-counting If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer register value outside this range. Conversely, when a general register value is outside this range, do not transfer a value within this range.
Page 238: Phase Counting Mode
Phase counting mode Select phase counting mode Set the MDF bit in TMDR to 1 to select phase counting mode. Select the flag setting condition with the FDIR bit in TMDR. Set the STR2 bit to 1 in TSTR to start the timer counter.
Page 239 Sample Setup Procedure for Phase Counting Mode: Figure 8-43 shows a sample procedure for setting up phase counting mode. TCNT2 value Counting up Counting down Time TCLKB TCLKA Figure 8-43 Setup Procedure for Phase Counting Mode (Example) Example of Phase Counting Mode: Figure 8-44 shows an example of operations in phase counting mode.
Page 240 Compare match signal Comparator TCNT Figure 8-45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 8.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode.
Page 241: Buffering
• General register used for input capture The TCNT value is transferred to the general register at input capture. The previous general register value is transferred to the buffer register. See figure 8-47. Buffering Select general register functions Set TIOR to select the output compare or input capture function of the general registers.
Page 242 • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times:  When TCNT3 matches GRA3  When TCNT4 underflows • Reset-synchronized PWM mode The buffer register value is transferred to the general register at compare match A3.
Page 243 TCNT value Counter cleared by compare match B H'0250 H'0200 H'0100 H'0000 Time H'0200 H'0100 H'0200 H'0250 H'0200 H'0100 H'0200 Toggle TIOCB output Toggle TIOCA output Compare match A Figure 8-49 Register Buffering (Example 1: Buffering of Output Compare Register) ø...
Page 244 previous GRA value is simultaneously transferred to BRA. Figure 8-52 shows the transfer timing. TCNT value Counter cleared by input capture B H'0180 H'0160 H'0005 Time H'0000 TIOCB TIOCA H'0005 H'0160 H'0005 H'0160 H'0180 Input capture A Figure 8-51 Register Buffering (Example 2: Buffering of Input Capture Register) ø...
Page 245 Figure 8-53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows.
Page 246: Itu Output Timing
8.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER.
Page 247 Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output.
Page 248: Interrupts
8.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 249 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 8-58 shows the timing. ø Input capture signal TCNT Figure 8-58 Timing of Setting of IMFA and IMFB by Input Capture...
Page 250: Clearing Of Status Flags
8.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 8-60 shows the timing. TSR write cycle ø Address TSR address IMF, OVF Figure 8-60 Timing of Clearing of Status Flags...
Page 251: Interrupt Sources
8.5.3 Interrupt Sources Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1.
Page 252: Usage Notes
8.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8-61.
Page 253 Contention between TCNT Word Write and Increment: If an increment pulse occurs in the state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 8-62. TCNT word write cycle ø Address TCNT address Internal write signal TCNT input clock TCNT...
Page 254 Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 8-63, which shows an increment pulse occurring in the T state of a byte write to TCNTH.
Page 255 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8-64. General register write cycle ø...
Page 256 Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 8-65. TCNT write cycle ø...
Page 257 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8-66. General register read cycle ø Address GR address Internal read signal Input capture signal...
Page 258 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 259 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8-68. General register write cycle ø...
Page 260 Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: f = ø/(N + 1) (f: counter frequency.
Page 261 Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized •...
Page 262 ITU Operating Modes Table 8-11 (a) ITU Operating Modes (Channel 0) Register Settings TSNC TMDR TFCR TOCR TOER TIOR0 TCR0 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset...
Page 263 Table 8-11 (b) ITU Operating Modes (Channel 1) Register Settings TSNC TMDR TFCR TOCR TOER TIOR1 TCR1 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset SYNC1 = 1 —...
Page 264 Table 8-11 (c) ITU Operating Modes (Channel 2) Register Settings TSNC TMDR TFCR TOCR TOER TIOR2 TCR2 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset SYNC2 = 1 o —...
Page 265 Table 8-11 (d) ITU Operating Modes (Channel 3) Register Settings TSNC TMDR TFCR TOCR TOER TIOR3 TCR3 Comple- Reset- Output Synchro- mentary Synchro- Level Master Clear Clock Operating Mode nization FDIR PWM nized PWM Buffering XTGD Select Enable Select Select Synchronous preset SYNC3 = 1 —...
Page 266 Table 8-11 (e) ITU Operating Modes (Channel 4) Register Settings TSNC TMDR TFCR TOCR TOER TIOR4 TCR4 Comple- Reset- Output Synchro- mentary Synchro- Level Master Clear Clock Operating Mode nization FDIR PWM nized PWM Buffering XTGD Select Enable Select Select Synchronous preset SYNC4 = 1 —...
Page 267: Section 9 Programmable Timing Pattern Controller
Section 9 Programmable Timing Pattern Controller 9.1 Overview The H8/3035 Series has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 268: Block Diagram
9.1.2 Block Diagram Figure 9-1 shows a block diagram of the TPC. ITU compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR NDRA...
Page 269: Tpc Pins
9.1.3 TPC Pins Table 9-1 summarizes the TPC output pins. Table 9-1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 270: Registers
9.1.4 Registers Table 9-2 summarizes the TPC registers. Table 9-2 TPC Registers Address Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 H'FFD3 Port A data register PADR R/(W) H'00 H'FFD4 Port B data direction register PBDDR H'00 H'FFD6 Port B data register...
Page 271: Register Descriptions
9.2 Register Descriptions 9.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
Page 272: Port B Data Direction Register (Pbddr)
9.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
Page 273: Next Data Register A (Ndra)
9.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers.
Page 274 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Page 275: Next Data Register B (Ndrb)
9.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers.
Page 276 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.
Page 277: Next Data Enable Register A (Ndera)
9.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
Page 278: Next Data Enable Register B (Nderb)
9.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
Page 279: Tpc Output Control Register (Tpcr)
9.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Page 280 Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP to TP Bit 5 Bit 4 G2CMS1 G2CMS0 Description TPC output group 2 (TP to TP ) is triggered by compare match in ITU channel 0...
Page 281: Tpc Output Mode Register (Tpmr)
9.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP to TP )
Page 282 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected ITU channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
Page 283: Operation
9.3 Operation 9.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 284: Output Timing
9.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 9-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 285: Normal Tpc Output
9.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 9-4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited). Set the TPC output trigger period.
Page 286 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9-5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR • The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 287: Non-Overlapping Tpc Output
9.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 9-6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set the TPC output trigger period in GRB Set GR values and the non-overlap margin in GRA.
Page 288 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin • The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B.
Page 289: Tpc Output Triggering By Input Capture
9.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 290 NDER Compare match A Compare match B Internal data bus TPC output pin Figure 9-9 Non-Overlapping TPC Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin).
Page 291: Section 10 Watchdog Timer
As a watchdog timer, it generates a reset signal for the H8/3035 Series chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow.
Page 292: Block Diagram
10.1.2 Block Diagram Figure 10-1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources ø/2 RSTCSR ø/32 ø/64 Reset Reset control Clock ø/128 (internal, external) Clock selector ø/256...
Page 293: Register Configuration
10.1.4 Register Configuration Table 10-2 summarizes the WDT registers. Table 10-2 WDT Registers Address Write Read Name Abbreviation Initial Value H'FFA8 H'FFA8 Timer control/status register TCSR R/(W) H'18 H'FFA9 Timer counter TCNT H'00 H'FFAA H'FFAB Reset control/status register RSTCSR R/(W) H'3F Notes: 1.
Page 294: Timer Control/Status Register (Tcsr)
10.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Page 295 ,7 ,7 Bit 6—Timer Mode Select (WT/ ): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows.
Page 296: Reset Control/Status Register (Rstcsr)
10.2.3 Reset Control/Status Register (RSTCSR) WRST RSTOE — — — — — — Initial value Read/Write R/(W) — — — — — — Reserved bits Reset output enable Enables or disables external output of the reset signal Watchdog timer reset Indicates that a reset signal has been generated RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been...
Page 297: Notes On Register Access
5(62 Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the pin of the reset signal generated if TCNT overflows during watchdog timer operation. Bit 6 RSTOE Description Reset signal is not output externally (Initial value) Reset signal is output externally Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
Page 298: Operation
TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3035 Series is internally reset for a duration of 518 states.
Page 299: Interval Timer Operation
A watchdog reset has the same vector as a reset generated by input at the pin. Software can distinguish a reset from a watchdog reset by checking the WRST bit in RSTCSR. If a reset and a watchdog reset occur simultaneously, the reset takes priority.
Page 300: Timing Of Setting Of Overflow Flag (Ovf)
1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3035 Series chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
Page 301: Interrupts
ø TCNT H'FF H'00 Overflow signal WDT internal reset WRST Figure 10-7 Timing of Setting of WRST Bit and Internal Reset 10.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 10.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T...
Page 302 Write cycle: CPU writes to TCNT ø TCNT Internal write signal TCNT input clock TCNT Counter write data Figure 10-8 Contention between TCNT Write and Increment Changing CKS2 to CKS0 Values: Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0.
Page 303: Section 11 Serial Communication Interface
Section 11 Serial Communication Interface 11.1 Overview The H8/3035 Series has a serial communication interface (SCI). The SCI can communicate in asynchronous mode or synchronous mode, and has a multiprocessor communication function for serial communication among two or more processors.
Page 304: Block Diagram
• Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the SCI. Internal data bus Module data bus ø Baud rate ø/4 generator Transmit/ ø/16 receive control ø/64 Parity generation Clock...
Page 305: Input/Output Pins
11.1.3 Input/Output Pins The SCI has the serial pins listed in table 11-1. Table 11-1 SCI Pins Name Abbreviation Function Serial clock pin Input/output SCI clock input/output Receive data pin Input SCI receive data input Transmit data pin Output SCI transmit data output 11.1.4 Register Configuration The SCI has the internal registers as listed in table 11-2.
Page 306: Register Descriptions
11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) RSR is an 8-bit register that receives serial data. Initial value Read/Write — — — — — — — — The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 307: Transmit Shift Register (Tsr)
11.2.3 Transmit Shift Register (TSR) TSR is an 8-bit register used to transmit serial data. Initial value Read/Write — — — — — — — — The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 308: Serial Mode Register (Smr)
11.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator’s clock source Multiprocessor mode...
Page 309 Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 Description 8-bit data (Initial value) 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted. Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data.
Page 310 Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit setting is ignored. Bit 3 STOP Description One stop bit (Initial value)
Page 311: Serial Control Register (Scr)
11.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0 These bits select the SCI clock source Transmit end interrupt enable...
Page 312 Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to RDR; also enables or disables the receive-error interrupt (ERI). Bit 6 Description Receive-end (RXI) and receive-error (ERI) interrupt requests...
Page 313 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
Page 314 Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0).
Page 315: Serial Status Register (Ssr)
11.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer Value of multi- processor bit to be transmitted Multiprocessor bit...
Page 316 Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial transmit data can be written in TDR. Bit 7 TDRE Description TDR contains valid transmit data [Clearing conditions] Software reads TDRE while it is set to 1, then writes 0.
Page 317 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads ORER while it is set to 1, then writes 0. A receive overrun error occurred [Setting condition] Reception of the next serial data ends when RDRF = 1.
Page 318 Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 Description Receiving is in progress or has ended normally (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0.
Page 319: Bit Rate Register (Brr)
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1 Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its...
Page 320 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode ø (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 148 –0.04 174 –0.26 212 0.03 0.16 108 0.21 127 0 155 0.16 0.16 217 0.21 255 0 0.16 0.16...
Page 321 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 2 0.08 –0.07 2 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800...
Page 322 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 14.7456 Bit Rate Error Error Error Error (bits/s) –0.17 0.70 0.03 – 0.12 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 0.16 2400 0.16...
Page 323 Table 11-4 Examples of Bit Rates and BRR Settings in Synchronous Mode ø (MHz) Bit Rate (bit/s) — — — — — — — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k 250 k...
Page 324 SMR Settings Clock Source CKS1 CKS0 ø ø/4 ø/16 ø/64 The bit rate error in asynchronous mode is calculated as follows. Error (%) = (ø × 10 /((N + 1) × B × 64 × 2 )–1} × 100 2n–1 Table 11-5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies.
Page 325 Table 11-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings ø (MHz) Maximum Bit Rate (bits/s) 62500 2.097152 65536 2.4576 76800 93750 3.6864 115200 125000 4.9152 153600 156250 187500 6.144 192000 7.3728 230400 250000 9.8304 307200 312500 375000 12.288 384000 437500 14.7456...
Page 326 Table 11-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 327: Operation
Table 11-7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 11.3 Operation 11.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses.
Page 328 Synchronous Mode • The communication format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors. • An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.
Page 329: Operation In Asynchronous Mode
Table 11-9 SMR and SCR Settings and SCI Clock Source Selection SCR Settings Bit 7 Bit 1 Bit 0 CKE1 CKE0 Mode Clock Source SCK Pin Function Asynchronous Internal SCI does not use the SCK pin mode Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16...
Page 330 Idle (mark) state (LSB) (MSB) Serial data Start Parity Stop Transmit or receive data 1 bit 7 bits or 8 bits 1 bit or 1 bit or no bit 2 bits One unit of data (character or frame) Figure 11-2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits)
Page 331 Communication Formats: Table 11-10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 11-10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data...
Page 332 1 frame Figure 11-3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 333 Start of initialization Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after Clear TE and RE bits the setting is made in SCR. to 0 in SCR Select the communication format in SMR.
Page 334 Transmitting Serial Data (Asynchronous Mode): Figure 11-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, Start transmitting check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0.
Page 335 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 336 Receiving Serial Data (Asynchronous Mode): Figure 11-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling and break Start receiving detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify...
Page 337 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 11-7 Sample Flowchart for Receiving Serial Data (2)
Page 338 In receiving, the SCI operates as follows. • The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 339: Multiprocessor Communication
Figure 11-8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt handler request reads data in RDR and Framing error, clears RDRF flag to 0 ERI request 1 frame Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
Page 340 Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID-sending cycle: receiving Data-sending cycle: processor address data sent to receiving...
Page 341 SCI initialization: the transmit data Initialize output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit Read TDRE flag in SSR data in TDR.
Page 342 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 343 Receiving Multiprocessor Serial Data: Figure 11-12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read Set MPIE bit to 1 in SCR...
Page 344 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER and FER flags to 0 in SSR Figure 11-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Figure 11-13 shows an example of SCI receive operation using a multiprocessor format.
Page 345 Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI request RXI handler reads Not own ID, so No RXI request, (multiprocessor RDR data and clears MPIE bit is set RDR not updated interrupt), MPIE = 0 RDRF flag to 0 to 1 again a.
Page 346: Synchronous Operation
11.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
Page 347 SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 348 Transmitting Serial Data (Synchronous Mode): Figure 11-16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit Start transmitting data in TDR and clear the TDRE flag to 0.
Page 349 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 350 Receiving Serial Data (Synchronous Mode): Figure 11-18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 351 Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 11-18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. • The SCI synchronizes with serial clock input or output and initializes internally. •...
Page 352 Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt handler request reads data in RDR and request Overrun error, clears RDRF flag to 0 ERI request 1 frame Figure 11-19 Example of SCI Receive Operation...
Page 353 Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 11-20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. SCI initialization: the transmit data output function of the TxD pin and Initialize receive data input function of the RxD pin are selected, enabling Start transmitting and receiving...
Page 354: Sci Interrupts
11.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11- 12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in SCR.
Page 355 Table 11-13 SSR Status Flags and Transfer of Receive Data Receive Data Transfer RSR → → RDR RDRF ORER Receive Errors × Overrun error Framing error Parity error × Overrun error + framing error × Overrun error + parity error Framing error + parity error ×...
Page 356 Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock.
Page 357 Restrictions in Synchronous Mode: When data transmission is performed using an external clock source as the serial clock, an interval of at least 5 states is necessary between clearing the TDRE bit in SSR and the start (falling edge) of the first transmit clock pulse corresponding to each frame (figure 11-22).
Page 359: Section 12 A/D Converter
Section 12 A/D Converter 12.1 Overview The H8/3035 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. 12.1.1 Features A/D converter features are listed below. • 10-bit resolution • Eight input channels •...
Page 360: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A – ø/8 Comparator Analog Control circuit multi- plexer Sample-and- ø/16 hold circuit interrupt ADTRG Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA:...
Page 361: Input Pins
12.1.3 Input Pins Table 12-1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter. V is the A/D conversion reference voltage.
Page 362: Register Configuration
12.1.4 Register Configuration Table 12-2 summarizes the A/D converter’s registers. Table 12-2 A/D Converter Registers Address Name Abbreviation Initial Value H'FFE0 A/D data register A (high) ADDRAH H'00 H'FFE1 A/D data register A (low) ADDRAL H'00 H'FFE2 A/D data register B (high) ADDRBH H'00 H'FFE3...
Page 363 an A/D data register are reserved bits that always read 0. Table 12-3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP).
Page 364: A/D Control/Status Register (Adcsr)
12.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts...
Page 365 Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE Description A/D end interrupt request (ADI) is disabled (Initial value) A/D end interrupt request (ADI) is enabled Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 $'75* during A/D conversion.
Page 366: A/D Control Register (Adcr)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection Channel Selection Description Single Mode Scan Mode (Initial value) , AN...
Page 367: Cpu Interface
12.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
Page 368: Operation
Upper-byte read Module data bus Bus interface (H'AA) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Lower-byte read Module data bus Bus interface (H'40) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Figure 12-2 A/D Data Register Access Operation (Reading H'AA40) 12.4 Operation The A/D converter operates by successive approximations with 10-bit resolution.
Page 369: Single Mode (Scan = 0)
12.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends.
Page 370 Figure 12-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 371: Scan Mode (Scan = 1)
12.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 372 Figure 12-4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected)
Page 373: Input Sampling And A/D Conversion Time
12.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 12-5 shows the A/D conversion timing.
Page 374: External Trigger Input Timing
Table 12-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay t — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 12.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 375: Interrupts
12.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 12.6 Usage Notes When using the A/D converter, note the following points: Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input ≤...
Page 377: Section 13 Ram
Section 13 RAM 13.1 Overview The H8/3035 Series has 4 kbytes of on-chip static RAM. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable for rapid data transfer.
Page 378: Register Configuration
13.1.2 Register Configuration The on-chip RAM is controlled by the system control register (SYSCR). Table 13-1 gives the address and initial value of SYSCR. Table 13-1 RAM Control Register Address* Name Abbreviation Initial Value H'FFF2 System control register SYSCR H'0B Note: * Lower 16 bits of the address 13.2 System Control Register (SYSCR) SSBY...
Page 379: Operation
When the RAME bit is set to 1 in mode 3, accesses to addresses H'FEF10 to H'FFF0F of the H8/3035 Series are directed to the on-chip RAM space. When the RAME bit is cleared to 0, read accesses to such addresses always return H'FF, while write accesses are invalid.
Page 381: Section 14 Rom
Figure 14-1 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001 H'0002 H'0003 On-chip ROM H'3FFFE H'3FFFF Even addresses Odd addresses Figure 14-1 H8/3035 Series ROM Block Diagram (H8/3035)
Page 382: Prom Mode
14.2 PROM Mode 14.2.1 PROM Mode Setting In PROM mode, the H8/3035 version with on-chip PROM suspends its microcontroller functions, enabling the on-chip PROM to be programmed through the same pin function as the HN27C4001. Note that the PROM requires use of a PROM programmer supporting this LSI. Also note that page programming and option page programming are not supported in PROM mode.
Page 383 H8/3035 PROM Socket FP-80A, TFP-80C HN27C4001 (32 pin) RESO EA9EA15EA16EA18EO0EO1EO2EO3EO4EO5EO6EO7EA0EA1EA2EA3EA4EA5EA6EA7EA8 EA10EA11EA12EA13EA14 EA17 STBY Legend Programming voltage (12.5 V) EO7 – EO0 : Data input/output EA18 – EA0 : Address input Output enable Chip enable Notes : Pins not shown in this diagram should be left open. Figure 14-2 Socket Adapter Pin Assignments...
Page 384: Programming
Address in Address in MCU mode PROM mode H'00000 H'00000 On-chip PROM H'3FFFF H'3FFFF Unused* address area H'7FFFF H'7FFFF Note * When this address is read in PROM mode, the output data should be H'FF. Figure 14-3 H8/3035 Memory Map in PROM Mode 14.3 Programming Table 14-3 indicates how to select the program, verify, and other modes in PROM mode.
Page 385: Programming And Verification
The page programming and option page programming are not supported. Do not select the page programming or option page programming mode. When selecting a PROM programmer, check that it supports this chip. Be sure to set the address range to H'00000 to H'3FFFF. 14.3.1 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data.
Page 386 Table 14-4 DC Characteristics —Preliminary— (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Item Symbol Min Unit Test Conditions Input high to EO , EA — + 0.3 V &( voltage to EA...
Page 387 Table 14-5 AC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) Item Symbol Unit Test Conditions Address setup time — — µs Figure 14-5 setup time — — µs Data setup time —...
Page 388: Programming Precautions
Program Verify Address Data Input data Output data Note: is defined by the value given in the flowchart. Figure 14-5 PROM Program/Verify Timing 14.3.2 Programming Precautions • Program with the specified voltages and timing. The programming voltage (V ) in PROM mode is 12.5 V. Applied voltages in excess of the rated values can permanently destroy the chip.
Page 389: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 391: Section 15 Clock Pulse Generator
Section 15 Clock Pulse Generator 15.1 Overview The H8/3035 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø) and other internal clock signals (ø/2 to ø/4096). The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, and prescalers.
Page 392: Connecting A Crystal Resonator
15.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 15-2. The damping resistance Rd should be selected according to table 15-1. An AT-cut parallel- resonance crystal should be used. EXTAL XTAL = 10 pF to 22 pF Figure 15-2 Connection of Crystal Resonator (Example)
Page 393 Use a crystal resonator with a frequency equal to the system clock frequency (ø). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation.
Page 394: External Clock Input
15.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 15-5. In example b, the clock should be held high in standby mode. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. EXTAL External clock input XTAL...
Page 395 External Clock: The external clock frequency should be equal to the system clock frequency (ø). Table 15-3 and figure 15-6 indicate the clock timing. Table 15-3 Clock Timing = 2.7 V to = 5.0 V 5.5 V ±10% Item Symbol Unit Test Conditions External clock rise...
Page 396: Duty Adjustment Circuit
EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t ). As clock signal output is not confirmed during the t DEXT DEXT period, the reset signal should be driven low and the reset state maintained during this time. Table 15-4 External Clock Output Stabilization Delay Time Conditions: V = 2.7 to 5.5 V, AV...
Page 397: Section 16 Power-Down State
Section 16 Power-Down State 16.1 Overview The H8/3035 Series has a power-down state that greatly reduces power consumption by halting CPU functions. The power-down state includes the following three modes: • Sleep mode • Software standby mode • Hardware standby mode Table 16-1 indicates the methods of entering and exiting these power-down modes and the status of the CPU and on-chip supporting modules in each mode.
Page 398: Register Configuration
16.2 Register Configuration The system control register (SYSCR) controls the power-down state. Table 16-2 summarizes this register. Table 16-2 Control Register Address* Name Abbreviation Initial Value H'FFF2 System control register SYSCR H'0B Note: * Lower 16 bits of the address. 16.2.1 System Control Register (SYSCR) SSBY STS2...
Page 399: Sleep Mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description SLEEP instruction causes transition to sleep mode...
Page 400: Exit From Sleep Mode
16.3.2 Exit from Sleep Mode 67%< Sleep mode is exited by an interrupt, or by input at the pin. Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module.
Page 401: Selection Of Oscillator Waiting Time After Exit From Software Standby Mode
16.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR should be set as follows. Crystal Resonator: Set STS2 to STS0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 402: Usage Note
Clock oscillator ø NMIEG SSBY NMI exception Software standby Oscillator NMI exception handling mode (power- settling time handling NMIEG = 1 down state) osc2 SSBY = 1 SLEEP instruction Figure 16-1 NMI Timing for Software Standby Mode (Example) 16.4.5 Usage Note The I/O ports retain their existing states in software standby mode.
Page 403: Exit From Hardware Standby Mode
16.5.2 Exit from Hardware Standby Mode 67%< Hardware standby mode is exited by inputs at the pins. While is low, when 67%< goes high, the clock oscillator starts running. should be held low long enough for the clock oscillator to settle. When goes high, reset exception handling begins, followed by a transition to the program execution state.
Page 405: Section 17 Electrical Characteristics (Preliminary)
Section 17 Electrical Characteristics (Preliminary) 17.1 Absolute Maximum Ratings Table 17-1 lists the absolute maximum ratings. Table 17-1 Absolute Maximum Ratings —Preliminary— Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.5 Input voltage (except port 7) –0.3 to V +0.3 Input voltage (port 7)
Page 406: Electrical Characteristics
17.2 Electrical Characteristics 17.2.1 DC Characteristics Table 17-2 lists the DC characteristics. Table 17-3 lists the permissible output currents. Table 17-2 DC Characteristics – Preliminary – Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V*, T...
Page 407 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 408 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions Input...
Page 409 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 410 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Min...
Page 411 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 412 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 413 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V*, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 414 Table 17-2 DC Characteristics (cont) – Preliminary – Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ...
Page 415 Table 17-3 Permissible Output Currents – Preliminary – Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Min...
Page 416 This LSI 2 kΩ Port Darlington pair Figure 17-1 Darlington Pair Drive Circuit (Example) This LSI Ports 600Ω Figure 17-2 LED Drive Circuit (Example)
Page 417: Ac Characteristics
17.2.2 AC Characteristics Bus timing parameters are listed in table 17-4. Control signal timing parameters are listed in table 17-5. Timing parameters of the on-chip supporting modules are listed in table 17-6. Table 17-4 Bus Timing – Preliminary – Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø...
Page 418 Table 17-4 Bus Timing (cont) – Preliminary – Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø...
Page 419 Note: At 8 MHz, the following times depend on the clock cycle time as shown below. = 1.5 × t = 1.0 × t – 68 (ns) – 40 (ns) ACC1 WSW1 = 2.5 × t = 1.5 × t –...
Page 420 Table 17-5 Control Signal Timing – Preliminary – Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø...
Page 421 Table 17-6 Timing of On-Chip Supporting Modules – Preliminary – Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø...
Page 422 Table 17-6 Timing of On-Chip Supporting Modules (cont) – Preliminary – Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø...
Page 423 C = 90 pF: ports 1, 2, 3, 5, 6, 8, ø H8/3035 Series C = 30 pF: ports 9, A, B output pin Ω R = 2.4 k Ω R = 12 k Input/output timing measurement levels • Low: 0.8 V •...
Page 424: A/D Conversion Characteristics
17.2.3 A/D Conversion Characteristics Table 17-7 lists the A/D conversion characteristics. Table 17-7 A/D Converter Characteristics – Preliminary – Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø...
Page 425: Operational Timing
17.3 Operational Timing This section shows timing diagrams. 17.3.1 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 17-4 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 17-5 shows the timing of the external three-state access cycle.
Page 426 ø to A ACC4 ACC4 RD (read) ACC2 to D (read) WSW2 WR (write) WDS2 to D (write) Figure 17-5 Basic Bus Cycle: Three-State Access ø to A RD (read) to D (read) WR (write) to D (write) WAIT Figure 17-6 Basic Bus Cycle: Three-State Access with One Wait State...
Page 427: Control Signal Timing
17.3.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 17-7 shows the reset input timing. • Reset output timing Figure 17-8 shows the reset output timing. • Interrupt input timing Figure 17-9 shows the interrupt input timing for NMI and ø...
Page 428: Clock Timing
ø NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (I = 0 to 4) NMIW (J = 0 to 2) Figure 17-9 Interrupt Input Timing 17.3.3 Clock Timing Clock timing is shown below. • Oscillator settling timing Figure 17-10 shows the oscillator settling timing.
Page 429: Tpc And I/O Port Timing
17.3.4 TPC and I/O Port Timing TPC and I/O port timing is shown below. ø Ports 1 to 3, 5 to 9, A, and B (read) Ports 1 to 3, 5, 6, 8, 9, A, and B (write) Figure 17-11 TPC and I/O Port Input/Output Timing 17.3.5 ITU Timing ITU timing is shown as follows: •...
Page 430: Sci Input/Output Timing
TCKS ø TCKS TCLKA to TCLKD TCKWL TCKWH Figure 17-13 ITU External Clock Input Timing 17.3.6 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 17-14 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 17-15 shows the SCI input/output timing in synchronous mode.
Page 431: Appendix A Instruction Set
Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 432 Condition Code Notation Symbol Description ↑ Changed according to execution result ↓ Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes...
Page 433 Table A-1 Instruction Set Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — × × — Rs8 → Rd8 MOV.B Rs, Rd — — × ×...
Page 434 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation @aa:24 → Rd16 MOV.W @aa:24,Rd W — — — Rs16 → @ERd MOV.W Rs, @ERd W — — — Rs16 → @(d:16, ERd) MOV.W Rs, —...
Page 435 PUSH.L ERn — — — ERn32 → @SP MOVFPE @aa:16, Cannot be used in the Cannot be used in the H8/3035 Series H8/3035 Series MOVTPE Rs, Cannot be used in the Cannot be used in the @aa:16 H8/3035 Series H8/3035 Series...
Page 436 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — Rd8 decimal adjust → DAA Rd —...
Page 437 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32 ÷ Rs16 DIVXU. W Rs, ERd W — — (6) (7) — — →ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷ Rs8 → Rd16 DIVXS.
Page 438 Table A-1 Instruction Set (cont) Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd W —...
Page 439 Table A-1 Instruction Set (cont) Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd — — SHAR.L ERd —...
Page 440 Table A-1 Instruction Set (cont) Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd B —...
Page 441 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬...
Page 442 Table A-1 Instruction Set (cont) Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation BRA d:8 (BT d:8) — If condition Always — — — — — — is true the PC← PC+d else next;...
Page 443 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation BLE d:8 — If condition Z v (N⊕V) — — — — — — is true the PC← PC+d else next; BLE d:16 —...
Page 444 Table A-1 Instruction Set (cont) System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — CCR → @–SP → PC CCR ← @SP+ —...
Page 445 Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. 3. Normal mode cannot be used with the H8/3035 Series.
Page 446: Operation Code Maps
A.2 Operation Code Maps Table A-2 Operation Code Map (1) 1st byte 2nd byte Instruction code: Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. Table A.2 Table A.2 Table A.2 Table A.2 XORC ANDC...
Page 447 Table A-2 Operation Code Map (2) 1st byte 2nd byte Instruction code: AH AL Table A.2 Table A.2 Table A.2 LDC/STC SLEEP ADDS ADDS SHLL SHAL SHLL SHAL SHLR SHAR SHLR SHAR ROTXL ROTL ROTXL ROTL ROTXR ROTXR ROTR ROTR EXTU EXTU EXTS...
Page 448 Table A-2 Operation Code Map (3) 1st byte 2nd byte 3rd byte 4th byte Instruction code: Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. ALBH BLCH 01406 01C05 MULXS MULXS 01D05 DIVXS DIVXS...
Page 449: Number Of States Required For Execution
A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A-3 indicates the number of states required per cycle according to the bus size. Table A-4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction.
Page 450 Table A-3 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 16-Bit 2-State 3-State 2-State 3-State Cycle Memory 8-Bit Bus Access Access Access Access Instruction 6 + 2m 3 + m fetch Branch address read Stack...
Page 451 Table A-4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd ADDX...
Page 452 Table A-4 Number of Cycles per Instruction (cont) Instructio Branch Stack Byte Data Word Data Internal n Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
Page 453 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA Rd DAS Rd Note: Normal mode cannot be used with the H8/3035 Series.
Page 454 LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. Normal mode cannot be used with the H8/3035 Series.
Page 455 MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @–ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 Note: Normal mode cannot be used with the H8/3035 Series.
Page 456 PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd Note: * Normal mode cannot be used with the H8/3035 Series.
Page 457 SUBX Rs, Rd TRAPA TRAPA #x:2 Normal* Advanced XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR Note: * Normal mode cannot be used with the H8/3035 Series.
Page 459: Appendix B Internal I/O Register Field
Appendix B Internal I/O Register Field B.1 Addresses Bit Names Data Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'1C H'1D H'1E H'1F H'20 — —...
Page 460 (Continued from preceding page) Bit Names Data Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'3B — — — — — — — — — H'3C —...
Page 461 (Continued from preceding page) Bit Names Address Register Data Bus Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'60 TSTR — — — STR4 STR3 STR2 STR1 STR0 ITU (all channels)
Page 462 (Continued from preceding page) Bit Names Address Register Data Bus Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'82 TCR3 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 channel 3 H'83...
Page 463 (Continued from preceding page) Bit Names Address Register Data Bus Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'A0 TPMR — — — — G3NOV G2NOV G1NOV G0NOV TPC H'A1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0...
Page 464 (Continued from preceding page) Bit Names Address Register Data Bus Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'B8 — — — — — — — — —...
Page 465 (Continued from preceding page) Bit Names Address Register Data Bus Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'D8 P2PCR Port 2 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR H'D9 —...
Page 466 (Continued from preceding page) Bit Names Address Register Data Bus Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'F0 — — — — — — — — —...
Page 467: Function
B.2 Function Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR Timer Start Register H'60 ITU (all channels) numbers Initial bit — — — STR4 STR3 STR2 STR1 STR0 values Initial value Names of the Read/Write —...
Page 468: Tstr-Timer Start Register H'60 Itu (All Channels)
TSTR—Timer Start Register H'60 ITU (all channels) — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — — Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting...
Page 469: Tsnc-Timer Synchro Register H'61 Itu (All Channels)
TSNC—Timer Synchro Register H'61 ITU (all channels) — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized...
Page 470: Tmdr-Timer Mode Register H'62 Itu (All Channels)
TMDR—Timer Mode Register H'62 ITU (all channels) — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value Read/Write — PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally...
Page 471: Tfcr-Timer Function Control Register H'63 Itu (All Channels)
TFCR—Timer Function Control Register H'63 ITU (all channels) — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — — Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally...
Page 472: Tcr0-Timer Control Register 0 H'64 Itu0
TCR0—Timer Control Register 0 H'64 ITU0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 0 Bit 1 TPSC2 TPSC1 TPSC0 TCNT Clock Source Internal clock: ø Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input...
Page 473: Tior0-Timer I/O Control Register 0 H'65 Itu0
TIOR0—Timer I/O Control Register 0 H'65 ITU0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 GRA Function GRA is an output No output at compare match compare register 0 output at GRA compare match...
Page 474: Tier0-Timer Interrupt Enable Register 0 H'66 Itu0
TIER0—Timer Interrupt Enable Register 0 H'66 ITU0 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA is disabled 1 IMIA interrupt requested by IMFA is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB is disabled 1 IMIB interrupt requested by IMFB is enabled...
Page 475: Tsr0-Timer Status Register 0 H'67 Itu0
TSR0—Timer Status Register 0 H'67 ITU0 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] TCNT = GRA when GRA functions as a compare match register.
Page 476: Tcnt0 H/L-Timer Counter 0 H/L H'68, H'69 Itu0
TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 Initial value Read/Write Output compare or input capture register TCR1—Timer Control Register 1 H'6E...
Page 477: Tior1-Timer I/O Control Register 1 H'6F Itu1
TIOR1—Timer I/O Control Register 1 H'6F ITU1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 H'70 ITU1 — — — — —...
Page 478: Gra1 H/L-General Register A1 H/L H'74, H'75 Itu1
GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 H'78 ITU2...
Page 479: Tior2-Timer I/O Control Register 2 H'79 Itu2
TIOR2—Timer I/O Control Register 2 H'79 ITU2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Notes: 1. Bit functions are the same as for ITU0. Channel 2 does not have a compare match toggle output function. If this setting is used, 1 output will be selected automatically.
Page 480: Tcnt2 H/L-Timer Counter 2 H/L H'7C, H'7D Itu2
TCNT2 H/L—Timer Counter 2 H/L H'7C, H'7D ITU2 Initial value Read/Write Phase counting mode: up/down-counter Other modes: up-counter GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2 Initial value...
Page 481: Tcr3-Timer Control Register 3 H'82 Itu3
TCR3—Timer Control Register 3 H'82 ITU3 — CCLR1 CCLR0 CKEG1 CLEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR3—Timer I/O Control Register 3 H'83 ITU3 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value...
Page 482: Tsr3-Timer Status Register 3 H'85 Itu3
TSR3—Timer Status Register 3 H'85 ITU3 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Bit functions are the same as for ITU0 Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF...
Page 483: Tcnt3 H/L-Timer Counter 3 H/L H'86, H'87 Itu3
TCNT3 H/L—Timer Counter 3 H/L H'86, H'87 ITU3 Initial value Read/Write Complementary PWM mode: up/down counter Other modes: up-counter GRA3 H/L—General Register A3 H/L H'88, H'89 ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3 Initial value...
Page 484: Bra3 H/L-Buffer Register A3 H/L H'8C, H'8D Itu3
BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3 Initial value Read/Write Used to buffer GRA BRB3 H/L—Buffer Register B3 H/L H'8E, H'8F ITU3 Initial value Read/Write Used to buffer GRB TOER—Timer Output Enable Register H'90 ITU (all channels)
Page 485 — — EXB4 EXA4 Initial value Read/Write — — Master enable TIOCA 0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA 0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings Master enable TIOCB...
Page 486: Tocr-Timer Output Control Register H'91 Itu (All Channels)
TOCR—Timer Output Control Register H'91 ITU (all channels) — — — XTGD — — OLS4 OLS3 Initial value Read/Write — — — — — Output level select 3 0 TIOCB , TOCXA , and TOCXB outputs are inverted 1 TIOCB , TOCXA , and TOCXB outputs are not inverted Output level select 4 0 TIOCA , TIOCA , and TIOCB outputs are inverted 1 TIOCA , TIOCA , and TIOCB outputs are not inverted...
Page 487: Tcr4-Timer Control Register 4 H'92 Itu4
TCR4—Timer Control Register 4 H'92 ITU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR4—Timer I/O Control Register 4 H'93 ITU4 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value...
Page 488: Tcnt4 H/L-Timer Counter 4 H/L H'96, H'97 Itu4
TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4...
Page 489: Brb4 H/L-Buffer Register B4 H/L H'9E, H'9F Itu4
BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3.
Page 490: Tpmr-Tpc Output Mode Register H'a0 Tpc
TPMR—TPC Output Mode Register H'A0 — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Group 0 non-overlap 0 Normal TPC output in group 0 Output values change at compare match A in the selected ITU channel 1 Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected ITU channel Group 1 non-overlap...
Page 491: Tpcr-Tpc Output Control Register H'a1 Tpc
TPCR—TPC Output Control Register H'A1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 ITU Channel Selected as Output Trigger TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 0 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 1 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 2 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 3...
Page 492: Nderb-Next Data Enable Register B H'a2 Tpc
NDERB—Next Data Enable Register B H'A2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 Description TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP to TP are enabled (NDR15 to NDR8 are transferred to PB to PB )
Page 493: Ndrb-Next Data Register B H'a4/H'a6 Tpc
NDRB—Next Data Register B H'A4/H'A6 • Same output trigger for TPC output groups 2 and 3 Address H'FFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Next output data for Next output data for TPC output group 3 TPC output group 2 Address H'FFA6 —...
Page 494: Ndra-Next Data Register A H'a5/H'a7 Tpc
NDRA—Next Data Register A H'A5/H'A7 • Same output trigger for TPC output groups 0 and 1 Address H'FFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Next output data for Next output data for TPC output group 1 TPC output group 0 Address H'FFA7 —...
Page 495: Tcnt-Timer Counter H'a9 (Read), Wdt H'a8 (Write)
TCNT—Timer Counter H'A9 (read), H'A8 (write) Initial value Read/Write Interval at which RTCNT is cleared RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) WRST RSTOE — — — — — — Initial value Read/Write R/(W) — — — — — — Reset output enable 0 Reset signal is not output externally 1 Reset signal is output externally...
Page 496: Tcsr-Timer Control/Status Register H'a8 Wdt
TCSR—Timer Control/Status Register H'A8 — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Timer enable Clock select 2 to 0 TCNT is initialized to H'00 and halted CKS2 CKS1 CKS0 Description ø/2 TCNT is counting ø/32 Timer mode select ø/64 0 Interval timer: requests interval timer interrupts ø/128...
Page 497: Smr-Serial Mode Register H'b0 Sci
SMR—Serial Mode Register H'B0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source ø clock Multiprocessor mode ø/4 clock 0 Multiprocessor function disabled ø/16 clock 1 Multiprocessor format selected ø/64 clock Stop bit length 0 One stop bit 1 Two stop bits...
Page 498: Brr-Bit Rate Register H'b1 Sci
BRR—Bit Rate Register H'B1 Initial value Read/Write Serial communication bit rate setting...
Page 499: Scr-Serial Control Register H'b2 Sci
SCR—Serial Control Register H'B2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Bit 1 Bit 2 CKE1 CKE2 Clock Selection and Output Asynchronous mode Internal clock, SCK pin available for generic input/output Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode Internal clock, SCK pin used for clock output Synchronous mode...
Page 500: Tdr-Transmit Data Register H'b3 Sci
TDR—Transmit Data Register H'B3 Initial value Read/Write Serial transmit data...
Page 501: Ssr-Serial Status Register H'b4 Sci
SSR—Serial Status Register H'B4 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit Multiprocessor bit transfer Multiprocessor bit value in Multiprocessor bit value in receive data is 0 transmit data is 0 Multiprocessor bit value in Multiprocessor bit value in receive data is 1 transmit data is 1...
Page 502: Rdr-Receive Data Register H'b5 Sci
RDR—Receive Data Register H'B5 Initial value Read/Write Serial receive data P1DDR—Port 1 Data Direction Register H'C0 Port 1 Initial value Read/Write Port 1 input/output select 0 Generic input 1 Generic output P2DDR—Port 2 Data Direction Register H'C1 Port 2 Initial value Read/Write Port 2 input/output select 0 Generic input...
Page 503: P1Dr-Port 1 Data Register H'c2 Port 1
P1DR—Port 1 Data Register H'C2 Port 1 Initial value Read/Write Data for port 1 pins P2DR—Port 2 Data Register H'C3 Port 2 Initial value Read/Write Data for port 2 pins P3DDR—Port 3 Data Direction Register H'C4 Port 3 Initial value Read/Write Port 3 input/output select 0 Generic input...
Page 504: P5Ddr-Port 5 Data Direction Register H'c8 Port 5
P5DDR—Port 5 Data Direction Register H'C8 Port 5 — — — — P5 DDR P5 DDR P5 DDR P5 DDR Initial value Read/Write — — — — Port 5 input/output select 0 Generic input 1 Generic output P6DDR—Port 6 Data Direction Register H'C9 Port 6 —...
Page 505: P6Dr-Port 6 Data Register H'cb Port 6
P6DR—Port 6 Data Register H'CB Port 6 — — — — Initial value Read/Write — Data for port 6 pins P8DDR—Port 8 Data Direction Register H'CD Port 8 — — — — P8 DDR P8 DDR P8 DDR P8 DDR Initial value Read/Write —...
Page 506: P8Dr-Port 8 Data Register H'cf Port 8
P8DR—Port 8 Data Register H'CF Port 8 — — — — Initial value Read/Write — — — Data for port 8 pins P9DDR—Port 9 Data Direction Register H'D0 Port 9 — — — P9 DDR — P9 DDR — P9 DDR Initial value Read/Write —...
Page 507: P9Dr-Port 9 Data Register H'd2 Port 9
P9DR—Port 9 Data Register H'D2 Port 9 — — — — — Initial value Read/Write — — Data for port 9 pins PADR—Port A Data Register H'D3 Port A Initial value Read/Write Data for port A pins PBDDR—Port B Data Direction Register H'D4 Port B PB DDR PB DDR...
Page 508: Pbdr-Port B Data Register H'd6 Port B
PBDR—Port B Data Register H'D6 Port B Initial value Read/Write Data for port B pins P2PCR—Port 2 Input Pull-Up Control Register H'D8 Port 2 P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up control 7 to 0...
Page 509: Addra H/L-A/D Data Register A H/L H'e0, H'e1 A/D
ADDRA H/L—A/D Data Register A H/L H'E0, H'E1 — — — — — — Initial value Read/Write ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 — — — —...
Page 510: Addrd H/L-A/D Data Register D H/L H'e6, H'e7 A/D
ADDRD H/L—A/D Data Register D H/L H'E6, H'E7 — — — — — — Initial value Read/Write ADDRDH ADDRDL A/D conversion data 10-bit data giving an A/D conversion result ADCR—A/D Control Register H'E9 TRGE — — — — — — —...
Page 511: Adcsr-A/D Control/Status Register H'e8 A/D
ADCSR—A/D Control/Status Register H'E8 ADIE ADST SCAN Initial value Read/Write R/(W) Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Selection Selection Description Single Mode Scan Mode Scan mode AN , AN 0 Single mode...
Page 512: Astcr-Access State Control Register H'ed Bus Controller
ASTCR—Access State Control Register H'ED Bus controller AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Area 7 to 0 access state control Bits 7 to 0 AST7 to AST0 Number of States in Access Cycle Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas...
Page 513: Wcr-Wait Control Register H'ee Bus Controller
WCR—Wait Control Register H'EE Bus controller — — — — WMS1 WMS0 Initial value Read/Write — — — — Wait mode select 1 and 0 Wait count 1 and 0 Bit 3 Bit 2 Bit 1 Bit 0 WMS1 WMS0 Wait Mode Number of Wait States Programmable wait mode...
Page 514: Wcer-Wait Controller Enable Register H'ef Bus Controller
WCER—Wait Controller Enable Register H'EF Bus controller WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0 Initial value Read/Write Wait state controller enable 7 to 0 0 Wait-state control is disabled (pin wait mode 0) 1 Wait-state control is enabled MDCR—Mode Control Register H'F1 System control —...
Page 515: Syscr-System Control Register H'f2 System Control
SYSCR—System Control Register H'F2 System control SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit...
Page 516: Adrcr-Address Control Register H'f3 Bus Controller
ADRCR—Address Control Register H'F3 Bus controller A23E A22E A21E — — — — — Initial value Modes 1 and 3 Read/Write — — — — — — — Initial value Mode 2 Read/Write — — — — PA6 to PA4 (A23 to A21) address output select 0 Address output 1 I/O pins other than the above...
Page 517: Iscr-Irq Sense Control Register H'f4 Interrupt Controller
ISCR—IRQ Sense Control Register H'F4 Interrupt controller — — — IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control 0 Interrupts are requested when IRQ to IRQ inputs are low 1 Interrupts are requested by falling-edge input at IRQ to IRQ IER—IRQ Enable Register H'F5 Interrupt controller...
Page 518: Isr-Irq Status Register H'f6 Interrupt Controller
ISR—IRQ Status Register H'F6 Interrupt controller — — — IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * IRQ to IRQ flags Bits 4 to 0 IRQ4F to IRQ0F Setting and Clearing Conditions [Clearing conditions] Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
Page 519: Ipra-Interrupt Priority Register A H'f8 Interrupt Controller
IPRA—Interrupt Priority Register A H'F8 Interrupt controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 521: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Software standby Mode 3 Hardware standby Mode 1 mode 3 Reset WP1D Mode 3 Reset Mode 1/2 WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 n = 0 to 7 Set priority Figure C-1 Port 1 Block Diagram...
Page 522: Port 2 Block Diagram
C.2 Port 2 Block Diagram Reset Software standby Mode 3 RP2P WP2P Hardware standby Mode 1 to mode 3 Reset WP2D Mode 3 Reset Mode 1/2 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2: Read port 2 n = 0 to 7...
Page 523: Port 3 Block Diagram
C.3 Port 3 Block Diagram Reset Hardware Mode 3 standby Write to external address WP3D Reset Mode 3 Mode 1/2 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7 Figure C-3 Port 3 Block Diagram...
Page 524: Port 5 Block Diagram
C.4 Port 5 Block Diagram Reset Software standby Mode 3 RP5P Hardware standby WP5P Mode 1 to Mode 3 Reset WP5D Mode 3 Reset Mode 1/2 WP5P: Write to P5PCR RP5P: Read P5PC4 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 n = 0 to 3...
Page 525: Port 6 Block Diagram
C.5 Port 6 Block Diagram Reset Bus controller Mode 3 WP6D WAIT Reset input enable Bus controller WAIT input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-5 (a) Port 6 Block Diagram (Pin P6...
Page 526 Software standby Mode 3 Hardware standby Reset WP6D Reset Mode 3 Mode 1/2 AS output RD output WR output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 3 to 5 Figure C-5 (b) Port 6 Block Diagram (Pins P6 to P6...
Page 527: Port 7 Block Diagram
C.6 Port 7 Block Diagram A/D converter Input enable Analog input RP7: Read port 7 n = 0 to 7 Figure C-6 Port 7 Block Diagram...
Page 528: Port 8 Block Diagram
C.7 Port 8 Block Diagram Reset WP8D Reset Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C-7(a) Port 8 Block Diagram (Pin P8...
Page 529 Reset WP8D Reset Mode 3 Mode 1/2 Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 1 to 3 Figure C-7 (b) Port 8 Block Diagram (Pin 8...
Page 530: Port 9 Block Diagram
C.8 Port 9 Block Diagram Reset WP9D Reset Output enable Serial transmit data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-8 (a) Port 9 Block Diagram (Pin P9...
Page 531 Reset WP9D Input enable Reset Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-8 (b) Port 9 Block Diagram (Pin P9...
Page 532 Reset WP9D Clock input enable Reset Clock output enable Clock output Clock input WP9D: Write to P9DDR WP9: Write to port 9 Interrupt controller RP9: Read port 9 input Figure C-8 (c) Port 9 Block Diagram (Pin P9...
Page 533: Port A Block Diagram
C.9 Port A Block Diagram Reset WPAD Reset TPC output enable Next data Output trigger Counter input clock WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 or 1 Figure C-9 (a) Port A Block Diagram (Pins PA , PA...
Page 534 Reset WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input Counter input clock WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 2 or 3 Figure C-9 (b) Port A Block Diagram (Pins PA , PA...
Page 535 Software standby Address output enable Mode 2 Reset WPAD TPC output Reset enable Next data Output trigger Output enable Compare match output Input capture input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 4 to 7 Note: PA address output enable is fixed at 1 in mode 2.
Page 536: Port B Block Diagram
C.10 Port B Block Diagram Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 0 to 3 Figure C-10 (a) Port B Block Diagram (Pins PB to PB...
Page 537 Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 4 or 5 Figure C-10 (b) Port B Block Diagram (Pins PB , PB...
Page 538 Reset WPBD Reset TPC output enable Next data Output trigger WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C-10 (c) Port B Block Diagram (Pin PB...
Page 539 Reset WPBD Reset TPC output enable Next data Output trigger A/D converter ADTRG input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C-10 (d) Port B Block Diagram (Pin PB...
Page 541: Appendix D Pin States
Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Hardware Software Program Reset Standby Standby Sleep Execution Name Mode State Mode Mode Mode State ø — Clock output T Clock output Clock output to P1 1, 2 keep keep...
Page 542 Table D-1 Port States (cont) Hardware Software Reset Standby Standby Sleep Program Execution Name Mode State Mode Mode Mode State to P7 1 to 3 T Input port to P8 1 to 3 T keep keep I/O port , P9 1 to 3 T keep keep...
Page 543: Pin States At Reset
D.2 Pin States at Reset Reset in T State: Figure D-1 is a timing diagram for the case in which goes low during the T state of an external memory access cycle. As soon as goes low, all ports are initialized to the input state.
Page 544 Access to external address ø Internal reset signal Address bus H'000000 (mode 1) AS (mode 1) RD (read access) (mode 1) WR (write access) (mode 1) Data bus High impedance (write access) (mode 1) High impedance I/O port (modes 1 to 3) Figure D-2 Reset during Memory Access (Reset during T State) Reset in T...
Page 545 Access to external address ø Internal reset signal Address bus H'000000 (mode 1) AS (mode 1) RD (read access) (mode 1) WR (write access) (mode 1) High impedance Data bus (write access) (mode 1) High impedance I/O port (modes 1 to 3) Figure D-3 Reset during Memory Access (Reset during T State)
Page 547: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the signal low 10 67%< system clock cycles before the signal goes low, as shown below.
Page 549: Appendix F Product Code Lineup
Appendix F Product Code Lineup Table F-1 H8/3035 Series Product Code Lineup Product Type Product Code Mark Code Package (Hitachi Package Code) H8/3035 PROM Standard HD6473035F HD6473035F 80-pin QFP version product (FP-80A) HD6473035TE HD6473035TE 80-pin TQFP (TFP-80C) Mask HD6433035F HD6433035(***)F...
Page 551: Appendix G Package Dimensions
Appendix G Package Dimensions Figures G-1 and G-2 show the H8/3035 Series FP-80A and TFP-80C package dimensions. Unit: mm 17.2 ± 0.3 0.32 ± 0.08 0.12 M 0.30 ± 0.06 0.83 0° – 8° 0.8 ± 0.3 0.10 Dimension including the plating thickness...
Page 552 14.0 ± 0.2 Unit: mm 0.22 ± 0.05 0.10 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.10 Dimension including the plating thickness Base material dimension Figure G-2 Package Dimensions (TFP-80C)

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Hitachi H8/3035 Series Hardware Manual

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