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Hitachi H8/3035 Series manual available for free PDF download: Hardware Manual
Hitachi H8/3035 Series Hardware Manual (552 pages)
Single-Chip Microcomputer
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 3.06 MB
Table of Contents
Table of Contents
3
Preface
15
Section 1 Overview
17
Overview
17
Block Diagram
21
Pin Description
22
Pin Arrangement
22
Pin Functions
23
Pin Functions
26
Section 2 CPU
31
Overview
31
Features
31
Differences from H8/300 CPU
32
CPU Operating Modes
32
Address Space
33
Register Configuration
34
Overview
34
General Registers
35
Control Registers
36
Initial CPU Register Values
37
Data Formats
37
General Register Data Formats
38
Memory Data Formats
40
Instruction Set
41
Instruction Set Overview
41
Instructions and Addressing Modes
42
Tables of Instructions Classified by Function
43
Movfpe
44
Movtpe
44
Adds, - L
45
Inc, Dec - Bwl
45
Divxu B/W
46
Extu W/L
46
Neg - Bwl
46
Rts
50
Andcb
51
Nop
51
Rte
51
Sleep
51
Basic Instruction Formats
52
Addressing Modes
53
Addressing Modes and Effective Address Calculation
53
Notes on Use of Bit Manipulation Instructions
53
Effective Address Calculation
56
Overview
60
Processing States
60
Exception-Handling State
61
Program Execution State
61
Exception-Handling Sequences
62
Legend
63
Power-Down State
63
Reset State
63
Basic Operational Timing
64
On-Chip Memory Access Timing
64
Overview
64
On-Chip Supporting Module Access Timing
65
Access to External Address Space
66
Operating Mode Selection
67
Overview
67
Register Configuration
67
Section 3 MCU Operating Modes
67
Mode Control Register (MDCR)
68
System Control Register (SYSCR)
69
Mode 1
71
Mode 2
71
Mode 3
71
Operating Mode Descriptions
71
Pin Functions in each Operating Mode
71
Memory Map in each Operating Mode
72
Exception Handling Operation
75
Exception Handling Types and Priority
75
Overview
75
Section 4 Exception Handling
75
Exception Vector Table
76
Overview
77
Reset
77
Reset Sequence
77
Interrupts
78
Interrupts after Reset
78
Trap Instruction
79
Notes on Stack Usage
80
Stack Status after Exception Handling
80
Features
83
Overview
83
Section 5 Interrupt Controller
83
Block Diagram
84
Pin Configuration
85
Register Configuration
85
Register Descriptions
86
System Control Register (SYSCR)
86
Interrupt Priority Registers a and B (IPRA, IPRB)
88
IRQ Status Register (ISR)
93
IRQ Enable Register (IER)
94
IRQ Sense Control Register (ISCR)
94
External Interrupts
95
Interrupt Sources
95
Internal Interrupts
96
Interrupt Vector Table
97
Interrupt Handling Process
99
Interrupt Operation
99
Interrupt Sequence
104
Interrupt Response Time
105
Usage Notes
105
Contention between Interrupt and Interrupt-Disabling Instruction
106
Instructions that Inhibit Interrupts
107
Interrupts During EEPMOV Instruction Execution
107
Usage Notes
107
Features
111
Overview
111
Section 6 Bus Controller
111
Block Diagram
112
Input/Output Pins
112
Access State Control Register (ASTCR)
113
Register Configuration
113
Register Descriptions
113
Wait Control Register (WCR)
114
Wait State Controller Enable Register (WCER)
115
Address Control Register (ADRCR)
116
Area Division
118
Operation
118
Bus Control Signal Timing
120
Wait Modes
122
Interconnections with Memory (Example)
128
Precautions on Setting ASTCR and ABWCR
130
Register Write Timing
130
Usage Notes
130
Overview
131
Section 7 I/O Ports
131
Overview
134
Port 1
134
Register Descriptions
134
Pin Functions in each Mode
136
Overview
137
Port 2
137
Register Descriptions
137
Pin Functions in each Mode
139
Input Pull-Up Transistors
140
Overview
141
Port 3
141
Register Descriptions
141
Pin Functions in each Mode
143
Overview
144
Port 5
144
Register Descriptions
144
Pin Functions in each Mode
146
Input Pull-Up Transistors
147
Overview
148
Port 6
148
Register Descriptions
148
Pin Functions in each Mode
150
Overview
152
Port 7
152
Overview
153
Port 8
153
Register Description
153
Register Descriptions
154
Pin Functions
156
Overview
157
Port 9
157
Register Descriptions
157
Pin Functions
159
Overview
160
Port a
160
Register Descriptions
161
Pin Functions
163
Overview
167
Port B
167
Register Descriptions
168
Pin Functions
170
Features
175
Overview
175
Section 8 16-Bit Integrated Timer Unit (ITU)
175
Block Diagrams
178
Input/Output Pins
183
Register Configuration
184
Register Descriptions
186
Timer Start Register (TSTR)
186
Timer Synchro Register (TSNC)
188
Timer Mode Register (TMDR)
190
Timer Function Control Register (TFCR)
193
Timer Output Master Enable Register (TOER)
195
Timer Output Control Register (TOCR)
197
Timer Counters (TCNT)
198
General Registers (GRA, GRB)
199
Buffer Registers (BRA, BRB)
200
Timer Control Registers (TCR)
201
Timer I/O Control Register (TIOR)
203
Timer Status Register (TSR)
205
Timer Interrupt Enable Register (TIER)
207
16-Bit Accessible Registers
209
CPU Interface
209
8-Bit Accessible Registers
211
Operation
212
Overview
212
Basic Functions
214
Synchronization
221
PWM Mode
223
Reset-Synchronized PWM Mode
227
Complementary PWM Mode
229
Phase Counting Mode
238
Buffering
241
ITU Output Timing
246
Interrupts
248
Setting of Status Flags
248
Clearing of Status Flags
250
Interrupt Sources
251
Usage Notes
252
Features
267
Overview
267
Section 9 Programmable Timing Pattern Controller
267
Block Diagram
268
TPC Pins
269
Registers
270
Port a Data Direction Register (PADDR)
271
Port a Data Register (PADR)
271
Register Descriptions
271
Port B Data Direction Register (PBDDR)
272
Port B Data Register (PBDR)
272
Next Data Register a (NDRA)
273
Next Data Register B (NDRB)
275
Next Data Enable Register a (NDERA)
277
Next Data Enable Register B (NDERB)
278
TPC Output Control Register (TPCR)
279
TPC Output Mode Register (TPMR)
281
Operation
283
Overview
283
Output Timing
284
Normal TPC Output
285
Non-Overlapping TPC Output
287
Note on Non-Overlapping Output
289
Operation of TPC Output Pins
289
TPC Output Triggering by Input Capture
289
Usage Notes
289
Features
291
Overview
291
Section 10 Watchdog Timer
291
Block Diagram
292
Pin Configuration
292
Register Configuration
293
Register Descriptions
293
Timer Counter (TCNT)
293
Timer Control/Status Register (TCSR)
294
Reset Control/Status Register (RSTCSR)
296
Notes on Register Access
297
Operation
298
Watchdog Timer Operation
298
Interval Timer Operation
299
Timing of Setting of Overflow Flag (OVF)
300
Timing of Setting of Watchdog Timer Reset Bit (WRST)
300
Interrupts
301
Usage Notes
301
Features
303
Overview
303
Section 11 Serial Communication Interface
303
Block Diagram
304
Input/Output Pins
305
Register Configuration
305
Receive Data Register (RDR)
306
Receive Shift Register (RSR)
306
Register Descriptions
306
Transmit Data Register (TDR)
307
Transmit Shift Register (TSR)
307
Serial Mode Register (SMR)
308
Serial Control Register (SCR)
311
Serial Status Register (SSR)
315
Bit Rate Register (BRR)
319
Operation
327
Overview
327
Operation in Asynchronous Mode
329
Multiprocessor Communication
339
Synchronous Operation
346
SCI Interrupts
354
Usage Notes
354
Features
359
Overview
359
Section 12 A/D Converter
359
Block Diagram
360
Input Pins
361
A/D Data Registers a to D (ADDRA to ADDRD)
362
Register Configuration
362
Register Descriptions
362
A/D Control/Status Register (ADCSR)
364
A/D Control Register (ADCR)
366
CPU Interface
367
Operation
368
Single Mode (SCAN = 0)
369
Scan Mode (SCAN = 1)
371
Input Sampling and A/D Conversion Time
373
External Trigger Input Timing
374
Interrupts
375
Usage Notes
375
Block Diagram
377
Overview
377
Section 13 RAM
377
Register Configuration
378
System Control Register (SYSCR)
378
Mode 1
379
Mode 2
379
Mode 3
379
Operation
379
Block Diagram
381
Overview
381
Section 14 ROM
381
PROM Mode
382
PROM Mode Setting
382
Socket Adapter and Memory Map
382
Programming
384
Programming and Verification
385
Programming Precautions
388
Reliability of Programmed Data
389
Block Diagram
391
Oscillator Circuit
391
Overview
391
Section 15 Clock Pulse Generator
391
Connecting a Crystal Resonator
392
External Clock Input
394
Duty Adjustment Circuit
396
Prescalers
396
Overview
397
Section 16 Power-Down State
397
Register Configuration
398
System Control Register (SYSCR)
398
Sleep Mode
399
Transition to Sleep Mode
399
Exit from Sleep Mode
400
Exit from Software Standby Mode
400
Software Standby Mode
400
Transition to Software Standby Mode
400
Sample Application of Software Standby Mode
401
Selection of Oscillator Waiting Time after Exit from Software Standby Mode
401
Hardware Standby Mode
402
Transition to Hardware Standby Mode
402
Usage Note
402
Exit from Hardware Standby Mode
403
Timing for Hardware Standby Mode
403
Absolute Maximum Ratings
405
Section 17 Electrical Characteristics (Preliminary)
405
DC Characteristics
406
Electrical Characteristics
406
AC Characteristics
417
A/D Conversion Characteristics
424
Bus Timing
425
Operational Timing
425
Control Signal Timing
427
Clock Timing
428
ITU Timing
429
TPC and I/O Port Timing
429
SCI Input/Output Timing
430
Appendix A Instruction Set
431
Instruction List
431
Operation Code Maps
446
Number of States Required for Execution
449
Addresses
459
Appendix B Internal I/O Register Field
459
Function
467
TSTR-Timer Start Register H'60 ITU (All Channels)
468
TSNC-Timer Synchro Register H'61 ITU (All Channels)
469
TMDR-Timer Mode Register H'62 ITU (All Channels)
470
TFCR-Timer Function Control Register H'63 ITU (All Channels)
471
TCR0-Timer Control Register 0 H'64 ITU0
472
TIOR0-Timer I/O Control Register 0 H'65 ITU0
473
TIER0-Timer Interrupt Enable Register 0 H'66 ITU0
474
TSR0-Timer Status Register 0 H'67 ITU0
475
GRA0 H/L-General Register A0 H/L H'6A, H'6B ITU0
476
GRB0 H/L-General Register B0 H/L H'6C, H'6D ITU0
476
TCNT0 H/L-Timer Counter 0 H/L H'68, H'69 ITU0
476
TCR1-Timer Control Register 1 H'6E ITU1
476
TCNT1 H/L-Timer Counter 1 H/L H'72, H'73 ITU1
477
TIER1-Timer Interrupt Enable Register 1 H'70 ITU1
477
TIOR1-Timer I/O Control Register 1 H'6F ITU1
477
TSR1-Timer Status Register 1 H'71 ITU1
477
GRA1 H/L-General Register A1 H/L H'74, H'75 ITU1
478
GRB1 H/L-General Register B1 H/L H'76, H'77 ITU1
478
TCR2-Timer Control Register 2 H'78 ITU2
478
TIER2-Timer Interrupt Enable Register 2 H'7A ITU2
479
TIOR2-Timer I/O Control Register 2 H'79 ITU2
479
TSR2-Timer Status Register 2 H'7B ITU2
479
GRA2 H/L-General Register A2 H/L H'7E, H'7F ITU2
480
GRB2 H/L-General Register B2 H/L H'80, H'81 ITU2
480
TCNT2 H/L-Timer Counter 2 H/L H'7C, H'7D ITU2
480
TCR3-Timer Control Register 3 H'82 ITU3
481
TIER3-Timer Interrupt Enable Register 3 H'84 ITU3
481
TIOR3-Timer I/O Control Register 3 H'83 ITU3
481
TSR3-Timer Status Register 3 H'85 ITU3
482
GRA3 H/L-General Register A3 H/L H'88, H'89 ITU3
483
GRB3 H/L-General Register B3 H/L H'8A, H'8B ITU3
483
TCNT3 H/L-Timer Counter 3 H/L H'86, H'87 ITU3
483
BRA3 H/L-Buffer Register A3 H/L H'8C, H'8D ITU3
484
BRB3 H/L-Buffer Register B3 H/L H'8E, H'8F ITU3
484
TOER-Timer Output Enable Register H'90 ITU (All Channels)
484
TOCR-Timer Output Control Register H'91 ITU (All Channels)
486
TCR4-Timer Control Register 4 H'92 ITU4
487
TIER4-Timer Interrupt Enable Register 4 H'94 ITU4
487
TIOR4-Timer I/O Control Register 4 H'93 ITU4
487
TSR4-Timer Status Register 4 H'95 ITU4
487
BRA4 H/L-Buffer Register A4 H/L H'9C, H'9D ITU4
488
GRA4 H/L-General Register A4 H/L H'98, H'99 ITU4
488
GRB4 H/L-General Register B4 H/L H'9A, H'9B ITU4
488
TCNT4 H/L-Timer Counter 4 H/L H'96, H'97 ITU4
488
BRB4 H/L-Buffer Register B4 H/L H'9E, H'9F ITU4
489
TPMR-TPC Output Mode Register H'A0 TPC
490
TPCR-TPC Output Control Register H'A1 TPC
491
NDERA-Next Data Enable Register a H'A3 TPC
492
NDERB-Next Data Enable Register B H'A2 TPC
492
NDRB-Next Data Register B H'A4/H'A6 TPC
493
NDRA-Next Data Register a H'A5/H'A7 TPC
494
RSTCSR-Reset Control/Status Register H'AB (Read), WDT H'AA (Write)
495
TCNT-Timer Counter H'A9 (Read), WDT H'A8 (Write)
495
TCSR-Timer Control/Status Register H'A8 WDT
496
SMR-Serial Mode Register H'B0 SCI
497
BRR-Bit Rate Register H'B1 SCI
498
SCR-Serial Control Register H'B2 SCI
499
TDR-Transmit Data Register H'B3 SCI
500
SSR-Serial Status Register H'B4 SCI
501
P1DDR-Port 1 Data Direction Register H'C0 Port 1
502
P2DDR-Port 2 Data Direction Register H'C1 Port 2
502
RDR-Receive Data Register H'B5 SCI
502
P1DR-Port 1 Data Register H'C2 Port 1
503
P2DR-Port 2 Data Register H'C3 Port 2
503
P3DDR-Port 3 Data Direction Register H'C4 Port 3
503
P3DR-Port 3 Data Register H'C6 Port 3
503
P5DDR-Port 5 Data Direction Register H'C8 Port 5
504
P5DR-Port 5 Data Register H'CA Port 5
504
P6DDR-Port 6 Data Direction Register H'C9 Port 6
504
P6DR-Port 6 Data Register H'CB Port 6
505
P7DR-Port 7 Data Register H'CE Port 7
505
P8DDR-Port 8 Data Direction Register H'CD Port 8
505
P8DR-Port 8 Data Register H'CF Port 8
506
P9DDR-Port 9 Data Direction Register H'D0 Port 9
506
PADDR-Port a Data Direction Register H'D1 Port a
506
P9DR-Port 9 Data Register H'D2 Port 9
507
PADR-Port a Data Register H'D3 Port a
507
PBDDR-Port B Data Direction Register H'D4 Port B
507
P2PCR-Port 2 Input Pull-Up Control Register H'D8 Port 2
508
P5PCR-Port 5 Input Pull-Up Control Register H'DB Port 5
508
PBDR-Port B Data Register H'D6 Port B
508
ADDRA H/L-A/D Data Register a H/L H'E0, H'E1 A/D
509
ADDRB H/L-A/D Data Register B H/L H'E2, H'E3 A/D
509
ADDRC H/L-A/D Data Register C H/L H'E4, H'E5 A/D
509
ADCR-A/D Control Register H'E9 A/D
510
ADDRD H/L-A/D Data Register D H/L H'E6, H'E7 A/D
510
ADCSR-A/D Control/Status Register H'E8 A/D
511
ASTCR-Access State Control Register H'ED Bus Controller
512
WCR-Wait Control Register H'EE Bus Controller
513
MDCR-Mode Control Register H'F1 System Control
514
WCER-Wait Controller Enable Register H'EF Bus Controller
514
SYSCR-System Control Register H'F2 System Control
515
ADRCR-Address Control Register H'F3 Bus Controller
516
IER-IRQ Enable Register H'F5 Interrupt Controller
517
ISCR-IRQ Sense Control Register H'F4 Interrupt Controller
517
ISR-IRQ Status Register H'F6 Interrupt Controller
518
IPRA-Interrupt Priority Register a H'F8 Interrupt Controller
519
IPRB-Interrupt Priority Register B H'F9 Interrupt Controller
519
Appendix C I/O Port Block Diagrams
521
Port 1 Block Diagram
521
Port 2 Block Diagram
522
Port 3 Block Diagram
523
Port 5 Block Diagram
524
Port 6 Block Diagram
525
Port 7 Block Diagram
527
Port 8 Block Diagram
528
Port 9 Block Diagram
530
Port a Block Diagram
533
Port B Block Diagram
536
Appendix D Pin States
541
Port States in each Mode
541
Pin States at Reset
543
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
547
Appendix F Product Code Lineup
549
Appendix G Package Dimensions
551
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