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Table 8-3 ITU Registers (cont)
Channel Address
Name
*1
4
H'FF92
Timer control register 4
H'FF93
Timer I/O control register 4
H'FF94
Timer interrupt enable register 4
H'FF95
Timer status register 4
H'FF96
Timer counter 4 (high)
H'FF97
Timer counter 4 (low)
H'FF98
General register A4 (high)
H'FF99
General register A4 (low)
H'FF9A
General register B4 (high)
H'FF9B
General register B4 (low)
H'FF9C
Buffer register A4 (high)
H'FF9D
Buffer register A4 (low)
H'FF9E
Buffer register B4 (high)
H'FF9F
Buffer register B4 (low)
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
8.2 Register Descriptions
8.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in
channels 0 to 4.
Bit
7
—
Initial value
1
Read/Write
—
TSTR is initialized to H'E0 by a reset and in standby mode.
172
6
5
—
—
STR4
1
1
—
—
R/W
Reserved bits
Abbre-
viation
R/W
TCR4
R/W
TIOR4
R/W
TIER4
R/W
TSR4
R/(W)
TCNT4H
R/W
TCNT4L
R/W
GRA4H
R/W
GRA4L
R/W
GRB4H
R/W
GRB4L
R/W
BRA4H
R/W
BRA4L
R/W
BRB4H
R/W
BRB4L
R/W
4
3
2
STR3
STR2
0
0
0
R/W
R/W
Counter start 4 to 0
These bits start and
stop TCNT4 to TCNT0
Initial
Value
H'80
H'88
H'F8
H'F8
*2
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
1
0
STR1
STR0
0
0
R/W
R/W
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