Page 1 Hitachi Single-Chip Microcomputer H8/3672 Series H8/3672F-ZTAT HD64F3672 H8/3670F-ZTAT HD64F3670 Hardware Manual ADE-602-239 Rev. 1.0 03/20/01 Hitachi, Ltd.
Page 2 Rev. 2.0, 03/01, page of xxiv...
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 Rev. 2.0, 03/01, page of xxiv...
Page 5 Note: * F-ZTAT is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8/3672 Series in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 6 C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-246 Hitachi Debugging Interface User's Manual ADE-702-212 Hitachi Embedded Workshop User's Manual ADE-702-201 Hitachi Embedded Workshop, Hitachi Debugging Interface Tutorial ADE-702-231 F-ZTAT Microcomputer On-Board Writing Program User's Manual ADE-702-227 Application Notes: Manual Title ADE No.
Page 7: Table Of Contents
Contents Section 1 Overview........................1 Overview...........................1 Internal Block Diagram.....................2 Pin Arrangement .......................3 Pin Functions ........................5 Section 2 CPU....................7 Address Space and Memory Map ..................8 Register Configuration ...................... 9 2.2.1 General Registers .....................10 2.2.2 Program Counter (PC) .....................11 2.2.3 Condition-Code Register (CCR) ................11 Data Formats ........................
Page 8 3.4.1 External Interrupts ....................48 3.4.2 Internal Interrupts ....................49 3.4.3 Interrupt Handling Sequence ................... 49 3.4.4 Interrupt Response Time..................51 Usage Notes ........................53 3.5.1 Interrupts after Reset....................53 3.5.2 Notes on Stack Area Use ..................53 3.5.3 Notes on Rewriting Port Mode Registers ..............53 Section 4 Address Break..................55 Register Descriptions ......................
Page 9 Block Configuration......................73 Register Descriptions ......................74 7.2.1 Flash Memory Control Register 1 (FLMCR1)............75 7.2.2 Flash Memory Control Register 2 (FLMCR2)............76 7.2.3 Erase Block Register 1 (EBR1) ................76 7.2.4 Flash Memory Enable Register(FENR) ..............77 On-Board Programming Modes..................77 7.3.1 Boot Mode .......................78 7.3.2 Programming/Erasing in User Program Mode............80 Flash Memory Programming/Erasing ................
Page 10 9.5.2 Port Data Register 8(PDR8)..................105 9.5.3 Pin Functions ......................105 Port B ..........................107 9.6.1 Port Data Register B(PDRB) ................... 108 Section 10 Timer V....................109 10.1 Features..........................109 10.2 Input/Output Pins ......................110 10.3 Register Descriptions ......................111 10.3.1 Timer Counter V (TCNTV) ................. 111 10.3.2 Time Constant Registers A and B (TCORA, TCORB)........
Page 11 11.5.7 Timing of IMFA to IMFD Setting at Input Capture ..........146 11.6 Usage Notes ........................147 Section 12 Watchdog Timer ................149 12.1 Features ..........................149 12.2 Register Descriptions ......................149 12.2.1 Timer Control/Status Register WD(TCSRWD)...........150 12.2.2 Timer Counter WD(TCWD) ................151 12.2.3 Timer Mode Register WD(TMWD) ..............151 12.3 Operation...........................152 Section 13 Serial Communication Interface3 (SCI3) ........
Page 12 13.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 192 Section 14 A/D Converter .................193 14.1 Features..........................193 14.2 Input/Output Pins ......................195 14.3 Register Description......................196 14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ..........196 14.3.2 A/D Control/Status Register (ADCSR) ...............
Page 13 Register Bits........................254 Registers States in Each Operating Mode .................257 Appendix C I/O Port Block Diagrams .............. 260 I/O Port Block ........................260 Port States in Each Operating State...................275 Appendix D Product Code Lineup..............276 Appendix E Package Dimensions..............277 xiii Rev.
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Page 15 Figures of Contents Section 1 Overview Figure 1-1 Internal Block Diagram....................2 Figure 1-2 Pin Arrangement (FP-64E) ...................3 Figure 1-3 Pin Arrangement (FP-48F)....................4 Section 2 CPU Figure 2-1 Memory Map.........................8 Figure 2-2 CPU Registers .......................9 Figure 2-3 Usage of General Registers ..................10 Figure 2-4 Relationship between Stack Pointer and Stack Area...........
Page 16 Figure 5-6 Example of Incorrect Board Design................64 Section 6 Power-down Modes Figure 6-1 Mode Transition Diagram ...................69 Section 7 ROM Figure 7-1 Flash Memory Block Configuration................74 Figure 7-2 Programming/Erasing Flowchart Example in User Program Mode......80 Figure 7-3 Program/Program-Verify Flowchart ................82 Figure 7-4 Erase/Erase-Verify Flowchart ..................85 Section 9 I/O Ports Figure 9-1 Port 1 Pin Configuration .....................
Page 17 Figure 11-9 PWM Mode Example (1) ..................138 Figure 11-10 PWM Mode Example (2) ..................139 Figure 11-11 Buffer Operation Example (Output Compare) ............139 Figure 11-12 PWM Mode Example (TOB=0, TOC=0, TOD=0: initial output values are set to 0) ....... 140 Figure 11-13 PWM Mode Example (TOB=1, TOC=1,and TOD=1: initial output values are set to 1) ......
Page 18 Figure 13-14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode) ................182 Figure 13-15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ........... 184 Figure 13-16 Sample Multiprocessor Serial Transmission Flowchart........185 Figure 13-17 Sample Multiprocessor Serial Reception Flowchart (1)........
Page 19 Figure C.12 Port 7 Block Diagram (P75) ................... 271 Figure C.13 Port 7 Block Diagram (P74) ................... 272 Figure C.14 Port 8 Block Diagram (P84 to P81) ................ 273 Figure C.15 Port 8 Block Diagram (P80) ................... 274 Figure C.16 Port B Block Diagram (PB3 to PB0) ..............275 Appendix E Package Dimensions Figure E.1 FP-64E Package Dimensions ..................277 Figure E.2 FP-48F Package Dimensions ..................
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Page 21 Tables of Contents Section 1 Overview Table 1-1 Pin Functions........................5 Section 2 CPU Table 2-1 Operation Notation .......................16 Table 2-2 Data Transfer Instructions .................... 17 Table 2-3 Arithmetic Operations Instructions (1).................18 Table 2-3 Arithmetic Operations Instructions (2).................19 Table 2-4 Logic Operations Instructions ..................20 Table 2-5 Shift Instructions ......................
Page 22 Table 7-3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible .........................79 Table 7-4 Reprogram Data Computation Table................82 Table 7-5 Additional-Program Data Computation Table..............83 Table 7-6 Programming Time....................... 83 Section 10 Timer V Table 10-1 Pin Configuration .....................110 Table 10-2 Clock signals to input to TCNTV and the counting conditions........113 Section 11 Timer W Table 11-1 Timer W Functions....................124...
Page 23 Table A.2 Operation Code Map (3) .................... 242 Table A.3 Number of Cycles in Each Instruction ............... 244 Table A.4 Number of Cycles in Each Instruction ............... 245 Table A.5 Combinations of Instructions and Addressing Modes ..........250 Rev. 1.0, 03/01, page xxiii of xxiv...
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Page 25: Section 1 Overview
Section 1 Overview Overview • High-speed H8/300H central processing unit with an internal 16-bit architecture  Upward-compatible with H8/300 CPUs on an object level  Sixteen 16-bit general registers  62 basic instructions • Various peripheral functions  Timer V (8-bit timer) ...
Page 26: Internal Block Diagram
Internal Block Diagram EIOT_0 EIOT_1 System clock EIOT_2 H8/300H generator P17/ /TRGV Data bus (lower) P14/ P22/TXD P21/RXD P20/SCK3 P76/TMOV P75/TMCIV Timer W SCI3 P74/TMRIV Watchdog timer Timer V P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI P55/ A/D converter P54/ P53/ P52/ P51/ P50/ Port B...
Page 27: Pin Arrangement
Pin Arrangement 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P76/TMOV P14/ P75/TMCIV P74/TMRIV P17/ /TRGV H8/3672 Top view P55/ PB3/AN3 P54/ PB2/AN2 P53/ PB1/AN1 P52/ PB0/AN0 8 9 10 11 12 13 14 15 16 Note: Do not connect NC pins.
Page 28 36 35 34 33 32 31 30 29 28 27 26 25 P76/TMOV P14/ P75/TMCIV P74/TMRIV P17/ /TRGV H8/3672 Top view P55/ PB3/AN3 P54/ PB2/AN2 P53/ PB1/AN1 P52/ PB0/AN0 8 9 10 11 12 Figure 1-3 Pin Arrangement (FP-48F) Rev. 1.0, 03/01, page...
Page 29: Pin Functions
Pin Functions Table 1-1 Pin Functions Pin No. Type Symbol FP-64E FP-48F Functions Power Input Power supply pin. Connect this pin source pins to the system power supply. Input Ground pin. Connect all these pins to the system power supply(0V). Input Analog power supply pin for the A/D converter.
Page 30 Pin No. Type Symbol FP-64E FP-48F Functions Timer V TMOV Output This is an output pin for waveforms generated by the output compare function. TMCIV Input External event input pin. TMRIV Input Counter reset input pin. TRGV Input Counter start trigger input pin. Timer W FTCI Input...
Page 31: Section 2 Cpu
Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upword-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs ...
Page 32: Address Space And Memory Map
Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figure 2-1 show the memory map. HD64F3670 HD64F3672 (Flash memory version) (Flash memory version) H'0000 H'0000 Interrupt vector Interrupt vector H'0033 H'0033...
Page 33: Register Configuration
Register Configuration The H8/300H CPU has the internal registers shown in figure 2-2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR). General Registers (ERn) ER7 (SP) Control Registers (CR)
Page 34: General Registers
2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2-3 illustrates the usage of the general registers.
Page 35: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2-4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Page 36 Bit Name Initial Value Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception- handling sequence. undefined User Bit Can be written and read by software using the...
Page 37: Data Formats
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 38 Data Type General Data Format Register Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2-5 General Register Data Formats (2) Rev.
Page 39: Memory Data Formats
2.3.2 Memory Data Formats Figure 2-6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.
Page 40: Instruction Set
Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2-2 to 2-9 summarizes the instructions in each functional category. The notation used in tables 2-2 to 2-9 is defined below. Table 2-1 Operation Notation Symbol Description General register (destination)*...
Page 41 Table 2-2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd, Cannot be used in this LSI. MOVFPE Rs →...
Page 42 Table 2-3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.
Page 43 Table 2-3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 44 Table 2-4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 45 Table 2-6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → ( of ) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 46 Table 2-6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ ( of ) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 47 Table 2-7 Branch Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 48 Table 2-8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access.
Page 49: Basic Instruction Formats
Table 2-9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+, R4–1 →...
Page 50: Operation Field
• Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. •...
Page 51: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation 2.5.1 Addressing Modes The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. The H8/300H CPU supports the eight addressing modes listed in table 2-10. Each instruction uses a subset of these addressing modes.
Page 52 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.
Page 53: Effective Address Calculation
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
Page 54 Table 2-12 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct(Rn) Operand is general register contents. Register indirect(@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents 1, 2, or 4...
Page 55 Table 2-12 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. Program-counter relative PC contents @(d:8,PC) @(d:16,PC) Sign extension Memory indirect @@aa:8 Memory contents Legend r, rm,rn : Register field op :...
Page 56: Basic Bus Cycle
Basic Bus Cycle CPU operation is synchronized by a system clock (ø) or a subclock (ø ). The period from a rising edge of ø or ø to the next rising edge is called one state. A bus cycle consists of two states or three states.
Page 57: On-Chip Peripheral Modules
2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to appendix B, Register Addresses. Registers with 16-bit data bus width can be accessed by word size only.
Page 58: Cpu States
CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2-11, Figure 2-12 shows the state transitions.
Page 59: Usage Notes
Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs source handling complete Program halt state Program execution state SLEEP instruction executed Figure 2-12 State Transitions Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Page 60 Figure 2-13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place.
Page 61 Prior to executing BSET Input/output Input Input Output Output Output Output Output Output Pin state High level level level level level level level level PCR5 PDR5 BSET instruction executed The BSET instruction is executed for port 5. BSET @PDR5 After executing BSET Input/output Input Input...
Page 62 Prior to executing BSET MOV.B #80, The PDR5 value (H'80) is written to a work area in MOV.B R0L, @RAM0 memory (RAM0) as well as to PDR5. MOV.B R0L, @PDR5 Input/output Input Input Output Output Output Output Output Output Pin state High level level...
Page 63 Prior to executing BCLR Input/output Input Input Output Output Output Output Output Output Pin state High level level level level level level level level PCR5 PDR5 BCLR instruction executed The BCLR instruction is executed for PCR5. BCLR @PCR5 After executing BCLR Input/output Output Output...
Page 64 Prior to executing BCLR MOV.B #3F, The PCR5 value (H'3F) is written to a work area in MOV.B R0L, @RAM0 memory (RAM0) as well as to PCR5. MOV.B R0L, @PCR5 Input/output Input Input Output Output Output Output Output Output Pin state High level level...
Page 65: Section 3 Exception Handling
Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts.
Page 66 Table 3-1 Exception Sources and Vector Address Vector Exception Sources Number Vector Address Reset H'0000 to H'0001 Reserved for system use 1 to 6 H'0002 to H'000D H'000E to H'000F Trap instruction (#0) H'0010 to H'0011 (#1) H'0012 to H'0013 (#2) H'0014 to H'0015 (#3)
Page 67: Register Descriptions
Register Descriptions Interrupts are controlled by the following registers. For details on register addresses and register states during each processing, refer to appendix B, Internal I/O Register. • Interrupt Edge Select Register 1(IEGR1) • Interrupt Edge Select Register 2(IEGR2) • Interrupt Enable Register 1(IENR1) •...
Page 68: Interrupt Edge Select Register 2(Iegr2)
3.2.2 Interrupt Edge Select Register 2(IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value Description − − Reserved − − These bits are always read as 1, and cannot be modified. WPEG5 WKP5 Edge Select 0: Falling edge of WKP5(ADTRG) pin input is detected...
Page 69: Interrupt Enable Register 1(Ienr1)
3.2.3 Interrupt Enable Register 1(IENR1) IENR1 enables direct transition interrupts, and external pin interrupts. Bit Bit Name Initial Value Description IENDT Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. − − Reserved This bit is always read as 0, and cannot be modified.
Page 70: Interrupt Flag Register 1(Irr1)
3.2.4 Interrupt Flag Register 1(IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Bit Bit Name Initial Value Description IRRDT Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.
Page 71: Wakeup Interrupt Flag Register(Iwpr)
3.2.5 Wakeup Interrupt Flag Register(IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Bit Bit Name Initial Value Description − − Reserved − − These bits are always read as 1, and cannot be modified. IWPF5 WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the...
Page 72: Reset
Reset When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes.
Page 73: Internal Interrupts
WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
Page 74 Interrupt Handling Sequence 3.4.3 Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2.
Page 75: Interrupt Response Time
SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 76 Figure 3-3 Interrupt Sequence Rev. 1.0, 03/01, page 52 of 280...
Page 77: Usage Notes
Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
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Page 79: Section 4 Address Break
Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Page 80: Address Break Control Register(Abrkcr)
4.1.1 Address Break Control Register(ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value Description RTINTE RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked.
Page 81: Address Break Status Register(Abrksr)
Table 4-1 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits I/O register with 8-bit data bus...
Page 82: Break Data Registers (Bdrh, Bdrl)
4.1.4 Break Data Registers (BDRH, BDRL) BDRH, BDRL are 16-bit read/write registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8- bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission.
Page 83 When the address break is specified in the data read cycle Register setting Program • ABRKCR = H'A0 0258 • BAR = H'025A 025A 025C MOV.W @H'025A,R0 0260 Underline indicates the address 0262 to be stacked. Next instruc- instruc- instruc- instruc- instruc- instru-...
Page 84 When the interrupt acceptance is prohibited after the RTE (RTB) instruction Register setting Program Underline indicates the • ABRKCR = H'10 0258 address to be stacked. 025A Interrupt 025C MOV.W @H'025A,R0 Interrupt 039A 0260 039C 0262 039E instruc- instruc- instruc- instruc- instruc- tion...
Page 85: Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. Figure 5-1 shows a block diagram of the clock pulse generators.
Page 86: Connecting A Ceramic Oscillator
Figure 5-3 Equivalent Circuit of Crystal Oscillator Table 5-1 Crystal Oscillator Parameters Frequency(MHz) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω (max) (max) 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting a Ceramic Oscillator Figure 5-4 shows a typical method of connecting a ceramic oscillator.
Page 87: Prescalers
Prescalers 5.2.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode and subsleep mode, the system clock pulse generator stops.
Page 88: Notes On Board Design
5.3.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC and OSC pins. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5-6). Avoid Signal A Signal B...
Page 89: Section 6 Power-Down Modes
Section 6 Power-down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power dissipation is significantly reduced. The module standby mode reduces power dissipation by selectively halting on-chip module functions. •...
Page 90: System Control Register 2(Syscr2)
Bit Bit Name Initial Value Description SSBY Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: a transition is made to the sleep mode 1: a transition is made to the standby mode. For details, see table 6-2.
Page 91: Module Standby Control Register 1(Mstcr1)
Bit Bit Name Initial Value Description SMSEL Sleep Mode Selection This bit selects the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6-2. − − Reserved This bit is always read as 0, and cannot be modieied DTON Direct Transfer on Flag This bit selects the mode to transit after the execution of a...
Page 92: Module Standby Control Register 2(Mstcr2)
Bit Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified − − Reserved This bit is always read as 0 and cannot be modified MSTS3 SCI3 Module Standby SCI3 enters the standby mode when this bit is set to 1 MSTAD A/D Converter Module Standby A/D converter enters the standby mode when this bit is set...
Page 93: Mode Transitions And States Of The Lsi
Mode Transitions and States of the LSI Figure 6-1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program.
Page 94 Table 6-2 Transition Mode after the SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP Transition Mode due to DTON SSBY SMSEL Instruction Execution Interrupt Sleep mode Active mode Sleep mode Active mode Standby mode Active mode Active mode(direct transition) —...
Page 95: Sleep Mode
6.2.1 Sleep Mode In the sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, the sleep mode is cleared and interrupt exception handling starts. The sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Page 96: Operating Frequency In The Active Mode
Operating Frequency in the Active Mode Operation in the active mode is clocked at the frequency designated by the MA2, to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. Direct Transition The CPU can execute programs in active mode.The operating freuncy can be changed by making a transition directly from active mode to active mode.
Page 97: Section 7 Rom
Section 7 ROM The features of the 20-kbyte (4 kbytes of them are the EIOT control program area) flash memory built into HD64F3672 are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 98: Register Descriptions
H'0000 H'0001 H'0002 Programming unit: 128 bytes H'007F Erase unit H'0080 H'0081 H'0082 H'00FF 1kbyte H'0380 H'0381 H'0382 H'03FF H'0400 H'0401 H'0402 H'047F Programming unit: 128 bytes Erase unit H'0480 H'0481 H'0481 H'04FF 1kbyte H'0780 H'0781 H'0782 H'07FF H'0800 H'0801 H'0802 Programming unit: 128 bytes H'087F...
Page 99: Flash Memory Control Register 1 (Flmcr1)
7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit Name Initial Value Description —...
Page 100: Flash Memory Control Register 2 (Flmcr2)
7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Name Initial Value Description FLER Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing).
Page 101: Flash Memory Enable Register(Fenr)
7.2.4 Flash Memory Enable Register(FENR) FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR. Bit Bit Name Initial Value Description FLSHE Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1.
Page 102: Boot Mode
7.3.1 Boot Mode Table 7-2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing.
Page 103 Table 7-2 Boot Mode Operation Host Operation LSI Operation Item Processing Contents Processing Contents Branches to boot program at reset-start. Bit rate Continuously transmits data H'00 at · Measures low-level period of receive data H'00. adjustment specified bit rate. · Calculates bit rate and sets it in BRR of SCI3. ·...
Page 104: Programming/Erasing In User Program Mode
7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory.
Page 105: Flash Memory Programming/Erasing
Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode.
Page 106 Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program Wait 50 µs data area and reprogram data area n= 1 Set P bit in FLMCR1 m= 0 Wait (Wait time=programming time)
Page 107 Table 7-5 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming Table 7-6 Programming Time Programming In Additional (Number of Writes) Time Programming Comments 1 to 6 7 to 1,000 —...
Page 108: Erase/Erase-Verify
7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7-4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1).
Page 109 Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 µs E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ←...
Page 110: Program/Erase Protection
Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized.
Page 111: Section 8 Ram
Section 8 RAM This LSI has 2 kbyte of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Rev. 1.0, 03/01, page 87 of 280...
Page 112 Rev. 1.0, 03/01, page 88 of 280...
Page 113: Section 9 I/O Ports
Section 9 I/O Ports The series of this LSI has twenty-six general I/O ports and four input-only ports. Port 8 is a large current port, which can drive 20 mA (@V = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset.
Page 114: Port Mode Register 1(Pmr1)
9.1.1 Port Mode Register 1(PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description IRQ3 P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: P17 I/O port 1: IRQ3/TRGV input pin −...
Page 115: Port Control Register 1(Pcr1)
9.1.2 Port Control Register 1(PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description PCR17 When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the PCR16 corresponding pin an output port, while clearing the bit to 0...
Page 116: Port Pull-Up Control Register 1(Pucr1)
9.1.4 Port Pull-Up Control Register 1(PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value Description PUCR17 Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the on- PUCR16 state when these bits are set to 1, while they enter the off-...
Page 117 P15 pin Register PCR1 Bit Name PCR15 Pin Function Setting value P15 input pin P15 output pin P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function Setting value 0 P14 input pin P14 output pin IRQ0 input pin Legend X: Don't care.
Page 118: Port 2
Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9-2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses.
Page 119: Port Data Register 2(Pdr2)
9.2.2 Port Data Register 2(PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W Description − − Reserved − − These bits are always read as 1 and cannot be modified. − −...
Page 120: Port 5
P20/SCK3 pin Register SCR3 PCR2 Bit Name CKE1 CKE0 PCR20 Pin Function Setting Value P20 input pin P20 output pin SCK3 output pin SCK3 output pin SCK3 input pin Legend X:Don't care. Port 5 Port 5 is a general I/O port also functioning as an A/D trigger input pin and wakeup interrupt input pin.
Page 121: Port Mode Register 5(Pmr5)
9.3.1 Port Mode Register 5(PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description POF7 R/W P57 Pin Function Switch 0: P57 I/O port 1: NMOS open-drain output POF6 R/W P56 Pin Function Switch 0: P56 I/O port 1: NMOS open-drain output R/W P55/WKP5/ ADTRG Pin Function Switch...
Page 122: Port Control Register 5(Pcr5)
9.3.2 Port Control Register 5(PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description PCR57 When each of the port 5 pins P57 to P50 functions as an general I/O port, setting a PCR5 bit to 1 makes the PCR56 corresponding pin an output port, while clearing the bit to 0...
Page 123: Port Pull-Up Control Register 5(Pucr5)
9.3.4 Port Pull-up Control Register 5(PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description − − Reserved − − These bits are always read as 0 and cannot be modified. PUCR55 Only bits for which PCR5 is cleared are valid.
Page 124 P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 P55 input pin P55 output pin WKP5/ADTRG input pin Legend X: Don't care. P54/WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function Setting Value 0 P54 input pin P54 output pin WKP4 input pin...
Page 125: Port 7
P51/WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function Setting Value 0 P51 input pin P51 output pin WKP1 input pin Legend X: Don't care. P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting Value 0 P50 input pin P50 output pin WKP0 input pin...
Page 126: Port Control Register 7(Pcr7)
9.4.1 Port Control Register 7(PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description − − − Reserved PCR76 Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an PCR75 input port.
Page 127: Pin Functions
9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Pin Function Setting Value 0000 P76 input pin P76 output pin Other than TMOV output pin the above values...
Page 128: Port 8
Port 8 Port 8 is a general I/O port also functioning as a Timer W I/O pin. Each pin of the port 8 is shown in figure 9-5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA.
Page 129: Port Data Register 8(Pdr8)
9.5.2 Port Data Register 8(PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description − − Reserved − − − − PDR8 stores output data for port 8 pins. PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read.
Page 130 P83/FTIOC pin Register TIOR1 PCR8 Bit Name IOC2 IOC1 IOC0 PCR83 Pin Function Setting Value 0 P83 input/FTIOC input pin P83 output/FTIOC input pin FTIOC output pin FTIOC output pin P83 input/FTIOC input pin P83 output/FTIOC input pin Legend X: Don't care. P82/FTIOB pin Register TIOR0...
Page 131: Port B
P80/FTCI pin Register PCR8 Bit Name PCR80 Pin Function Setting Value 0 P80 input/FTCI input pin P80 output/FTCI input pin Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9-6.
Page 132: Port Data Register B(Pdrb)
9.6.1 Port Data Register B(PDRB) PDRB is a general input-only port data register of port B. Bit Bit Name Initial Value R/W Description − − − Reserved − − − − − − − − − − The input value of each pin is read by reading this register. −...
Page 133: Section 10 Timer V
Section 10 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input.
Page 134: Input/Output Pins
TCRV1 TCORB Trigger TRGV control Comparator Clock select TMCIV TCNTV Comparator ø TCORA Clear TCRV0 TMRIV control Interrupt request control Output TCSRV TMOV control CMIA CMIB Legend: TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0:...
Page 135: Register Descriptions
10.3 Register Descriptions Time V has the following registers. For details on register addresses and register states during each process, refer to appendix B, Internal I/O Registers. • Timer counter V(TCNTV) • Timer constant register A(TCORA) • Timer constant register B(TCORB) •...
Page 136: Timer Control Register V0(Tcrv0)
10.3.3 Timer Control Register V0(TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Bit Name Initial Value R/W Description CMIEB Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled.
Page 137 Table 10-2 Clock signals to input to TCNTV and the counting conditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 ICKS0 Description − Clock input disabled Internal clock: counts on φ/4, falling edge Internal clock: counts on φ/8, falling edge Internal clock: counts on φ/16, falling edge Internal clock: counts on φ/32, falling edge Internal clock: counts on φ/64, falling edge...
Page 138: Timer Control/Status Register V(Tcsrv)
10.3.4 Timer Control/Status Register V(TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Bit Bit Name Initial Value R/W Description CMFB Compare Match Flag B Setting condition: When the TCNTV value matches the TCORB value Clearing condition: After reading CMFB=1, cleared by writing 0 to CMFB CMFA...
Page 139: Timer Control Register V1(Tcrv1)
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 10.3.5 Timer Control Register V1(TCRV1) TCRV1 is an 8-bit read/write register that selects the edge at the TRGV pin, enables TRGV input,...
Page 140 2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0 will be set. The timing at this time is shown in figure 10-4. An interrupt request is sent to the CPU when OVIE in TCRV0 is 1. 3.
Page 141 ø TMCIV (External clock input pin) TCNTV input clock N – 1 N + 1 TCNTV Figure 10-3 Increment Timing with External Clock ø TCNTV H'FF H'00 Overflow signal Figure 10-4 OVF Set Timing ø TCNTV TCORA or TCORB Compare match signal CMFA or CMFB...
Page 142 ø Compare match A signal Timer V output Figure 10-6 TMOV Output Timing ø Compare match A signal H'00 TCNTV Figure 10-7 Clear Timing by Compare Match ø Compare match A signal Timer V output N – 1 H'00 TCNTV Figure 10-8 Clear Timing by TMRIV Input Rev.
Page 143: Timer V Application Examples
10.5 Timer V application examples 10.5.1 Pulse Output with Arbitrary Duty Cycle Figure 10-9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA.
Page 144: Pulse Output With Arbitrary Pulse Width And Delay From Trgv Input
10.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 10-10. To set up this output: 1.
Page 145: Usage Notes
10.6 Usage Notes The following types of contention or operation can occur in timer V operation. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 10-11, clearing takes precedence and the write to the counter is not carried out.
Page 146 TCORA write cycle by CPU ø TCORA address Address Internal write signal TCNTV TCORA TCORA write data Compare match signal Inhibited Figure 10-12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0 Figure 10-13 Internal Clock Switching and TCNTV Operation Rev.
Page 147: Section 11 Timer W
Section 11 Timer W Timer W has a 16-bit timer having output compare and input capture functions. Timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 11.1 Features •...
Page 148 Table 11-1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: φ, φ/2, φ/4, φ/8 Count clock External clock: FTCI General registers Period GRC (buffer GRD (buffer (output compare/input specified in register for register for capture registers) GRA in buffer GRB in buffer mode)
Page 149: Input/Output Pins
Internal clock: ø FTIOA ø/2 Clock FTIOB ø/4 selector ø/8 FTIOC Control logic External clock: FTCI FTIOD Comparator IRRTW Internal data bus Legend: TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits) TIOR:...
Page 150: Register Descriptions
11.3 Register Descriptions Timer W has the following registers. For details on register addresses and register states during each process, refer to appendix B, Internal I/O Registers. • Timer mode register W(TMRW) • Timer control register W(TCRW) • Timer interrupt enable register W(TIERW) •...
Page 151 Bit Bit Name Initial Value R/W Description Counter Start The counter operation is halted when this bit is 0; while it can be performed when this bit is 1. − − Reserved This bit is always read as 1 and cannot be modified. BUFEB Buffer Operation B Selects the GRD function.
Page 152: Timer Control Register W(Tcrw)
11.3.2 Timer Control Register W(TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer initial output levels. Bit Bit Name Initial Value Description CCLR Counter Clear The TCNT value is cleared by compare match A when this bit is 1.
Page 153: Timer Interrupt Enable Register W(Tierw)
11.3.3 Timer Interrupt Enable Register W(TIERW) TIERW controls the timer W interrupt request. Bit Bit Name Initial Value R/W Description OVIE Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. −...
Page 154 Bit Bit Name Initial Value Description IMFD Input Capture/Compare Match Flag D [Setting conditions] • TCNT=GRD when GRD functions as an output compare register • The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register [Clearing condition] Read IMFD when IMFD=1, then write 0 in IMFD...
Page 155: Timer I/O Control Register 0(Tior0)
11.3.5 Timer I/O Control Register 0(TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit Bit Name Initial Value R/W Description − − Reserved This bit is always read as 1 and cannot be modified. IOB2 I/O Control B2 Selects the GRB function.
Page 156: Timer I/O Control Register 1(Tior1)
11.3.6 Timer I/O Control Register 1(TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value Description − − Reserved This bit is always read as 1 and cannot be modified. IOD2 I/O Control D2 Selects the GRD function.
Page 157: Timer Counter (Tcnt)
11.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR of TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1.
Page 158: Operation
11.4 Operation • Normal Operation • PWM Operation 11.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running counter. When the CST bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1.
Page 159 TCNT value H'0000 Time CST bit Flag cleared by software IMFA Figure 11-3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 11-4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B.
Page 160 TCNT value H'FFFF Time H'0000 Toggle output FTIOA Toggle output FTIOB Figure 11-5 Toggle Output Example (TOA = 0, TOB = 1) Figure 11-6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B. TCNT value Counter cleared by compare match with GRA H'FFFF...
Page 161 TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time FTIOA H'1000 H'F000 H'55AA FTIOB H'AA55 Figure 11-7 Input Capture Operating Example Figure 11-8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal.
Page 162: Pwm Operation
11.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically.
Page 163 TCNT value Counter cleared by compare match A H'0000 Time FTIOB FTIOC FTIOD Figure 11-10 PWM Mode Example (2) Figure 11-11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A.
Page 164 TCNT value Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register...
Page 165 TCNT value Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register...
Page 166: Operation Timing
11.5 Operation Timing 11.5.1 TCNT Count Timing Figure 11-14 shows the TCNT count timing when the internal clock source is selected. Figure 11- 15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles;...
Page 167: Input Capture Timing
Figure 11-16 shows the output compare timing. φ TCNT input clock TCNT GRA to GRD Compare match signal FTIOA to FTIOD Figure 11-16 Output Compare Output Timing 11.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1.
Page 168: Timing Of Counter Clearing By Compare Match
11.5.4 Timing of Counter Clearing by Compare Match Figure 11-18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N+1. φ...
Page 169: Timing Of Imfa To Imfd Flag Setting At Compare Match
φ Input capture signal TCNT GRA, GRB GRC, GRD Figure 11-20 Buffer Operation Timing (Input Capture) 11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.
Page 170: Timing Of Imfa To Imfd Setting At Input Capture
11.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 11-22 shows the timing of the IMFA to IMFD flag setting at input capture.
Page 171: Usage Notes
11.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock(φ) cycles; shorter pulses will not be detected correctly. 2.
Page 172 Previous clock New clock Count clock TCNT The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 11-25 Internal Clock Switching and TCNT Operation Rev. 1.0, 03/01, page 148 of 280...
Page 173: Section 12 Watchdog Timer
Section 12 Watchdog Timer The watchdog timer(WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the WDT is shown in figure 12-1. Internal TCSRWD oscillator...
Page 174: Timer Control/Status Register Wd(Tcsrwd)
12.2.1 Timer Control/Status Register WD(TCSRWD) TCSRWD is a register that indicates TCSRWD and TCWD write control, watchdog timer operation control, and the operation status. Bit Bit Name Initial Value R/W Description B6WI Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0.
Page 175: Timer Counter Wd(Tcwd)
Bit Bit Name Initial Value R/W Description WRST Watchdog Timer Reset [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing condition] • Reset by RES pin • When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit=1 12.2.2 Timer Counter WD(TCWD)
Page 176: Operation
12.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD is required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated one base clock (φ) cycle later.
Page 177: Section 13 Serial Communication Interface3 (Sci3)
Section 13 Serial Communication Interface3 (SCI3) Serial Communication Interface3(SCI3) can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function).
Page 178 Internal clock (ø/64, ø/16, ø/4, ø) External SCK 3 clock Baud rate generator Clock Transmit/receive SCR3 control circuit Interrupt request (TEI, TXI, RXI, ERI) Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3:...
Page 179: Input/Output Pins
13.2 Input/Output Pins Table 13-1 shows the SCI3 pin configuration. Table 13-1 Pin Configuration Pin Name Abbrev. Function SCI3 clock SCK3 SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 13.3 Register Descriptions The SCI3 has the following registers for each channel.
Page 180: Receive Shift Register (Rsr)
13.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 181: Serial Mode Register (Smr)
13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source. Bit Name Initial Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length.
Page 182: Serial Control Register 3 (Scr3)
Bit Name Initial Value Description CKS1 Clock Select 0 and 1 CKS0 These bits select the clock source for the baud rate generator. 00: ø clock (n = 0) 01: ø/4 clock (n = 1) 10: ø/16 clock (n = 2) 11: ø/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.8, Bit...
Page 183 Bit Name Initial Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited.
Page 184: Serial Status Register (Ssr)
13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Name Initial Value Description TDRE Transmit Data Register Empty...
Page 185 Bit Name Initial Value Description Framing Error [Setting condition] • When a framing error occurs in reception [Clearing condition] • When 0 is written to FER after reading FER = Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] •...
Page 186: Bit Rate Register (Brr)
13.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13-2 shows the relationship between the N setting in BRR and the N setting in bits CKS1 and CKS0 of SMR in asynchronous mode.
Page 187 Table 13-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)(1) Operating Frequency ø (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 1200 0.16...
Page 188 Table 13-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency ø (MHz) 6.144 7.3728 Error Error Error Error Bit Rate (bit/s) –0.25 –0.44 0.08 –0.07 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 1200...
Page 189 Table 13-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency ø (MHz) 12.288 14.7456 Error Error Error Error Bit Rate (bit/s) 0.08 –0.17 0.70 0.03 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200...
Page 190 Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency ø (MHz) Bit Rate (bit/s) — — — — — — — — — — — — 2.5k 100k 250k 500k — — — — 2.5M — —...
Page 191: Operation In Asynchronous Mode
13.4 Operation in Asynchronous Mode Figure 13-2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Page 192: Clock
13.4.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3’s serial clock, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used.
Page 193: Sci3 Initialization
13.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 194: Data Transmission
13.4.3 Data Transmission Figure 13-5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 195 Start transmission [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the Read TDRE flag in SSR TDRE flag to 0. Checking and clearing of the TDRE flag is automatic.
Page 196: Serial Data Reception
13.4.4 Serial Data Reception Figure 13-7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 197 Table 13-5 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* Receive Data Receive Error Type Lost Overrun error Transferred to RDR Framing error Transferred to RDR Parity error Lost Overrun error + framing error Lost Overrun error + parity error Transferred to RDR Framing error + parity error Lost...
Page 198 Table 13-5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception.
Page 199 Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR3 to 0 PER = 1 Parity error processing Clear OER, PER, and FER flags in SSR to 0 Figure 13-8 Sample Serial Reception Data Flowchart (2) Rev.
Page 200: Operation In Clocked Synchronous Mode
13.5 Operation in Clocked Synchronous Mode Figure 13-9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Page 201: Serial Data Transmission
13.5.3 Serial Data Transmission Figure 13-10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 202 Start transmission Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. When data is Read TDRE flag in SSR written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission.
Page 203: Serial Data Reception (Clocked Synchronous Mode)
13.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13-12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data.
Page 204 Start reception Read the OER flag in the serial status register (SSR) to determine if there is an error. If an overrun error has occurred, Read OER flag in SSR execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR.
Page 205: Simultaneous Serial Data Transmission And Reception
13.5.5 Simultaneous Serial Data Transmission and Reception Figure 13-14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Page 206 Start transmission/reception [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the Read TDRE flag in SSR TDRE flag is automatically cleared to [2] Read SSR and check that the RDRF TDRE = 1 flag is set to 1, then read the receive data in RDR.
Page 207: Multiprocessor Communication Function
13.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Page 208 Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to...
Page 209: Multiprocessor Serial Data Transmission
13.6.1 Multiprocessor Serial Data Transmission Figure 13-16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Page 210: Multiprocessor Serial Data Reception
13.6.2 Multiprocessor Serial Data Reception Figure 13-17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 211 Set the MPIE bit in SCR to 1. Start reception Read OER and FER in SSR to check for errors. Receive error processing is performed Read MPIE bit in SCR3 in cases where a receive error occurs. Read SSR and check that the RDRF flag is Read OER and FER flags in SSR set to 1, then read the receive data in RDR and compare it with this station’s ID.
Page 212 Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear OER, and FER flags in SSR to 0 Figure 13-17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.0, 03/01, page 188 of 280...
Page 213 Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI interrupt RDRF flag RXI interrupt request operation request cleared is not generated, and MPIE cleared to 0 RDR retains its state to 0 User...
Page 214: Interrupts
13.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 13-6 shows the interrupt sources. Table 13-6 SCI3 Interrupt Requests Interrupt Requests Abbrev.
Page 215: Usage Notes
13.8 Usage Notes 13.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag.
Page 216: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
13.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 217: Section 14 A/D Converter
Section 14 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The Block diagram of the A/D converter is shown in figure 14-1. 14.1 Features • 10-bit resolution •...
Page 218 Module data bus Internal data bus 10-bit D/A ø/4 Control circuit ø/8 Comparator Sample-and- hold circuit interrupt request Legend ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 14-1 Block Diagram of A/D Converter...
Page 219: Input/Output Pins
14.2 Input/Output Pins Table 14-1 summarizes the input pins used by the A/D converter. Table 14-1 Pin Configuration Pin Name Symbol Function Analog power supply pin Input Analog block power supply and reference voltage Analog input pin 0 Input analog input pins Analog input pin 1 Input Analog input pin 2...
Page 220: Register Description
14.3 Register Description The A/D converter has the following registers. For details on register addresses, refer to appendix B, Internal I/O Register. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) •...
Page 221: A/D Control/Status Register (Adcsr)
14.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter. Bit Name Initial Value Description A/D End Flag [Setting conditions] • When A/D conversion ends in single mode • When A/D conversion ends on all the channels selected in scan mode [Clearing conditions] •...
Page 222: A/D Control Register (Adcr)
Bit Name Initial Value Description Channel Select 0 to 2 Select analog input channels. When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 to AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 14.3.3 A/D Control Register (ADCR)
Page 223: Operation
14.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed.
Page 224: Input Sampling And A/D Conversion Time
14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) has passed after the ADST bit is set to 1, then starts conversion.
Page 225: External Trigger Input Timing
Table 14-3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol A/D conversion start delay — — Input sampling time — — — — A/D conversion time CONV Note: All values represent the number of states. 14.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Page 226: A/D Conversion Precision Definitions
14.5 A/D Conversion Precision Definitions This LSI's A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14-4). •...
Page 227: Usage Notes
Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 14-5 A/D Conversion Precision Definitions (2) 14.6 Usage Notes 14.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ...
Page 228 This LSI A/D converter Sensor output equivalent circuit impedance 10 k to 5 k Sensor input Low-pass 20 pF 15 pF filter C to 0.1 F Figure 14-6 Analog Input Circuit Example Rev. 1.0, 03/01, page 204 of 280...
Page 229: Section 15 Power Supply Circuit
Section 15 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.
Page 230: When Not Using The Internal Power Supply Step-Down Circuit
15.2 When Not Using the Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and V pin, as shown in figure 15-2. The external power supply is then input directly to the internal power supply.
Page 231: Section 16 Electrical Characteristics
Section 16 Electrical Characteristics 16.1 Absolute Maximum Ratings Table 16-1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Input voltage Ports other than Port B –0.3 to V +0.3 Port B –0.3 to AV...
Page 232 Power Supply Voltage and Operating Frequency Range ø (MHz) 16.0 10.0 • AV = 3.3 V to 5.5 V • Active mode • Sleep mode (When MA2 = 0 in SYSCR2) ø (kHz) 2000 1250 78.125 • AV = 3.3 V to 5.5 V •...
Page 233: Dc Characteristics
16.2.2 DC Characteristics Table 16-2 DC Characteristics (1) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Unit Notes ×0.8 RES, Input high = 4.0 V to 5.5 —...
Page 234 Values Item Symbol Applicable Pins Test Condition Unit Notes Output P12 to P10, = 4.0 V to 5.5 – 1.0 — — high P17 to P14, voltage P22 to P20, –I = 1.5 mA P57 to P50, –I = 0.1 mA –...
Page 235 Values Item Symbol Applicable Pins Test Condition Unit Notes OSC1, RES, Input/ = 0.5 V to — — µA WKP0, WKP5, output – 0.5 V) IRQ0 to IRQ3, leakage ADTRG, TRGV, current TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3 P12 to P10, = 0.5 V to —...
Page 236 Values Item Symbol Applicable Pins Test Condition Unit Notes Sleep Sleep mode 1 — 11.5 17.0 SLEEP1 mode = 5.0 V, current = 16 MHz dissipation Sleep mode 1 — — = 3.0 V, Reference = 10 MHz value Sleep mode 2 —...
Page 237 RES Pin Mode Internal State Other Pins Oscillator Pins Active mode 1 Operates System clock oscillator: ceramic or crystal Active mode 2 Operates (ø/64) Sleep mode 1 Only timers operate Sleep mode 2 Only timers operate (ø/64) Standby mode CPU and timers System clock oscillator: both stop ceramic or crystal...
Page 238: Ac Characteristics
16.2.3 AC Characteristics Table 16-3 AC Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Test Condition Unit Figure System clock = 4.0 V to 5.5 V 2.0 —...
Page 239 Values Applicable Reference Item Symbol Pins Test Condition Unit Figure RES pin low At power-on and in — — Figure 16-2 width modes other than those below In active mode and — — sleep mode operation IRQ0 , IRQ3, Input pin high —...
Page 240 Table 16-4 Serial Interface (SCI3) Timing = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Test Condition Min Typ Max Unit Figure Input Asynchro- SCK3 —...
Page 241: A/D Converter Characteristics
16.2.4 A/D Converter Characteristics Table 16-5 A/D Converter Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Typ Max Unit Figure Analog power supply voltage Analog input voltage AN3 to...
Page 242: Watchdog Timer
Values Applicable Test Reference Item Symbol Pins Condition Typ Max Unit Figure Conversion time = 4.0 V — — (single mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — — ±3.5 Quantization error —...
Page 243: Flash Memory Characteristics (Preliminary)
16.2.6 Flash Memory Characteristics (Preliminary) Table 16-7 Flash Memory Characteristics (Preliminary) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Test Item Symbol Condition Unit Programming time (per 128 bytes)* —...
Page 244 Values Test Item Symbol Condition Unit Erase Wait time after SWE — — µs bit setting* Wait time after ESU — — µs bit setting* Wait time after E bit — setting* α Wait time after E bit clear* — —...
Page 245: Operation Timing
16.3 Operation Timing OSC1 Figure 16-1 System Clock Input Timing × 0.7 OSC1 Figure 16-2 RES Low Width Timing FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV Figure 16-3 Input Timing Rev. 1.0, 03/01, page 221 of 280...
Page 246 SCKW SCK3 Scyc Figure 16-4 SCK3 Input Clock Timing Scyc or V SCK3 or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 16-6. Figure 16-5 Serial Interface 3 Synchronous Mode Input/Output Timing Rev.
Page 247: Output Load Circuit
16.4 Output Load Circuit 2.4 kΩ LSI output pin 12 k Ω 30 pF Figure 16-6 Output Load Condition Rev. 1.0, 03/01, page 223 of 280...
Page 248 Rev. 1.0, 03/01, page 224 of 280...
Page 249: Appendix A Instruction Set
Appendix A Instruction Set Instruction List Operand Notation Symbol Description General (destination*) register General (source*) register General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand Program counter...
Page 250 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 1.0, 03/01, page 226 of 280...
Page 251: Data Transfer Instructions
Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @ERs → Rd8 MOV.B @ERs, Rd —...
Page 252 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–2 → ERd32 MOV.W Rs, @–ERd — — — Rs16 → @ERd Rs16 → @aa:16 MOV.W Rs, @aa:16 — — — Rs16 → @aa:24 MOV.W Rs, @aa:24 —...
Page 253: Arithmetic Instructions
2. Arithmetic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 — ADD.W #xx:16, Rd Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
Page 254 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — — → Rd8 Rd8 × Rs8 → Rd16 MULXU.
Page 255 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → ( EXTU EXTU.W Rd —...
Page 256 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 257 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL SHAL.W Rd — — — SHAL.L ERd — SHAR.B Rd — — SHAR SHAR.W Rd — — SHAR.L ERd —...
Page 258: Bit Manipulation Instructions
5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — BSET (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 259 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬ (#xx:3 of Rd8) → C —...
Page 260 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) Always — — — — — — — If condition is true then — — — — BRA d:16 (BT d:16) —...
Page 261 Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — — PC ← @aa:8 JMP @@aa:8 —...
Page 262 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — TRAPA CCR → @–SP → PC CCR ← @SP+ — PC ← @SP+ —...
Page 263 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — EEPMOV repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 →...
Page 264: Operation Code Map
Operation Code Map Table A.2 Operation Code Map (1) Rev. 1.0, 03/01, page 240 of 280...
Page 265 Table A.2 Operation Code Map (2) Rev. 1.0, 03/01, page 241 of 280...
Page 266 Table A.2 Operation Code Map (3) Rev. 1.0, 03/01, page 242 of 280...
Page 267: Number Of Execution States
Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write.
Page 268 Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access — Internal operation Note: * Depends on which on-chip module is accessed. See section B.1, Register Addresses. Rev.
Page 269 Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 270 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd...
Page 271 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8...
Page 272 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B @Rs, Rd MOV.B @(d:16, Rs), MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd...
Page 273 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd...
Page 274: Combinations Of Instructions And Addressing Modes
Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Addressing Mode Functions Instructions Data — — — — transfer POP, PUSH — — — — — — — — — — — — instructions MOVFPE, —...
Page 275: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Register Addresses Data Abbre- Module Access Register Name viation Bit No Address Name Width State Timer mode register W TMRW H'FF80 Timer W Timer control register W TCRW H'FF81 Timer W Timer interrupt enable register W TIERW H'FF82 Timer W...
Page 276 Data Abbre- Module Access Register Name viation Bit No Address Name Width State Transmit data register H'FFAB SCI3 Serial status register H'FFAC SCI3 Receive data register H'FFAD SCI3 A/D data register A ADDRA H'FFB0 A/D converter 8 A/D data register B ADDRB H'FFB2 A/D converter 8...
Page 277 Data Abbre- Module Access Register Name viation Bit No Address Name Width State Port data register B PDRB H'FFDD I/O port Port mode register 1 PMR1 H'FFE0 I/O port Port mode register 5 PMR5 H'FFE1 I/O port Port control register 1 PCR1 H'FFE4 I/O port...
Page 278: Register Bits
Register Bits Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TMRW — BUFEB BUFEA — PWMD PWMC PWMB Timer W TCRW CCLR CKS2 CKS1 CKS0 TIERW OVIE — —...
Page 279 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TDRE RDRF TEND MPBR MPBT SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ADDRA A/D converter — — — —...
Page 280 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PDRB — — — — I/O port PMR1 IRQ3 — — IRQ0 — — — PMR5 POF7 POF6 WKP5 WKP4 WKP3 WKP2 WKP1...
Page 281: Registers States In Each Operating Mode
Registers States in Each Operating Mode Register Name Reset Active Sleep Subsleep Standby Module − − − − TMRW Initialized Timer W − − − − TCRW Initialized − − − − TIERW Initialized − − − − TSRW Initialized −...
Page 282 Register Name Reset Active Sleep Standby Module − − ADDRA Initialized Initialized A/D converter − − ADDRB Initialized Initialized − − ADDRC Initialized Initialized − − ADDRD Initialized Initialized − − ADCSR Initialized Initialized − − ADCR Initialized Initialized − −...
Page 283 Register Name Reset Active Sleep Standby Module − − − SYSCR1 Initialized Power-down − − − SYSCR2 Initialized Power-down − − − IEGR1 Initialized Interrupts − − − IEGR2 Initialized Interrupts − − − IENR1 Initialized Interrupts − − − IRR1 Initialized Interrupts...
Page 284: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams I/O Port Block RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus PUCR Pull-up MOS TRGV Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register...
Page 285 Internal data bus PUCR Pull-up MOS Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.2 Port 1 Block Diagram (P14) Rev. 1.0, 03/01, page 261 of 280...
Page 286 Internal data bus PUCR Pull-up MOS Legend PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure C.3 Port 1 Block Diagram (P16, P15, P12, P10) Rev. 1.0, 03/01, page 262 of 280...
Page 287 Internal data bus PUCR Pull-up MOS Legend PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure C.4 Port 1 Block Diagram (P11) Rev. 1.0, 03/01, page 263 of 280...
Page 288 Internal data bus SCI3 Legend PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.5 Port 2 Block Diagram (P22) Rev. 1.0, 03/01, page 264 of 280...
Page 289 Internal data bus SCI3 Legend PDR: Port data register PCR: Port control register Figure C.6 Port 2 Block Diagram (P21) Rev. 1.0, 03/01, page 265 of 280...
Page 290 SCI3 SCKIE SCKOE Internal data bus SCKO SCKI Legend PDR: Port data register PCR: Port control register Figure C.7 Port 2 Block Diagram (P20) Rev. 1.0, 03/01, page 266 of 280...
Page 291 Internal data bus Legend PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.8 Port 5 Block Diagram (P57, P56) Rev. 1.0, 03/01, page 267 of 280...
Page 292 Internal data bus PUCR Pull-up MOS Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.9 Port 5 Block Diagram (P55) Rev. 1.0, 03/01, page 268 of 280...
Page 293 Internal data bus PUCR Pull-up MOS Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure C.10 Port 5 Block Diagram (P54 to P50) Rev. 1.0, 03/01, page 269 of 280...
Page 294 Internal data bus Timer V TMOV Legend PDR: Port data register PCR: Port control register Figure C.11 Port 7 Block Diagram (P76) Rev. 1.0, 03/01, page 270 of 280...
Page 295 Internal data bus Timer V TMCIV Legend PDR: Port data register PCR: Port control register Figure C.12 Port 7 Block Diagram (P75) Rev. 1.0, 03/01, page 271 of 280...
Page 296 Internal data bus Timer V TMRIV Legend PDR: Port data register PCR: Port control register Figure C.13 Port 7 Block Diagram (P74) Rev. 1.0, 03/01, page 272 of 280...
Page 297 Internal data bus Timer W Output control signals A to D FTIOA FTIOB FTIOC FTIOD Legend PDR: Port data register PCR: Port control register Figure C.14 Port 8 Block Diagram (P84 to P81) Rev. 1.0, 03/01, page 273 of 280...
Page 298 Internal data bus Timer W FTCI Legend PDR: Port data register PCR: Port control register Figure C.15 Port 8 Block Diagram (P80) Rev. 1.0, 03/01, page 274 of 280...
Page 299: Port States In Each Operating State
Internal data bus A/D converter CH3 to CH0 Figure C.16 Port B Block Diagram (PB3 to PB0) Port States in Each Operating State Port Reset Active Sleep Subsleep Standby P17 to P14, High impedance Functioning Retained Retained High impedance* P12 to P10 P22 to P20 High impedance Functioning Retained...
Page 300: Appendix D Product Code Lineup
Appendix D Product Code Lineup Package (Hitachi Package Code) LQFP-64 LQFP-48 Product Type (FP-64E) (FP-48F) H8/3672 Flash memory version Standard product HD64F3672FP HD64F3672FX H8/3670 Flash memory version Standard product HD64F3670FP HD64F3670FX Rev. 1.0, 03/01, page 276 of 280...
Page 301: Appendix E Package Dimensions
Appendix E Package Dimensions The package dimensions that are shows in the Hitachi Semiconductor Packages Data Book has priority. Unit: mm 12.0 ± 0.2 *0.22 ± 0.05 0.08 0.20 ± 0.04 1.25 0 – 8 0.5 ± 0.2 0.10 Hitachi Code FP-64E –...
Page 302 Unit: mm 12.0 ± 0.2 1.425 *0.32 ± 0.05 0.13 0.30 ± 0.04 0 – 8 0.50 ± 0.1 0.10 Hitachi Code FP-48F JEDEC — EIAJ — *Dimension including the plating thickness Base material dimension Mass (reference value) 0.4 g Figure E.2 FP-48F Package Dimensions...
Page 303 Index A/D Converter ............... 193 programming units ..........73 A/D conversion time..........200 Programming/Erasing in User Program Mode..80 external trigger input ..........201 Software Protection..........86 sample-and-hold circuit ........200 General Registers............10 Scan Mode............199 I/O Ports................89 Single Mode............199 I/O Port Block Diagrams........260 Absolute Maximum Ratings ..........
Page 304 ABRKSR........57, 252, 255, 258 RDR ..........156, 252, 255, 257 ADCR .......... 198, 252, 255, 258 RSR..............156 ADCSR ........197, 252, 255, 258 SCR3..........158, 251, 254, 257 ADDRA ........196, 252, 255, 258 SMR ..........157, 251, 254, 257 ADDRB ........196, 252, 255, 258 SSR..........160, 252, 255, 257 ADDRC........
Page 305 Publication Date: 1st Edition, March 2001 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.

This manual is also suitable for:

H8/3672f-ztat hd64f3672 H8/3670f-ztat hd64f3670

Hitachi H8/3672 Series Hardware Manual

Section 2 CPU

Section 3 Exception Handling

Section 4 Address Break

Section 5 Clock Pulse Generators

Section 6 Power-Down Modes

Section 7 ROM

Section 8 RAM

Section 9 I/O Ports

Section 10 Timer V

Section 11 Timer W

Section 12 Watchdog Timer

Section 13 Serial Communication Interface3 (SCI3)

Section 14 A/D Converter

Section 15 Power Supply Circuit

Section 16 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Registers

Appendix C I/O Port Block Diagrams

Appendix D Product Code Lineup

Appendix E Package Dimensions

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