Table of Contents
5.2
Prescalers
5.2.1
Prescaler S
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode and subsleep mode, the system clock pulse generator stops. Prescaler S also stops
and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be
set separately for each on-chip peripheral function.
In active mode the clock input to prescaler S is determined by the division factor designated by
MA2 and MA0 in SYSCR2.
5.3
Usage Notes
5.3.1
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.
Rev. 1.0, 03/01, page 63 of 280
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