Operation In Asynchronous Mode - Hitachi H8/3672 Series Hardware Manual

Single-chip microcomputer
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13.4

Operation in Asynchronous Mode

Figure 13-2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units,
enabling full-duplex. Both the transmitter and the receiver also have a double-buffered structure,
so data can be read or written during transmission or reception, enabling continuous data transfer.
1
LSB
Serial
0
data
Start
bit
1 bit
Figure 13-2 Data Format in Asynchronous Communication
D0
D1
D2
D3
Transmit/receive data
7 or 8 bits
One unit of transfer data (character or frame)
MSB
D4
D5
D6
D7
Parity
bit
1 bit,
or none
Idle state
(mark state)
1
0/1
1
1
Stop bit
1 or
2 bits
Rev. 1.0, 03/01, page 167 of 280
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