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Interrupt accepted
Interrupt level
decision and wait
Instruction
Internal
for end of instruction
prefetch
processing
ø
Interrupt
request
signal
A
to A
(1)
(3)
19
0
Internal
read signal
Internal
High
write signal
(2)
(4)
On-chip
data
(1)
Instruction prefetch address (not executed;
return address, same as PC contents)
(2), (4)
Instruction code (not executed)
(3)
Instruction prefetch address (not executed)
(5)
SP – 2
(7)
SP – 4
Note: Mode 1, with program code and stack in on-chip memory area.
Internal
Stack
Vector fetch
processing
(5)
(7)
(9)
(11)
(6)
(8)
(10)
(12)
(6), (8)
PC and CCR saved to stack
(9), (11)
Vector address
(10), (12)
Starting address of interrupt service routine (contents of
vector address)
(13)
Starting address of interrupt service routine; (13) = (10), (12)
(14)
First instruction of interrupt service routine
Prefetch of
interrupt
service routine
instruction
(13)
(14)
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