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Bit 4—Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
Description
0
Refresh cycles disabled
1
DRAM refresh cycles enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (Tp) is to
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit
does not affect the self-refresh function.
Bit 2
TPC
Description
0
1-state precharge cycle inserted
1
2-state precharge cycle inserted
Bit 1—RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between T
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW
Description
0
Wait state (Trw) insertion disabled
1
One wait state (Trw) inserted
Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (T
RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW
Description
0
Wait state (T
1
One wait state (T
) insertion disabled
RW
) inserted
RW
(Initial value)
(Initial value)
and T
in DRAM
r
c1
(Initial value)
) insertion for CAS-before-
RW
(Initial value)
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