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When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only
UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0,
PB5 can be used as an input/output port.
Note that RAS down mode cannot be used when a device other than DRAM is connected to
external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is
always inserted when an external access to other than DRAM space occurs after a DRAM space
access. For details, see section 6.9, Idle Cycle.
CSEL Settings and UCAS and LCAS Output Pins
Table 6.8
UCAS
CSEL
0
PB4
HWR
1
Figure 6.19 shows the control timing.
A
CSn (RAS)
PB4(UCAS)
Byte control
PB5(LCAS)
Note: n = 2 to 5
Figure 6.19 Control Timing (Upper-Byte Write Access When CSEL = 0)
T
p
φ
to A
23
0
RD(WE)
LCAS
PB5
LWR
Tr
T
c1
Row
Column
T
c2
151
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