Table of Contents
11.1 Overview............................................................................................................................ 383
11.1.1 Features ................................................................................................................. 383
11.1.2 Block Diagram...................................................................................................... 384
11.1.3 Pin Configuration.................................................................................................. 385
11.1.4 Register Configuration.......................................................................................... 386
11.2 Register Descriptions ......................................................................................................... 387
11.2.1 Port A Data Direction Register (PADDR)............................................................ 387
11.2.2 Port A Data Register (PADR)............................................................................... 387
11.2.3 Port B Data Direction Register (PBDDR) ............................................................ 388
11.2.4 Port B Data Register (PBDR) ............................................................................... 388
11.2.5 Next Data Register A (NDRA) ............................................................................. 389
11.2.6 Next Data Register B (NDRB) ............................................................................. 391
11.2.7 Next Data Enable Register A (NDERA) .............................................................. 393
11.2.8 Next Data Enable Register B (NDERB)............................................................... 394
11.2.9 TPC Output Control Register (TPCR).................................................................. 395
11.2.10 TPC Output Mode Register (TPMR).................................................................... 398
11.3 Operation............................................................................................................................ 400
11.3.1 Overview............................................................................................................... 400
11.3.2 Output Timing ...................................................................................................... 401
11.3.3 Normal TPC Output.............................................................................................. 402
11.3.4 Non-Overlapping TPC Output.............................................................................. 404
11.3.5 TPC Output Triggering by Input Capture............................................................. 406
11.4 Usage Notes ....................................................................................................................... 407
11.4.1 Operation of TPC Output Pins.............................................................................. 407
11.4.2 Note on Non-Overlapping Output ........................................................................ 407
12.1 Overview............................................................................................................................ 409
12.1.1 Features ................................................................................................................. 409
12.1.2 Block Diagram...................................................................................................... 410
12.1.3 Pin Configuration.................................................................................................. 410
12.1.4 Register Configuration.......................................................................................... 411
12.2 Register Descriptions ......................................................................................................... 412
12.2.1 Timer Counter (TCNT)......................................................................................... 412
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 413
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 415
12.2.4 Notes on Register Access...................................................................................... 417
12.3 Operation............................................................................................................................ 419
12.3.1 Watchdog Timer Operation .................................................................................. 419
12.3.2 Interval Timer Operation ...................................................................................... 420
12.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 421
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 422
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.................................. 383
Table of Contents
