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7.2
Register Descriptions (1) (Short Address Mode)
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 7.4.
Table 7.4
Selection of Short and Full Address Modes
Bit 2
Channel
DTS2A
0
1
Other than above
1
1
Other than above
7.2.1
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1.
Bit
31
30
29
28
27
Initial value
1
1
1
1
Read/Write
—
—
—
—
—
MARR
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0) or by a conversion-end interrupt from the A/D
converter, and as a source address register otherwise.
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
188
Bit 1
DTS1A
Description
1
DMAC channel 0 operates as one channel in full address mode
DMAC channels 0A and 0B operate as two independent channels
in short address mode
1
DMAC channel 1 operates as one channel in full address mode
DMAC channels 1A and 1B operate as two independent channels
in short address mode
26
25
24
23
22
21
20
1
1
1
1
—
—
—
R/W
R/W
R/W
R/W
MARE
Source or destination address
19
18
17
16
15
14
13
12
Undetermined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MARH
11
10
9
8
7
6
5
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MARL
3
2
1
0
R/W
R/W
R/W
R/W
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