Table of Contents
PB
5
WPBD:
Write to PBDDR
WPB:
Write to port B
RPB:
Read port B
Figure C.7 (d) Port B Block Diagram (Pin PB
Reset
R
Q
D
PB
DDR
5
C
WPBD
Reset
R
Q
D
PB
DR
5
C
WPB
RPB
SCI
Clock input
enable
TPC
TPC output enable
Next data
Output trigger
Bus controller
CAS output enable
CAS output
SCI
Clock output enable
Clock output
Clock input
)
5
751
Table of Contents
