Hitachi HD6413006 Manuals

Manuals and User Guides for Hitachi HD6413006. We have 1 Hitachi HD6413006 manual available for free PDF download: Hardware Manual

Hitachi HD6413006 Hardware Manual (787 pages)

Brand: Hitachi | Category: Computer Hardware | Size: 2.76 MB

Table of Contents
8
Section 1 Overview
21
Overview
21
Internal Block Diagram
25
Pin Description
26
Pin Arrangement
26
Pin Functions
28
1.3.3 Pin Assignments in each Mode
33
Section 2 CPU
37
Overview
37
Features
37
Differences from H8/300 CPU
38
CPU Operating Modes
39
Address Space
40
Register Configuration
41
Overview
41
General Registers
42
Control Registers
43
Initial CPU Register Values
44
Data Formats
45
General Register Data Formats
45
Memory Data Formats
46
Instruction Set
48
Instruction Set Overview
48
Instructions and Addressing Modes
49
Tables of Instructions Classified by Function
50
2.6.4 Basic Instruction Formats
59
Notes on Use of Bit Manipulation Instructions
60
Addressing Modes and Effective Address Calculation
62
Addressing Modes
62
Effective Address Calculation
64
Processing States
68
Overview
68
Program Execution State
69
Exception-Handling State
69
Exception-Handling Sequences
71
Bus-Released State
72
Reset State
72
Power-Down State
72
Basic Operational Timing
73
Overview
73
On-Chip Memory Access Timing
73
On-Chip Supporting Module Access Timing
74
Access to External Address Space
75
Section 3 MCU Operating Modes
76
Overview
76
Operating Mode Selection
76
Register Configration
77
Mode Control Register (MDCR)
77
System Control Register (SYSCR)
78
Operating Mode Descriptions
81
Mode 1
81
Mode 2
81
Mode 3
81
Mode 4
81
Pin Functions in each Operating Mode
82
Memory Map in each Operating Mode
82
Note on Reserved Areas
82
Section 4 Exception Handling
85
Overview
85
Exception Handling Types and Priority
85
Exception Handling Operation
85
Exception Vector Table
86
Reset
88
4.2.1 Overview
88
4.2.2 Reset Sequence
88
Interrupts after Reset
90
Interrupts
91
Trap Instruction
91
Stack Status after Exception Handling
92
Notes on Stack Usage
92
Section 5 Interrupt Controller
94
Overview
94
Features
94
Block Diagram
95
Pin Configuration
96
Register Configuration
96
Register Descriptions
97
System Control Register (SYSCR)
97
Interrupt Priority Registers a and B (IPRA, IPRB)
98
IRQ Status Register (ISR)
105
IRQ Enable Register (IER)
106
IRQ Sense Control Register (ISCR)
107
Interrupt Sources
108
External Interrupts
108
Internal Interrupts
109
Interrupt Vector Table
109
Interrupt Operation
113
Interrupt Handling Process
113
Interrupt Sequence
118
Interrupt Response Time
119
Usage Notes
120
Contention between Interrupt and Interrupt-Disabling Instruction
120
Instructions that Inhibit Interrupts
121
Interrupts During EEPMOV Instruction Execution
121
Section 6 Bus Controller
122
Overview
122
Features
122
Block Diagram
124
Pin Configuration
125
Register Configuration
126
Register Descriptions
127
Bus Width Control Register (ABWCR)
127
Access State Control Register (ASTCR)
128
Wait Control Registers H and L (WCRH, WCRL)
128
Bus Release Control Register (BRCR)
132
Bus Control Register (BCR)
133
Chip Select Control Register (CSCR)
135
DRAM Control Register a (DRCRA)
136
DRAM Control Register B (DRCRB)
138
Refresh Timer Control/Status Register (RTMCSR)
141
Refresh Timer Counter (RTCNT)
142
Refresh Time Constant Register (RTCOR)
143
Operation
144
Area Division
144
Bus Specifications
146
Memory Interfaces
147
Chip Select Signals
147
Basic Bus Interface
149
Overview
149
Data Size and Data Alignment
149
Valid Strobes
150
Memory Areas
151
Basic Bus Control Signal Timing
153
Wait Control
160
DRAM Interface
162
Overview
162
DRAM Space and RAS Output Pin Settings
162
Address Multiplexing
163
Data Bus
163
Pins Used for DRAM Interface
163
Basic Timing
164
Precharge State Control
165
Wait Control
166
Byte Access Control and cas Output Pin
167
Burst Operation
169
Refresh Control
174
Examples of Use
177
Usage Notes
181
Interval Timer
184
Operation
184
Interrupt Sources
189
Burst ROM Interface
189
Overview
189
Basic Timing
189
Wait Control
190
Idle Cycle
191
Operation
192
Pin States in Idle Cycle
194
Bus Arbiter
195
Operation
195
Register and Pin Input Timing
198
Register Write Timing
198
BREQ Pin Input Timing
199
Section 7 DMA Controller
200
Overview
200
Features
200
Block Diagram
201
Functional Overview
202
Pin Configuration
203
Register Configuration
203
Register Descriptions (1) (Short Address Mode)
205
Memory Address Registers (MAR)
205
I/O Address Registers (IOAR)
206
Execute Transfer Count Registers (ETCR)
206
Data Transfer Control Registers (DTCR)
208
Register Descriptions (2) (Full Address Mode)
211
Memory Address Registers (MAR)
211
I/O Address Registers (IOAR)
211
Execute Transfer Count Registers (ETCR)
212
Data Transfer Control Registers (DTCR)
214
Operation
220
Overview
220
I/O Mode
222
Idle Mode
224
Repeat Mode
227
Normal Mode
231
Block Transfer Mode
238
DMAC Activation
239
DMAC Bus Cycle
241
Multiple-Channel Operation
247
External Bus Requests, DRAM Interface, and DMAC
248
NMI Interrupts and DMAC
249
Aborting a DMAC Transfer
250
Exiting Full Address Mode
251
DMAC States in Reset State, Standby Modes, and Sleep Mode
252
Interrupts
253
Usage Notes
254
Note on Word Data Transfer
254
DMAC Self-Access
254
Longword Access to Memory Address Registers
254
Note on Full Address Mode Setup
254
Note on Activating DMAC by Internal Interrupts
255
NMI Interrupts and Block Transfer Mode
256
Memory and I/O Address Register Values
256
Bus Cycle When Transfer Is Aborted
257
Transfer Requests by A/D Converter
257
Section 8 I/O Ports
258
Overview
258
Overview
261
Port 7
269
Overview
270
Port 8
270
Register Configuration
271
Port 9
275
Register Configuration
275
Port a
278
Overview
278
Register Configuration
280
Port B
289
Overview
289
Register Configuration
290
Section 9 16-Bit Timer
295
Overview
295
Features
295
Block Diagrams
298
Pin Configuration
301
Register Configuration
302
Register Descriptions
304
Timer Start Register (TSTR)
304
Timer Synchro Register (TSNC)
305
Timer Mode Register (TMDR)
306
Timer Interrupt Status Register a (TISRA)
308
Timer Interrupt Status Register B (TISRB)
311
Timer Interrupt Status Register C (TISRC)
314
Timer Counters (16TCNT)
316
General Registers (GRA, GRB)
317
Timer Control Registers (16TCR)
318
Timer I/O Control Register (TIOR)
320
Timer Output Level Setting Register C (TOLR)
322
CPU Interface
325
16-Bit Accessible Registers
325
8-Bit Accessible Registers
327
Operation
328
Overview
328
Basic Functions
328
Synchronization
338
PWM Mode
340
Phase Counting Mode
344
Setting Initial Value of 16-Bit Timer Output
346
Interrupts
347
Setting of Status Flags
347
Timing of Clearing of Status Flags
349
Interrupt Sources and DMA Controller Activation
350
Usage Notes
351
Section 10 8-Bit Timers
363
Overview
363
Features
363
Block Diagram
365
Pin Configuration
366
Register Configuration
367
Register Descriptions
368
Timer Counters (8TCNT)
368
Time Constant Registers a (TCORA)
369
Time Constant Registers B (TCORB)
370
Timer Control Register (8TCR)
370
Timer Control/Status Registers (8TCSR)
373
CPU Interface
377
8-Bit Registers
377
Operation
379
8TCNT Count Timing
379
Compare Match Timing
380
Input Capture Signal Timing
381
Timing of Status Flag Setting
382
Operation with Cascaded Connection
383
Input Capture Setting
385
Interrupt
387
Interrupt Source
387
A/D Converter Activation
388
8-Bit Timer Application Example
388
Usage Notes
389
Contention between 8TCNT Write and Clear
389
Contention between 8TCNT Write and Increment
390
Contention between TCOR Write and Compare Match
391
Contention between TCOR Read and Input Capture
392
Contention between Counter Clearing by Input Capture and Counter Increment
393
Contention between TCOR Write and Input Capture
394
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)
395
Contention between Compare Matches a and B
396
8TCNT Operation at Internal Clock Source Switchover
396
Section 11 Programmable Timing Pattern Controller (TPC)
399
Overview
399
Features
399
Block Diagram
400
Pin Configuration
401
Register Configuration
402
Register Descriptions
403
Port a Data Direction Register (PADDR)
403
Port a Data Register (PADR)
403
Port B Data Direction Register (PBDDR)
404
Port B Data Register (PBDR)
404
Next Data Register a (NDRA)
405
Next Data Register B (NDRB)
407
Next Data Enable Register a (NDERA)
409
Next Data Enable Register B (NDERB)
410
TPC Output Control Register (TPCR)
411
TPC Output Mode Register (TPMR)
414
Operation
416
Overview
416
Output Timing
417
Normal TPC Output
418
Non-Overlapping TPC Output
420
TPC Output Triggering by Input Capture
422
Usage Notes
423
Operation of TPC Output Pins
423
Note on Non-Overlapping Output
423
Section 12 Watchdog Timer
425
Overview
425
Features
425
Block Diagram
426
Pin Configuration
426
Register Configuration
427
Register Descriptions
428
Timer Counter (TCNT)
428
Timer Control/Status Register (TCSR)
429
Reset Control/Status Register (RSTCSR)
431
Notes on Register Access
433
Operation
435
Watchdog Timer Operation
435
Interval Timer Operation
436
Timing of Setting of Overflow Flag (OVF)
437
Timing of Setting of Watchdog Timer Reset Bit (WRST)
438
Interrupts
439
Usage Notes
439
Section 13 Serial Communication Interface
440
Overview
440
Features
440
Block Diagram
442
Pin Configuration
443
Register Configuration
444
Register Descriptions
445
Receive Shift Register (RSR)
445
Receive Data Register (RDR)
445
Transmit Shift Register (TSR)
446
Transmit Data Register (TDR)
446
Serial Mode Register (SMR)
447
Serial Control Register (SCR)
451
Serial Status Register (SSR)
455
Bit Rate Register (BRR)
461
Operation
470
Overview
470
Operation in Asynchronous Mode
472
Multiprocessor Communication
482
Synchronous Operation
488
SCI Interrupts
497
Usage Notes
498
Notes on Use of SCI
498
Section 14 Smart Card Interface
503
Overview
503
Features
503
Block Diagram
504
Pin Configuration
504
Register Configuration
505
Register Descriptions
506
Smart Card Mode Register (SCMR)
506
Serial Status Register (SSR)
508
Serial Mode Register (SMR)
510
Serial Control Register (SCR)
510
Operation
511
Overview
511
Pin Connections
512
Data Format
512
Register Settings
514
Clock
516
Transmitting and Receiving Data
518
Usage Notes
526
Section 15 A/D Converter
529
Overview
529
Features
529
Block Diagram
530
Pin Configuration
531
Register Configuration
532
Register Descriptions
533
A/D Data Registers a to D (ADDRA to ADDRD)
533
A/D Control/Status Register (ADCSR)
534
A/D Control Register (ADCR)
537
CPU Interface
538
Operation
539
Single Mode (SCAN = 0)
539
Scan Mode (SCAN = 1)
541
Input Sampling and A/D Conversion Time
543
External Trigger Input Timing
544
Interrupts
545
Usage Notes
545
Section 16 D/A Converter
550
Overview
550
Features
550
Block Diagram
550
Pin Configuration
551
Register Configuration
551
Register Descriptions
552
D/A Data Registers 0 and 1 (DADR0/1)
552
D/A Control Register (DACR)
552
D/A Standby Control Register (DASTCR)
554
Operation
555
D/A Output Control
557
Section 17 RAM
558
Overview
558
Block Diagram
558
Register Configuration
559
System Control Register (SYSCR)
560
Operation
561
Section 18 Clock Pulse Generator
562
Overview
562
Block Diagram
562
Oscillator Circuit
563
Connecting a Crystal Resonator
563
External Clock Input
565
Duty Adjustment Circuit
568
Prescalers
568
Frequency Divider
568
Register Configuration
568
Division Control Register (DIVCR)
568
Usage Notes
569
Section 19 Power-Down State
570
Overview
570
Register Configuration
572
System Control Register (SYSCR)
572
Module Standby Control Registerh (MSTCRH)
574
Module Standby Control Register L (MSTCRL)
575
Sleep Mode
577
Transition to Sleep Mode
577
Exit from Sleep Mode
577
Software Standby Mode
578
Transition to Software Standby Mode
578
Exit from Software Standby Mode
578
Selection of Waiting Time for Exit from Software Standby Mode
579
Sample Application of Software Standby Mode
580
Note
580
Hardware Standby Mode
581
Transition to Hardware Standby Mode
581
Exit from Hardware Standby Mode
581
Timing for Hardware Standby Mode
581
Module Standby Function
582
Module Standby Timing
582
Read/Write in Module Standby
582
Usage Notes
582
System Clock Output Disabling Function
583
Section 20 Electrical Characteristics
584
Absolute Maximum Ratings
584
Electrical Characteristics
585
DC Characteristics
585
AC Characteristics
595
A/D Conversion Characteristics
603
D/A Conversion Characteristics
605
Operational Timing
606
Clock Timing
606
Control Signal Timing
607
Bus Timing
609
DRAM Interface Bus Timing
615
TPC and I/O Port Timing
618
Timer Input/Output Timing
619
SCI Input/Output Timing
620
DMAC Timing
621
Appendix A Instruction Set
622
Instruction List
622
Operation Code Map
637
Number of States Required for Execution
640
Appendix B Internal I/O Registers
649
Addresses
649
Functions
658

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Hitachi HD6413006 Hardware Manual (787 pages)

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