Table of Contents
External space
access
DRAM access
DRAM access
T
Tr
T
T
T
T
T
T
p
c1
c2
1
2
c1
c2
φ
A
to A
23
0
AS
CSn (RAS)
PB4/PB5
(UCAS/LCAS)
D
to D
15
0
Note: n = 2 to 5
Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0)
When RAS down mode is selected, the conditions for an asserted RASn signal to return to the
high level are as shown below. The timing in these cases is shown in figure 6.22.
When DRAM space with a different row address is accessed
Immediately before a CAS-before-RAS refresh cycle
When the BE bit or RDM bit is cleared to 0 in DRCRA
Immediately before release of the external bus
154
Table of Contents
