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Bus cycle A
(DRAM access cycle)
T
p
φ
Address bus
HWR/LWR
(UCAS/LCAS)
CSn
(a) Idle cycle not inserted
Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
Figure 6.44 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.45.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do
not change simultaneously, or when it does not matter if they do.
176
Bus cycle B
T
T
T
T
T
r
c1
c2
1
2
Simultaneous change of
HWR/LWR and CSn
External read
T
1
φ
Address bus
RD
UCAS/LCAS
Address bus
(DRAM access cycle) Bus cycle B
φ
Address bus
HWR/LWR
(UCAS/LCAS)
CSn
DRAM space read
T
T
T
T
2
3
p
r
Bus cycle A
T
T
T
T
T
p
r
c1
c2
i
(b) Idle cycle inserted
T
T
c1
c2
T
T
1
2
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