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■ 2-Cycle Transfer (External -> I/O)
Figure 10-9
"Timing Chart for 2-Cycle Transfer (External -> I/O" shows the operation timing chart for (TYP3-
0=0000
, AWR=0008
B
H
Figure 10-9
"Timing Chart for 2-Cycle Transfer (External -> I/O" shows a case in which a wait is not set for
memory and I/O.
MCLK
A[31:0]
AS
CSn
RD
CSn
WRn
D[31:0]
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic
mode
DEOPn
DREQn
•
The bus is accessed in the same way as an interface when the DMAC transfer is not performed.
•
In basic mode, DACKn/DEOPn is output in both transfer source bus access and transfer destination bus
access.
10.7 2-Cycle Transfer (I/O -> External)
This section explains 2-cycle transfer (I/O -> external) operation.
, IOWR=00
).
H
Figure 10-9 Timing Chart for 2-Cycle Transfer (External -> I/O)
memory address
idle
I/O address
Chapter 31 External Bus
10.DMA Access Operation
603
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