Page 1 FUJITSU SEMICONDUCTOR CONTROLLER MANUAL - PRELIMINARY - CM71-xxxxx-1E 32-BIT MICROCONTROLLER MB91460 Series User’s Manual Version 1.00 2006-10-22 FR60...
Page 2 FUJITSU LIMITED...
Page 3 FR60 32-BIT MICROCONTROLLER MB91460 Series User’s Manual...
Page 4 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 5: Table Of Contents
Chapter 1 Introduction ... 1 How to Handle the Device ... 1 Instruction for Users... 3 Caution: debug-related matters ... 6 How to Use This Document ... 7 Chapter 2 MB91460 Rev.A/Rev.B Overview ... 11 Overview... 11 Features... 11 MB91460 Series Product Lineup ... 19 Block Diagram ...
Page 6 EIT Vector Table... 122 Multiple EIT Processing ... 123 Operation ... 125 Caution ... 128 Chapter 7 Branch Instruction ... 129 Branch Instruction with Delay Slot ... 129 Operation of Branch Instruction with Delay Slot ... 129 Actual Example (with Delay Slot)... 130 Restrictions on Branch Instruction with Delay Slot ...
Page 7 Explanations of Registers ... 169 Chapter 12 Instruction Cache... 179 General description... 179 Main body structure ... 179 Operating mode conditions... 185 Cacheable areas in the instruction cache... 186 Settings for handling the I-Cache ... 186 Chapter 13 Clock Control ... 189 Overview...
Page 8 Configuration ... 250 Registers... 251 Operation ... 253 Settings... 259 Q&A ... 260 Caution ... 262 Chapter 19 Timebase Timer... 263 Overview... 263 Features... 263 Configuration ... 264 Register ... 265 Operation ... 267 Setting... 268 Q & A ... 269 Caution ...
Page 9 Register ... 301 Operation ... 303 Setting... 306 Q & A ... 307 Caution ... 309 Chapter 24 Interrupt Control ... 311 Overview... 311 Features... 311 Configuration ... 312 Registers... 313 Operation ... 318 Setting... 319 Q & A ... 319 Caution ...
Page 10 Register ... 389 Operation ... 391 Setting... 393 Q & A ... 394 Caution ... 395 Chapter 29 MPU / EDSU ... 397 Overview... 397 Features... 398 Break Functions... 399 Registers... 407 Quick Reference ... 429 Chapter 30 I/O Ports ... 431 I/O Ports Functions ...
Page 11 Chapter 34 CAN Controller ... 691 Overview... 691 Register Description ... 692 Functional Description ... 720 CAN Application... 724 Chapter 35 Free-Run Timer ... 733 Overview... 733 Features... 733 Configuration Diagram... 734 Registers... 735 Operation ... 739 Setting... 741 Q & A ... 742 Caution ...
Page 12 Features... 795 Configuration ... 797 Registers... 799 Operation ... 808 Setting... 811 Q & A ... 813 Caution ... 821 Chapter 40 Pulse Frequency Modulator... 823 PFM Overview ... 823 Reload Counter Registers ... 826 Reload Counter Operation... 830 PFM Operation and Setting ... 833 Chapter 41 Up/Down Counter...
Page 13 Registers... 911 Operation ... 913 Setting... 914 Q & A ... 915 Caution ... 916 Chapter 46 Alarm Comparator ... 917 Overview... 917 Block Diagram ... 917 Alarm Comparator Control/Status Register (ACSR)... 918 Operation Modes ... 919 Chapter 47 LCD Controller ... 921 Overview...
Page 14 Application Note... 973 Chapter 51 Low Voltage Reset/Interrupt ... 975 Overview... 975 Features... 975 Registers... 976 Chapter 52 Regulator Control ... 979 Overview... 979 Features... 979 Registers... 980 Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM ... 983 Overview... 983 Check for Boot Conditions ... 983 Registers modified by Boot ROM ...
Page 17: Chapter 1 Introduction
Chapter 1 Introduction 1. How to Handle the Device ■ Device Handling Instructions This chapter describes latch-up prevention and pin termination. ● To set latch-up prevention Latch up may occur on CMOS ICs when the applied voltage for input terminals or output terminals is higher than V or lower than V , or a voltage higher than the maximum rating voltage is applied between V not to apply a voltage higher than the maximum rating voltage since latch up may surge electric current and result in...
Page 18 Chapter 1 Introduction 1.How to Handle the Device ● Caution: during the PLL clock operation Even if oscillator is disconnected or input is stopped while selecting PLL clock, self-excited oscillation circuit in the PLL may continue running at self-running frequency. This self-running operation is not covered by guarantee. ●...
Page 19: Instruction For Users
2. Instruction for Users ■ Clock Controls By inputting “L” to INIT, ensure clock oscillation stabilization time. ■ Switching of dual-purpose port Use PFR (Port function register) to switch between PORT and dual-purpose port. ■ Low-power-consumption mode • For standby mode, enable synchronous standby (TBCR.SYNCS=“1”) and then use the following sequences. (LDI #value_of_standby, R0 (LDI...
Page 20 Chapter 1 Introduction 2.Instruction for Users ■ Caution: PS register Because some commands previously proceed PS register, interrupt processing routine may be broken during the use of debugger or displayed data on PS flag may be updated due to the following excecptional operations ((1) and (2)).
Page 21 ■ Caution: writing to registers which include a status flag Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function, note that you should not clear status flag unintentionally. That is, take care not to clear the flag for status bit and make control bit to be the expected value during the writing.
Page 22: Caution: Debug-Related Matters
Chapter 1 Introduction 3.Caution: debug-related matters 3. Caution: debug-related matters ■ Stepwise execution of RETI command Under the circumstances where interruption is often generated when carrying out stepwise execution, only relevant interrupt processing routine is repeatedly executed after the stepwise execution of RETI. Therefore, main routine or low-level interruption program will not be executed.
Page 23: How To Use This Document
4. How to Use This Document ■ Main terminology: This table shows main terminology used for FR60. Term 32-bit-wide bus for internal instruction. I-bus Since FR60 series employ internal Harvard architecture, instruction and data are independent bus. For I-bus, Harverd/Prinston-bus-converter is connected. Internal 32-bit-wide data bus.
Page 24 Chapter 1 Introduction 4.How to Use This Document ■ Access size and address position Offset Address There are three kinds of accesses such as Byte access, Half-word access and Word access. However, note that some registers have restricted access. For more information, see “3.2. I/O Map (Page No.24)” or “Detail Description of Register”...
Page 25 ■ About access size and bit position Register name Register mark (1) Counter control register (Higher byte) This is the register (higher byte) which controls up/down counter operation. CCRH0 (Up/down counter 0): address 00B4h (Access: Byte, Half-word, Word) CCRH1 (Up/down counter 1): address 00B8h (Access: Byte, Half-word, Word) M16E/Reserved bit15: Enable 16-bit mode M16E (CCRH0 only)
Page 26 Chapter 1 Introduction 4.How to Use This Document ■ Meaning of Bit Attribute Symbols : Readable : Writable : Reading operation during read/modify/write operation. “/” (Slash) R/W: Readable and writable. (The read value is the value written.) “,” (comma) R,W: Values are different between read and write. (The read value is different from the value written.) : The read value is “0”.
Page 27: Chapter 2 Mb91460 Rev.a/Rev.b Overview
Chapter 2 MB91460 Rev.A/Rev.B Overview 1. Overview MB91460 is a series of standard microcontrollers containing a range of I/O peripherals and bus control functions. MB91460 features a 32-bit RISC CPU (FR60 series) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing. MB91460 derivatives also contain up to 16 kByte instruction cache memory and other internal memories to improve the execution speed of the CPU.
Page 28 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • 4 words (16 bytes) per set • Variable capacity (4/2/1 kB) • Lock function enabling programs to be resident • Available as instruction RAM requiring no wait state when not used as an instruction cache •...
Page 29 • 3 types of transfer sources (external pins/internal peripherals/and software) • Up to 128 selectable internal transfer sources • Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed) • Transfer mode (Demand transfer/burst transfer/step transfer/block transfer) • Fly-by transfer supported (between external I/O and memory) •...
Page 30 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features 2.10 Peripheral Function • General-purpose port : Up to 288 • N channel open drain port out of above: 8 (for I • A/D converter : 32 channels (1 unit) • Series-parallel type • Resolution: 10 bits •...
Page 31 • 16-bit reload counter • Includes clock prescaler (f • Free-run timer : 16 bits x 8 channels • 16-bit free running counter, signals an interrupt when overflow or match with compare register • Includes prescaler (f • Timer data register has R/W access •...
Page 32 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • LIN-USART (LIN=Local Interconnect Network) : 16 channels • Full-duplex double buffer system (4 ch with 16 byte RX/TX FIFO buffer each) • With parity/without parity selectable • 1 or 2 stop bits selectable •...
Page 33 the range of 1 to 1.5 cycles of the resource clock (CLKP) • PFM (pulse frequency modulator) : 16 bits x 1 channel • 16-bit reload timers for generating high/low pulse waveforms • Includes clock prescaler (f • Sound Generator : 1 channel •...
Page 34 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • Prescaler value for 32 kHz is 001FFF • Clock monitor (clock output function): 1 channel • Clock supervisor • Monitors external 32kHz and 4MHz for fails (e.g. crystal breaks) • Switches in case of fail to an available recovery clock (subclock or RC clock) •...
Page 35: Mb91460 Series Product Lineup
3. MB91460 Series Product Lineup Feature Core frequency Resource frequency Technology Watchdog Watchdog (RC osc. based) Bit Search Reset Input (INITX) Clock Modulator Low Power Mode MAC (uDSP) MMU/MPU Flash Flash Protection D-bus RAM I/D-bus RAM I-bus RAM / I-Cache Boot-ROM / BI-ROM Free Running Timer Reload Timer...
Page 36 Chapter 2 MB91460 Rev.A/Rev.B Overview 3.MB91460 Series Product Lineup Feature ADC (10 bit) Alarm Comparator Supply Supervisor Clock Supervisor Main clock oscillator Sub clock oscillator RC Oscillator DSU4 EDSU JTAG Boundary Scan Supply Voltage Regulator Power Consumption Temperatur Range (Ta) Package Power on to PLL run Flash Download Time...
Page 37: Block Diagram
Chapter 2 MB91460 Rev.A/Rev.B Overview 4.Block Diagram 4. Block Diagram The following illustration shows the block diagram of MB91460 series. Figure 4-1 Block Diagram MB91460 Series M−Bus D−Bus I−Bus F−Bus...
Page 38 Chapter 2 MB91460 Rev.A/Rev.B Overview 4.Block Diagram...
Page 39: Chapter 3 Mb91460 Series Basic Information
Chapter 3 MB91460 Series Basic Information 1.Memory Map Chapter 3 MB91460 Series Basic Information This chapter describes MB91460 series basic information including Memory- and I/O map, inter- rupt vector table, pin function list, circuit type and pin state table for each device mode. 1.
Page 40: I/O Map
Chapter 3 MB91460 Series Basic Information 2.I/O Map 2. I/O Map This section shows the association between memory space and each register of peripheral resources. • Table convention Address offset/Register name Address 000000 PDRD[R/W] xxxxxxxx Register initial value ("0", "1", "X" : undefined, "-" : not implemented) Register name (First column register is 4n address, Second column register is 4n+2 address...) Leftmost register address...
Page 41 Table 2-1 I/O Map Address PDR00 [R/W] 000000 XXXXXXXX PDR04 [R/W] 000004 XXXXXXXX PDR08 [R/W] 000008 XXXXXXXX PDR12 [R/W] 00000C XXXXXXXX PDR16 [R/W] 000010 XXXXXXXX PDR20 [R/W] 000014 XXXXXXXX PDR24 [R/W] 000018 XXXXXXXX PDR28 [R/W] 00001C XXXXXXXX PDR32 [R/W] 000020 XXXXXXXX 000024 00002C...
Page 42 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address SCR01 [R/W,W] 000048 00000000 ESCR01 [R/W] 00004C 00000X00 SCR02 [R/W,W] 000050 00000000 ESCR02 [R/W] 000054 00000X00 SCR03 [R/W,W] 000058 00000000 ESCR03 [R/W] 00005C 00000X00 SCR04 [R/W,W] 000060 00000000 ESCR04 [R/W] 000064 00000X00 SCR05 [R/W,W] 000068...
Page 43 Address BGR100 [R/W] 000080 00000000 BGR102 [R/W] 000084 00000000 BGR104 [R/W] 000088 00000000 BGR106 [R/W] 00008C 00000000 PWC20 [R/W] 000090 - - - - - - XX XXXXXXXX 000094 res. PWC21 [R/W] 000098 - - - - - - XX XXXXXXXX 00009C res.
Page 44 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IBCR0 [R/W] 0000D0 00000000 ITMKH0 [R/W] 0000D4 00 - - - - 11 0000D8 res. IBCR1 [R/W] 0000DC 00000000 ITMKH1 [R/W] 0000E0 00 - - - - 11 0000E4 res. 0000E8 LCDCMR [R/W] - - - - 0000 0000EC...
Page 45 Address PTMR02 [R] 000120 11111111 11111111 PDUT02 [W] 000124 XXXXXXXX XXXXXXXX PTMR03 [R] 000128 11111111 11111111 PDUT03 [W] 00012C XXXXXXXX XXXXXXXX PTMR04 [R] 000130 11111111 11111111 PDUT04 [W] 000134 XXXXXXXX XXXXXXXX PTMR05 [R] 000138 11111111 11111111 PDUT05 [W] 00013C XXXXXXXX XXXXXXXX PTMR06 [R] 000140...
Page 46 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address P0TMCSRH 000170 [R/W] - 0 - 000 - 0 P0TMRLR [W] 000174 XXXXXXXX XXXXXXXX P1TMRLR [W] 000178 XXXXXXXX XXXXXXXX 00017C 000180 res. IPCP0 [R] 000184 XXXXXXXX XXXXXXXX IPCP2 [R] 000188 XXXXXXXX XXXXXXXX OCS01 [R/W] 00018C - - - 0 - - 00 0000 - - 00...
Page 47 Address TMRLR1 [W] 0001B8 XXXXXXXX XXXXXXXX 0001BC reserved TMRLR2 [W] 0001C0 XXXXXXXX XXXXXXXX 0001C4 reserved TMRLR3 [W] 0001C8 XXXXXXXX XXXXXXXX 0001CC reserved TMRLR4 [W] 0001D0 XXXXXXXX XXXXXXXX 0001D4 reserved TMRLR5 [W] 0001D8 XXXXXXXX XXXXXXXX 0001DC reserved TMRLR6 [W] 0001E0 XXXXXXXX XXXXXXXX 0001E4 reserved TMRLR7 [W]...
Page 48 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TCDT2 [R/W] 0001F8 XXXXXXXX XXXXXXXX TCDT3 [R/W] 0001FC XXXXXXXX XXXXXXXX 000200 000204 000208 00020C 000210 000214 000218 00021C 000220 000224 000228 00023C 000240 DMACR [R/W] 0 - - 00000 000244 00024C 000250 000254 Register...
Page 49 Address 000258 00027C SCR08 [R/W,W] 000280 00000000 ESCR08 [R/W] 000284 00000X00 SCR09 [R/W,W] 000288 00000000 ESCR09 [R/W] 00028C 00000X00 SCR10 [R/W,W] 000290 00000000 ESCR10 [R/W] 000294 00000X00 SCR11 [R/W,W] 000298 00000000 ESCR11 [R/W] 00029C 00000X00 SCR12 [R/W,W] 0002A0 00000000 ESCR12 [R/W] 0002A4 00000X00 SCR13 [R/W,W]...
Page 50 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address SCR14 [R/W,W] 0002B0 00000000 ESCR14 [R/W] 0002B4 00000X00 SCR15 [R/W,W] 0002B8 00000000 ESCR15 [R/W] 0002BC 00000X00 BGR108 [R/W] 0002C0 00000000 BGR110 [R/W] 0002C4 00000000 BGR112 [R/W] 0002C8 00000000 BGR114 [R/W] 0002CC 00000000 0002D0 res.
Page 51 Address TCDT5 [R/W] 0002F4 XXXXXXXX XXXXXXXX TCDT6 [R/W] 0002F8 XXXXXXXX XXXXXXXX TCDT7 [R/W] 0002FC XXXXXXXX XXXXXXXX UDRC1 [W] 000300 00000000 UDCCH0 [R/W] 000304 00001000 UDCCH1 [R/W] 000308 00001000 00030C UDRC3 [W] 000310 00000000 UDCCH2 [R/W] 000314 00001000 UDCCH3 [R/W] 000318 00001000 00031C GCN13 [R/W]...
Page 52 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address PTMR14 [R] 000340 11111111 PDUT14 [W] 000344 XXXXXXXX PTMR15 [R] 000348 11111111 PDUT15 [W] 00034C XXXXXXXX 000350 00035C 000360 res. DADR0 [R/W] 000364 - - - - - - XX XXXXXXXX IBCR2 [R/W] 000368 00000000...
Page 53 Address 0003D8 0003E0 0003E4 0003E8 0003EC 0003F0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400 00043C Chapter 3 MB91460 Series Basic Information Register reserved reserved reserved BSD0 BSD1 [R/W] BSDC BSRR...
Page 54 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address ICR00 [R/W] 000440 ---11111 ICR04 [R/W] 000444 ---11111 ICR08 [R/W] 000448 ---11111 ICR12 [R/W] 00044C ---11111 ICR16 [R/W] 000450 ---11111 ICR20 [R/W] 000454 ---11111 ICR24 [R/W] 000458 ---11111 ICR28 [R/W] 00045C ---11111 ICR32 [R/W] 000460...
Page 55 Address PLLDIVM [R/W] 00048C - - - - 0000 PLLCTRL [R/W] 000490 - - - - 0000 OSCC1 [R/W] 000494 - - - - - 010 PORTEN [R/W] 000498 - - - - - - 00 0004A0 res. 0004A4 - - - - - - - - - - - XXXXX XXXXXXXX XXXXXXXX WTHR [R/W] 0004A8 - - - 00000...
Page 56 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address C340R [R/W] 0004D0 - - - - - - - 0 SHDE [R/W] 0004D4 0 - - - - - - - EXTLV [R/W] 0004D8 00000000 00000000 0004DC 00063C Register EISSRH [R/W] res.
Page 57 Address ASR0 [R/W] 000640 00000000 00000000 ASR1 [R/W] 000644 XXXXXXXX XXXXXXXX ASR2 [R/W] 000648 XXXXXXXX XXXXXXXX ASR3 [R/W] 00064C XXXXXXXX XXXXXXXX ASR4 [R/W] 000650 XXXXXXXX XXXXXXXX ASR5 [R/W] 000654 XXXXXXXX XXXXXXXX ASR6 [R/W] 000658 XXXXXXXX XXXXXXXX ASR7 [R/W] 00065C XXXXXXXX XXXXXXXX AWR0 [R/W] 000660 01111111 11111*11...
Page 58 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 0007FC res. 000800 000BFC TVCTW [W] 000C00 XXXXXXXX 000C04 000CFC PDRD00 [R] 000D00 XXXXXXXX PDRD04 [R] 000D04 XXXXXXXX PDRD08 [R] 000D08 XXXXXXXX PDRD12 [R] 000D0C XXXXXXXX PDRD16 [R] 000D10 XXXXXXXX PDRD20 [R] 000D14 XXXXXXXX PDRD24 [R]...
Page 59 Address DDR00 [R/W] 000D40 00000000 DDR04 [R/W] 000D44 00000000 DDR08 [R/W] 000D48 00000000 DDR12 [R/W] 000D4C 00000000 DDR16 [R/W] 000D50 00000000 DDR20 [R/W] 000D54 00000000 DDR24 [R/W] 000D58 00000000 DDR28 [R/W] 000D5C 00000000 DDR32 [R/W] 000D60 00000000 000D64 000D7C PFR00 [R/W] 000D80 11111111 PFR04 [R/W]...
Page 60 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 000DA4 000DBC EPFR00 [R/W] 000DC0 00000000 EPFR04 [R/W] 000DC4 00000000 EPFR08 [R/W] 000DC8 00000000 EPFR12 [R/W] 000DCC 00000000 EPFR16 [R/W] 000DD0 00000000 EPFR20 [R/W] 000DD4 00000000 EPFR24 [R/W] 000DD8 00000000 EPFR28 [R/W] 000DDC 00000000 EPFR32 [R/W]...
Page 61 Address PODR00 [R/W] 000E00 00000000 PODR04 [R/W] 000E04 00000000 PODR08 [R/W] 000E08 00000000 PODR12 [R/W] 000E0C 00000000 PODR16 [R/W] 000E10 00000000 PODR20 [R/W] 000E14 00000000 PODR24 [R/W] 000E18 00000000 PODR28 [R/W] 000E1C 00000000 PODR32 [R/W] 000E20 00000000 000E24 000E3C PILR00 [R/W] 000E40 00000000 PILR04 [R/W]...
Page 62 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 000E64 000E7C EPILR00 [R/W] 000E80 00000000 EPILR04 [R/W] 000E84 00000000 EPILR08 [R/W] 000E88 00000000 EPILR12 [R/W] 000E8C 00000000 EPILR16 [R/W] 000E90 00000000 EPILR20 [R/W] 000E94 00000000 EPILR24 [R/W] 000E98 00000000 EPILR28 [R/W] 000E9C 00000000 EPILR32 [R/W]...
Page 63 Address PPER00 [R/W] 000EC0 00000000 PPER04 [R/W] 000EC4 00000000 PPER08 [R/W] 000EC8 00000000 PPER12 [R/W] 000ECC 00000000 PPER16 [R/W] 000ED0 00000000 PPER20 [R/W] 000ED4 00000000 PPER24 [R/W] 000ED8 00000000 PPER28 [R/W] 000EDC 00000000 PPER32 [R/W] 000EE0 00000000 000EE4 000EFC PPCR00 [R/W] 000F00 11111111 PPCR04 [R/W]...
Page 64 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 000F24 000F3C 001000 001004 001008 00100C 001010 001014 001018 00101C 001020 001024 001028 006FFC FMCS [R/W] 007000 01101000 FMWT [R/W] 007004 11111111 11111111 007008 00700C 007010 007014 007FFC Register reserved DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
Page 65 Address 008000 MB91V460 Boot-ROM size is 4kB : 00B000 (instruction access is 1 waitcycle, data access is 1 waitcycle) 00BFFC CTRLR0 [R/W] 00C000 00000000 00000001 ERRCNT0 [R] 00C004 00000000 00000000 INTR0 [R] 00C008 00000000 00000000 BRPER0 [R/W] 00C00C 00000000 00000000 IF1CREQ0 [R/W] 00C010 00000000 00000001...
Page 66 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IF2CREQ0 [R/W] 00C040 00000000 00000001 IF2MSK20 [R/W] 00C044 11111111 11111111 IF2ARB20 [R/W] 00C048 00000000 00000000 IF2MCTR0 [R/W] 00C04C 00000000 00000000 IF2DTA10 [R/W] 00C050 00000000 00000000 IF2DTB10 [R/W] 00C054 00000000 00000000 00C058 00C05C IF2DTA20 [R/W] 00C060...
Page 67 Address TREQR20 [R] 00C080 00000000 00000000 TREQR40 [R] 00C084 00000000 00000000 TREQR60 [R] 00C088 00000000 00000000 TREQR80 [R] 00C08C 00000000 00000000 NEWDT20 [R] 00C090 00000000 00000000 NEWDT40 [R] 00C094 00000000 00000000 NEWDT60 [R] 00C098 00000000 00000000 NEWDT80 [R] 00C09C 00000000 00000000 INTPND20 [R] 00C0A0 00000000 00000000...
Page 68 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address CTRLR1 [R/W] 00C100 00000000 00000001 ERRCNT1 [R] 00C104 00000000 00000000 INTR1 [R] 00C108 00000000 00000000 BRPER1 [R/W] 00C10C 00000000 00000000 IF1CREQ1 [R/W] 00C110 00000000 00000001 IF1MSK21 [R/W] 00C114 11111111 11111111 IF1ARB21 [R/W] 00C118 00000000 00000000 IF1MCTR1 [R/W]...
Page 69 Address IF2CREQ1 [R/W] 00C140 00000000 00000001 IF2MSK21 [R/W] 00C144 11111111 11111111 IF2ARB21 [R/W] 00C148 00000000 00000000 IF2MCTR1 [R/W] 00C14C 00000000 00000000 IF2DTA11 [R/W] 00C150 00000000 00000000 IF2DTB11 [R/W] 00C154 00000000 00000000 00C158 00C15C IF2DTA21 [R/W] 00C160 00000000 00000000 IF2DTB21 [R/W] 00C164 00000000 00000000 00C168...
Page 70 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TREQR21 [R] 00C180 00000000 00000000 TREQR41 [R] 00C184 00000000 00000000 TREQR61 [R] 00C188 00000000 00000000 TREQR81 [R] 00C18C 00000000 00000000 NEWDT21 [R] 00C190 00000000 00000000 NEWDT41 [R] 00C194 00000000 00000000 NEWDT61 [R] 00C198 00000000 00000000 NEWDT81 [R]...
Page 71 Address CTRLR2 [R/W] 00C200 00000000 00000001 ERRCNT2 [R] 00C204 00000000 00000000 INTR2 [R] 00C208 00000000 00000000 BRPER2 [R/W] 00C20C 00000000 00000000 IF1CREQ2 [R/W] 00C210 00000000 00000001 IF1MSK22 [R/W] 00C214 11111111 11111111 IF1ARB22 [R/W] 00C218 00000000 00000000 IF1MCTR2 [R/W] 00C21C 00000000 00000000 IF1DTA12 [R/W] 00C220 00000000 00000000...
Page 72 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IF2CREQ2 [R/W] 00C240 00000000 00000001 IF2MSK22 [R/W] 00C244 11111111 11111111 IF2ARB22 [R/W] 00C248 00000000 00000000 IF2MCTR2 [R/W] 00C24C 00000000 00000000 IF2DTA12 [R/W] 00C250 00000000 00000000 IF2DTB12 [R/W] 00C254 00000000 00000000 00C258 00C25C IF2DTA22 [R/W] 00C260...
Page 73 Address TREQR22 [R] 00C280 00000000 00000000 TREQR42 [R] 00C284 00000000 00000000 TREQR62 [R] 00C288 00000000 00000000 TREQR82 [R] 00C28C 00000000 00000000 NEWDT22 [R] 00C290 00000000 00000000 NEWDT42 [R] 00C294 00000000 00000000 NEWDT62 [R] 00C298 00000000 00000000 NEWDT82 [R] 00C29C 00000000 00000000 INTPND22 [R] 00C2A0 00000000 00000000...
Page 74 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address CTRLR3 [R/W] 00C300 00000000 00000001 ERRCNT3 [R] 00C304 00000000 00000000 INTR3 [R] 00C308 00000000 00000000 BRPER3 [R/W] 00C30C 00000000 00000000 IF1CREQ3 [R/W] 00C310 00000000 00000001 IF1MSK23 [R/W] 00C314 11111111 11111111 IF1ARB23 [R/W] 00C318 00000000 00000000 IF1MCTR3 [R/W]...
Page 75 Address IF2CREQ3 [R/W] 00C340 00000000 00000001 IF2MSK23 [R/W] 00C344 11111111 11111111 IF2ARB23 [R/W] 00C348 00000000 00000000 IF2MCTR3 [R/W] 00C34C 00000000 00000000 IF2DTA13 [R/W] 00C350 00000000 00000000 IF2DTB13 [R/W] 00C354 00000000 00000000 00C358 00C35C IF2DTA23 [R/W] 00C360 00000000 00000000 IF2DTB23 [R/W] 00C364 00000000 00000000 00C368...
Page 76 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TREQR23 [R] 00C380 00000000 00000000 TREQR43 [R] 00C384 00000000 00000000 TREQR63 [R] 00C388 00000000 00000000 TREQR83 [R] 00C38C 00000000 00000000 NEWDT23 [R] 00C390 00000000 00000000 NEWDT43 [R] 00C394 00000000 00000000 NEWDT63 [R] 00C398 00000000 00000000 NEWDT83 [R]...
Page 77 Address CTRLR4 [R/W] 00C400 00000000 00000001 ERRCNT4 [R] 00C404 00000000 00000000 INTR4 [R] 00C408 00000000 00000000 BRPER4 [R/W] 00C40C 00000000 00000000 IF1CREQ4 [R/W] 00C410 00000000 00000001 IF1MSK24 [R/W] 00C414 11111111 11111111 IF1ARB24 [R/W] 00C418 00000000 00000000 IF1MCTR4 [R/W] 00C41C 00000000 00000000 IF1DTA14 [R/W] 00C420 00000000 00000000...
Page 78 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IF2CREQ4 [R/W] 00C440 00000000 00000001 IF2MSK24 [R/W] 00C444 11111111 11111111 IF2ARB24 [R/W] 00C448 00000000 00000000 IF2MCTR4 [R/W] 00C44C 00000000 00000000 IF2DTA14 [R/W] 00C450 00000000 00000000 IF2DTB14 [R/W] 00C454 00000000 00000000 00C458 00C45C IF2DTA24 [R/W] 00C460...
Page 79 Address TREQR24 [R] 00C480 00000000 00000000 TREQR44 [R] 00C484 00000000 00000000 TREQR64 [R] 00C488 00000000 00000000 TREQR84 [R] 00C48C 00000000 00000000 NEWDT24 [R] 00C490 00000000 00000000 NEWDT44 [R] 00C494 00000000 00000000 NEWDT64 [R] 00C498 00000000 00000000 NEWDT84 [R] 00C49C 00000000 00000000 INTPND24 [R] 00C4A0 00000000 00000000...
Page 80 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address CTRLR5 [R/W] 00C500 00000000 00000001 ERRCNT5 [R] 00C504 00000000 00000000 INTR5 [R] 00C508 00000000 00000000 BRPER5 [R/W] 00C50C 00000000 00000000 IF1CREQ5 [R/W] 00C510 00000000 00000001 IF1MSK25 [R/W] 00C514 11111111 11111111 IF1ARB25 [R/W] 00C518 00000000 00000000 IF1MCTR5 [R/W]...
Page 81 Address IF2CREQ5 [R/W] 00C540 00000000 00000001 IF2MSK25 [R/W] 00C544 11111111 11111111 IF2ARB25 [R/W] 00C548 00000000 00000000 IF2MCTR5 [R/W] 00C54C 00000000 00000000 IF2DTA15 [R/W] 00C550 00000000 00000000 IF2DTB15 [R/W] 00C554 00000000 00000000 00C558 00C55C IF2DTA25 [R/W] 00C560 00000000 00000000 IF2DTB25 [R/W] 00C564 00000000 00000000 00C568...
Page 82 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TREQR25 [R] 00C580 00000000 00000000 TREQR45 [R] 00C584 00000000 00000000 TREQR65 [R] 00C588 00000000 00000000 TREQR85 [R] 00C58C 00000000 00000000 NEWDT25 [R] 00C590 00000000 00000000 NEWDT45 [R] 00C594 00000000 00000000 NEWDT65 [R] 00C598 00000000 00000000 NEWDT85 [R]...
Page 83 Address 00F000 - - - - - - - - - - - - - - - - 11111100 00000000 00F004 - - - - - - - - - - - - - 000 00000000 10 - - 000000 00F008 00000000 00000000 00000000 00000000 00F00C...
Page 84 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 00F080 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
Page 85 Address 00F0C0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0CC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0D0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0D4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0D8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0DC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E4...
Page 86 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 010000 013FFC 014000 017FFC 018000 01BFFC 01C000 01FFFC Register Cache TAG way 1 (010000 - 0107FC Cache TAG way 2 (014000 - 0147FC Cache RAM way 1 (018000 - 0187FC Cache RAM way 2 (01C000 - 01C7FC Block...
Page 87 Address 020000 MB91V460 D-RAM size is 64kB : 020000 02FFFC 030000 MB91V460 I-/D-RAM size is 64kB : 030000 (instruction access is 0 waitcycles, data access is 1 waitcycle) 03FFFC 040000 05FFFC 060000 07FFFC 080000 09FFFC 0A0000 0BFFFC 0C0000 0DFFFC 0E0000 0FFFF4 0FFFF8 0FFFFC...
Page 88 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 200000 27FFFC 280000 2FFFFC 300000 37FFFC 380000 3FFFFC 400000 47FFFC 480000 4FFFFC Write operations to address 0FFFF8 shown above will be read. Notes: Use a read access (byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt accep- tance of the CPU) to a preceding write access to the resources on R-bus (e.g.
Page 89: Interrupt Vector Table
3. Interrupt Vector Table This section shows the allocation of interrupt and interrupt vector/interrupt register. Interrupt number Interrupt Decimal Reset Mode vector System reserved System reserved System reserved CPU supervisor mode (INT #5 instruction) Memory Protection excep- tion Co-processor fault trap Co-processor error trap INTE instruction...
Page 90 Chapter 3 MB91460 Series Basic Information 3.Interrupt Vector Table External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 4 Reload Timer 5...
Page 91 USART (LIN) 2 RX USART (LIN) 2 TX USART (LIN) 3 RX USART (LIN) 3 TX System reserved Delayed Interrupt System reserved System reserved USART (LIN, FIFO) 4 RX USART (LIN, FIFO) 4 TX USART (LIN, FIFO) 5 RX USART (LIN, FIFO) 5 TX USART (LIN, FIFO) 6 RX USART (LIN, FIFO) 6 TX USART (LIN, FIFO) 7 RX...
Page 92 Chapter 3 MB91460 Series Basic Information 3.Interrupt Vector Table Input Capture 0 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Output Compare 0 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5...
Page 93 Prog. Pulse Gen. 14 Prog. Pulse Gen. 15 Up/Down Counter 0 Up/Down Counter 1 Up/Down Counter 2 Up/Down Counter 3 Real Time Clock Calibration Unit A/D Converter 0 Alarm Comparator 0 Alarm Comparator 1 Low Voltage Detection Timebase Overﬂow PLL Clock Gear DMA Controller Main/Sub OSC stability wait Boot Security vector...
Page 94: Package
Chapter 3 MB91460 Series Basic Information 4.Package 4. Package ■ BGA-660P-M02 package (BGA660-03EK): MB91V460 BGA660-03EK Figure 4-1 External Dimension of...
Page 95: Pin Assignment Diagram
Chapter 3 MB91460 Series Basic Information 5.Pin Assignment Diagram 5. Pin Assignment Diagram ■ MB91V460 (BGA660 package) Figure 5-1 Pin Assignment Diagram of BGA660-03EK...
Page 96: Pin Definitions
Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions 6. Pin Definitions AL38 P00_7 AJ37 P00_6 AJ36 P00_5 AJ35 P00_4 AH36 P00_3 AH35 P00_2 AK38 P00_1 AJ38 P00_0 AH37 P01_7 AG37 P01_6 AG35 P01_5 AG36 P01_4 AF35 P01_3 AF36 P01_2 AH38 P01_1 AF37 P01_0...
Page 97 P04_4 P04_3 P04_2 P04_1 P04_0 P05_7 P05_6 P05_5 P05_4 P05_3 P05_2 P05_1 P05_0 P06_7 P06_6 P06_5 P06_4 P06_3 P06_2 P06_1 P06_0 P07_7 P07_6 P07_5 P07_4 P07_3 P07_2 P07_1 P07_0 P08_7 P08_6 P08_5 BGRNTX BGRNTX P08_4 P08_3 P08_2 P08_1 P08_0 P09_7 P09_6 P09_5 P09_4...
Page 98 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P12_7 P12_6 P12_5 P12_4 P12_3 P12_2 P12_1 P12_0 P13_7 P13_6 P13_5 P13_4 P13_3 P13_2 P13_1 P13_0 P14_7 P14_6 P14_5...
Page 99 P15_2 P15_1 P15_0 P16_7 P16_6 P16_5 P16_4 P16_3 P16_2 P16_1 P16_0 P17_7 P17_6 P17_5 P17_4 P17_3 P17_2 P17_1 P17_0 P18_7 P18_6 P18_5 P18_4 P18_3 P18_2 P18_1 P18_0 P19_7 P19_6 P19_5 P19_4 P19_3 P19_2 P19_1 P19_0 P20_7 P20_6 P20_5 P20_4 P20_3 P20_2 P20_1 P20_0...
Page 100 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions P21_5 P21_4 P21_3 P21_2 P21_1 P21_0 P22_7 P22_6 P22_5 P22_4 P22_3 P22_2 P22_1 P22_0 P23_7 P23_6 P23_5 P23_4 P23_3 P23_2 P23_1 P23_0 P24_7 P24_6 P24_5 P24_4 P24_3 P24_2 P24_1 P24_0 P25_7 P25_6 P25_5 P25_4 P25_3...
Page 101 P26_0 P27_7 P27_6 P27_5 P27_4 P27_3 P27_2 P27_1 P27_0 ALARM_1 ALARM_0 P28_7 P28_6 P28_5 P28_4 P28_3 P28_2 P28_1 P28_0 P29_7 P29_6 P29_5 P29_4 P29_3 P29_2 P29_1 P29_0 P30_7 P30_6 P30_5 P30_4 P30_3 P30_2 P30_1 P30_0 P31_7 P31_6 P31_5 P31_4 P31_3 P31_2 P31_1 P31_0...
Page 102 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions P32_5 P32_4 P32_3 P32_2 P32_1 P32_0 P33_7 P33_6 P33_5 P33_4 P33_3 P33_2 P33_1 P33_0 P34_7 P34_6 P34_5 P34_4 P34_3 P34_2 P34_1 P34_0 P35_7 P35_6 P35_5 P35_4 P35_3 P35_2 P35_1 P35_0 INITX RSTX HSTX NMIX MD_2...
Page 103 ICLK ICD_3 ICD_2 ICD_1 ICD_0 ICS_2 ICS_1 ICS_0 BREAK PLEVEL EXRAM TRSTX TCLK TOEX TWRX TCE1X TADSCX TAD_15 TAD_14 TAD_13 TAD_12 TAD_11 TAD_10 TAD_9 TAD_8 TAD_7 TAD_6 TAD_5 TAD_4 TAD_3 TAD_2 TAD_1 TAD_0 TDT_68 TDT_67 TDT_66 TDT_65 TDT_64 TDT_63 TDT_62 TDT_61 TDT_60 TDT_59...
Page 104 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions TDT_56 TDT_55 TDT_54 TDT_53 TDT_52 TDT_51 TDT_50 TDT_49 TDT_48 TDT_47 TDT_46 AU10 TDT_45 AT10 TDT_44 AR10 TDT_43 AT11 TDT_42 AR11 TDT_41 TDT_40 AV10 TDT_39 AU11 TDT_38 AU12 TDT_37 AR12 TDT_36 AT12 TDT_35 AR13 TDT_34 AT13...
Page 105 AR18 TDT_11 AV18 TDT_10 AR19 TDT_9 AU19 TDT_8 AT19 TDT_7 AV19 TDT_6 AT20 TDT_5 AV20 TDT_4 AR20 TDT_3 AU20 TDT_2 AR21 TDT_1 AV21 TDT_0 AV22 EMRAM AU21 ECSX AT21 EWRX_3 AU22 EWRX_2 AT22 EWRX_1 AR22 EWRX_0 AR23 EECSX AV23 EEWEX AU23 EEOEX AV24...
Page 106 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions AR29 EEA_0 AT29 EED_31 AR30 EED_30 AT30 EED_29 AU31 EED_28 AU32 EED_27 AV31 EED_26 AV32 EED_25 AT31 EED_24 AV33 EED_23 AR32 EED_22 AV34 EED_21 AU33 EED_20 AU34 EED_19 AT32 EED_18 AT33 EED_17 AR33 EED_16 AV35...
Page 107 AK37 FLASH_FRSTX VDD5 VDD5 VDD5 VDD5 VDD5 AP11 VDD5 AP19 VDD5 AP23 VDD5 AP31 VDD5 AM35 VDD5 AH34 VDD5 AD34 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VSS5 VSS5 VSS5 VSS5 AJ34 VSS5 AE34 VSS5 AA34 VSS5 VSS5 VSS5 VSS5 VSS5...
Page 108 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions HVDD5 HVSS5 HVSS5 HVSS5 AVSS AVRL AVRH5 AVCC5 AVRH3 AVCC3 VDD5R VDD5R VDD5R VDD5R AA38 VCC3C VCC3C VCC3C VCC3C VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VSS3 VSS3...
Page 109 AP20 VSS3 AP24 VSS3 AP28 VSS3 AP30 VSS3 AT36 VSS3 AU37 VSS3 AL34 VSS3 TS00_0 TS00_0 TS00_0 TS00_0 TS00_0 TS00_0 TS00_0 Chapter 3 MB91460 Series Basic Information 6.Pin Deﬁnitions...
Page 110: I/O Circuit Type
Chapter 3 MB91460 Series Basic Information 7.I/O Circuit Type 7. I/O Circuit Type The table below describes the circuit types which are used on the evaluation device MB91V460 Rev.A. Please refer to the datasheets for information about the circuit type of each pin used on the flash devices. Pull Up/ Type Pull Down...
Page 111 TE11_0 TE20_0 TE21_0 Dn (ctrl) TE22_0 TS00_0 TS01_0 TS02_0 Chapter 3 MB91460 Series Basic Information Tool Tool Tool Tool VDD 5V 7.I/O Circuit Type 8 mA 4 mA 4 mA 8 mA...
Page 112: Pin State Table
Chapter 3 MB91460 Series Basic Information 8.Pin State Table 8. Pin State Table Explanation of the meaning of words and phrases used in the pin state table according to the chosen mode. • Input enable: It is possible to input a signal to the device. •...
Page 113 AD35 P03_7 AC35 P03_6 AB37 P03_5 AC36 P03_4 AA37 P03_3 AB36 P03_2 AD38 P03_1 AC38 P03_0 AB35 AA36 AB38 AA35 MONCL P04_7 P04_6 P04_5 P04_4 P04_3 P04_2 P04_1 P04_0 P05_7 P05_6 P05_5 P05_4 P05_3 P05_2 P05_1 P05_0 P06_7 P06_6 P06_5 P06_4 P06_3 P06_2...
Page 114 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P08_7 P08_6 BGRNT P08_5 P08_4 P08_3 WRX3 P08_2 WRX2 P08_1 WRX1 P08_0 WRX0 P09_7 CSX7 P09_6 CSX6 P09_5 CSX5 P09_4 CSX4 P09_3 CSX3 P09_2 CSX2 P09_1 CSX1 P09_0 CSX0 P10_7 P10_6 MCLKE MCLKE P10_5 MCLKI MCLKI /MCLKI P10_4 MCLKO MCLKO /MCLKO...
Page 115 P12_7 DEOP3 DEOP3 P12_6 DEOTX3DEOTX3 DEOP3 P12_5 DACKX3 DACKX3 P12_4 DREQ3 DREQ3 P12_3 DEOP2 DEOP2 P12_2 DEOTX2DEOTX2 DEOP2 P12_1 DACKX2 DACKX2 P12_0 DREQ2 DREQ2 P13_7 DEOP1 DEOP1 P13_6 DEOTX1DEOTX1 DEOP1 P13_5 DACKX1 DACKX1 P13_4 DREQ1 DREQ1 P13_3 DEOP0 DEOP0 P13_2 DEOTX0DEOTX0 DEOP0 P13_1 DACKX0 DACKX0 P13_0 DREQ0 DREQ0 ICU7/...
Page 116 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P17_7 P17_6 P17_5 P17_4 P17_3 P17_2 P17_1 P17_0 P18_7 P18_6 P18_5 P18_4 P18_3 P18_2 P18_1 P18_0 P19_7 P19_6 P19_5 P19_4 P19_3 P19_2 P19_1 P19_0 P20_7 P20_6 P20_5 P20_4 P20_3 P20_2 P20_1 P20_0 P21_7 P21_6...
Page 117 P22_7 SCL1 P22_6 SDA1 P22_5 SCL0 P22_4 SDA0 P22_3 P22_2 P22_1 P22_0 P23_7 P23_6 P23_5 P23_4 P23_3 P23_2 P23_1 P23_0 INT15 Output Hi-Z, Output Hi-Z, INT14 Input Input enabled enabled INT13 INT12 INT11 Output Hi-Z, Output Hi-Z, INT10 Input Input enabled enabled INT9...
Page 118 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P24_7 P24_6 P24_5 P24_4 P24_3 P24_2 P24_1 P24_0 P25_7 P25_6 P25_5 P25_4 P25_3 P25_2 P25_1 P25_0 P26_7 P26_6 P26_5 P26_4 P26_3 P26_2 P26_1 P26_0 P27_7 P27_6 P27_5 P27_4 P27_3 P27_2 P27_1 P27_0 ALARM_ ALARM_...
Page 119 P29_7 P29_6 P29_5 P29_4 P29_3 P29_2 P29_1 P29_0 P30_7 P30_6 P30_5 P30_4 P30_3 COM3 P30_2 COM2 P30_1 COM1 P30_0 COM0 P31_7 SEG39 P31_6 SEG38 P31_5 SEG37 P31_4 SEG36 P31_3 SEG35 P31_2 SEG34 P31_1 SEG33 P31_0 SEG32 P32_7 SEG31 P32_6 SEG30 SCK15 P32_5 SEG29 SOT15 P32_4...
Page 120 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P34_7 P34_6 P34_5 P34_4 P34_3 P34_2 P34_1 P34_0 P35_7 P35_6 P35_5 P35_4 P35_3 P35_2 P35_1 P35_0 INITX RSTX HSTX NMIX MD_2 MD_1 MD_0 SEG15 SEG14 SCK11 SEG13 SOT11 Output Hi-Z, Output Hi-Z, SEG12 SIN11 Input Input...
Page 121: Chapter 4 Cpu Architecture
Chapter 4 CPU Architecture This chapter describes the architecture of FR60 family CPU. 1. Overview The CPUs of the FR60 family series employ RISC architecture and advanced function instructions for embedded application. CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. “32- bit/16-bit bus converter”...
Page 122: Features
Chapter 4 CPU Architecture 2.Features 2. Features ■ Features of internal architecture • RISC architecture • Base instruction: 1 instruction/1 cycle • 32-bit architecture • General-purpose register: 32-bit x 16 • 4GB of linear memory space • Equipped with multiplier. •32-bit x 32-bit multiplication: 5 cycles •16-bit x 16-bit multiplication: 3 cycles •...
Page 123: Cpu
3. CPU The CPU realizes the compact implementation of a 32-bit RISC FR architecture. It employs a 5-stage instruction pipeline method to execute 1 instruction per 1 cycle. This pipeline consists of the following stages. • Instruction fetch (IF): outputs instruction address to fetch instruction. •...
Page 124: Instruction Overview
Chapter 4 CPU Architecture 6.Instruction Overview 6. Instruction Overview The FR60 family supports logic operation, bit operation and direct addressing instruction optimized for embedded application as well as general RISC instruction system. Instruction-set list is shown in the appendix. Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it enables you to generate compact program code.
Page 125: Data Structure
7. Data Structure FR60 has two data allocations as follows. ■ Bit Ordering FR60 uses little endian as bit ordering. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ■...
Page 126: Word Alignment
Chapter 4 CPU Architecture 8.Word Alignment 8. Word Alignment Since instructions and data are accessed by byte, allocated addresses vary by instruction length or data width. ■ Program Access FR60 program is required to be allocated in addresses multiplied by 2. PC's bit0 is cleared for instruction execution upon the PC update.
Page 127: Addressing
9. Addressing Address space is 32-bit linear. ■ Map 0000 0000 0000 0100 0000 0200 0000 0400 000F FC00 000F FFFF FFFF FFFF FR60’s logical address space is 4GB (2 ■ Direct Addressing Area The following areas are used for I/O. These spaces are referred to as direct addressing area where you can specify direct operand address by the instruction.
Page 128 Chapter 4 CPU Architecture 9.Addressing...
Page 129: Chapter 5 Cpu Registers
Chapter 5 CPU Registers 1. General-purpose Registers Registers R0 through R15 are general-purpose registers. These registers are used for accumulator and memory access pointers on various operations. Of 16 registers, the following registers are reserved for special application. • R13: Virtual accumulator •...
Page 130 Chapter 5 CPU Registers 2.Dedicated Registers 2.1 PC: Program Counter Program Counter (PC) consists of 32 bits. Figure 2-2 Bit Structure of Program Counter (PC) Program counter (PC) indicates active instruction address. Upon the execution of the instruction, program counter (PC)’s bit 0 is cleared. 2.2 PS: Program Status Register Program status register (PS) is the register to hold program status which consists of three parts including ILM, SCR and CCR.
Page 131 This bit becomes “0” by reset. • [Bit 3] N: Negative flag This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers. It indicates that operation result is positive value. It indicates that operation result is negative value. •...
Page 132 Chapter 5 CPU Registers 2.Dedicated Registers program. ■ ILM: Interrupt Level Mask Register Figure 2-6 Register Structure of Interrupt Level Mask Register (ILM) ILM4 • This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask. •...
Page 133 ■ Caution: PS Register Since some instructions have already processed PS register in advance, the following exception operations may break interrupt processing routine during the use of debugger, or update PS flag data. In either cases, after returning from EIT, it is designed to execute the correct process so that operations before and after EIT will be processed in accordance with specification.
Page 134 Chapter 5 CPU Registers 2.Dedicated Registers 2.3 TBR: Table-base Register Table-base register (TBR) consists of 32 bits. Figure 2-7 Bit Structure of Table-base Register (TBR) Table-base register holds head address of vector table used for EIT processes. Vector address is made by adding offset value specified in TBR and EIT each. 2.4 RP: Return Pointer Return pointer (RP: Return Pointer) consists of 32 bits.
Page 135 2.6 USP: User Stack Pointer User Stack Pointer (USP) consists of 32 bits. Figure 2-10 Bit Structure of User Stack Pointer (USP) When S flag is “1”, this pointer works as R15. You can explicitly specify USP. You can not use it for RETI instruction. This pointer saves and returns PC and PS values at the position where system stack pointer (SSP) indicates.
Page 136 Chapter 5 CPU Registers 2.Dedicated Registers 2.7 MDH, MDL: Multiply & Divide Register Multiply & Divide register (MDH/MDL) consists of 32 bits. Figure 2-12 Bit Structure of Multiply & Divide Register (MDH/MDL) This is the register for multiplication and division and consists of 32 bits. Initial value by reset is indeterminate.
Page 137: Chapter 6 Eit: Exceptions, Interrupts And Traps
Chapter 6 EIT: Exceptions, Interrupts and Traps 1. Overview EIT means that some events interrupt current program to execute other programs. EIT stands for Exception, Interrupt and Trap. • Exception is the event which is generated in association with active context. It is returned to the instruction which triggered the exception.
Page 138: Eit Interrupt Level
Chapter 6 EIT: Exceptions, Interrupts and Traps 5.EIT Interrupt Level 5. EIT Interrupt Level Interrupt level is between 0 and 31, and controlled with 5 bits. Table 5-1 Interrupt Level of EIT Level Binary Decimal 00000 (Reserved for system) 00011 (Reserved for system) 00100 INTE instruction...
Page 139: Multiple Eit Processing
7. Multiple EIT Processing If multiple EITs are generated at the same time, CPU repeats the operation which selects one of the EIT to accept, and then executes EIT sequence, and detects EIT again. If there is no EIT to accept upon detecting EIT, CPU executes instruction of the last accepted EIT handler.
Page 140 Chapter 6 EIT: Exceptions, Interrupts and Traps 7.Multiple EIT Processing Main routine Priority (High) Generation of NMI (Middle) Execution of INT instruction (Low) Execution of user interrupt Figure 7-1 Multiple EITs Process INT instruction handler User interrupt handler (2) Second execution (3) Third execution NMI handler (1) First execution...
Page 141: Operation
8. Operation In the following sections, note that source “PC” means instruction address which detected each EIT trigger. Similarly, “address of next instruction” means the following addresses based on the instruction which detected the EIT. • When LDI is 32: PC+6 •...
Page 142 Chapter 6 EIT: Exceptions, Interrupts and Traps 8.Operation 8.2 Operation of INT Instruction INT No. u8 instruction is operated as follows. Branches to interrupt handler of vector specified in u8. ■ Operation 1. The contents of the program status (PS) are saved to the system stack. 2.
Page 143 8.4 Operation of Step Trace Trap If you set T flag at SCR within PS and enable step trace trap function, step trace trap is generated with each executing instruction. ■ Condition for detecting step trace trap T flag = 1 Instructions are other than delayed branch command.
Page 144: Caution
Chapter 6 EIT: Exceptions, Interrupts and Traps 9.Caution 8.6 Coprocessor Absent Trap If you execute coprocessor instruction for unmounted coprocessor, coprocessor absent trap is generated. ■ Operation 1. The contents of the program status (PS) are saved to the system stack. 2.
Page 145: Chapter 7 Branch Instruction
Chapter 7 Branch Instruction FR60 can instruct the operation with and without delay slot for branch instruction. 1. Branch Instruction with Delay Slot • Branch instruction with delay slot JMP:D @Ri CALL:D label12 BRA:D label9 BNO:D label9 BC:D label9 BNC:D label9 BV:D label9 BNV:D label9 BLE:D label9...
Page 146: Actual Example (With Delay Slot)
Chapter 7 Branch Instruction 3.Actual Example (with Delay Slot) 3. Actual Example (with Delay Slot) 3.1 JMP:D @Ri / CALL:D @Ri Instruction Ri referred in JMP:D @Ri / CALL:D @Ri instruction remains intact even if instructions within delay slot update Ri. •...
Page 147: Restrictions On Branch Instruction With Delay Slot
4. Restrictions on Branch Instruction with Delay Slot 4.1 Available Instructions for Delay Slot Instructions which meet the following requirements can only be executed in delay slot. • 1-cycle instruction • Non-branch instruction • Instruction which does not affect any operation even if its sequence is changed. “1-cycle instruction”...
Page 148: Branch Instruction Without Delay Slot
Chapter 7 Branch Instruction 5.Branch Instruction without Delay Slot 5. Branch Instruction without Delay Slot • Branch instruction without delay slot: JMP @Ri BRA label9 BC label9 BV label9 BLE label9 6. Operation of Branch Instruction without Delay Slot Operation without delay slot executes instructions in the order of instructions and never executes the instruction located in the next address where a branch instruction exists before branch.
Page 149: Chapter 8 Device State Transition
Chapter 8 Device State Transition 1. Overview MB91460 basically has devices state and flow as shown below. For more information, see “3. State Transition Diagram (Page Power-on INITX INT-pin input 2. Features ■ Device state • RUN (Normal operation): State where the program is executed. •...
Page 150: State Transition Diagram
Chapter 8 Device State Transition 3.State Transition Diagram 3. State Transition Diagram This section describes state transition. Figure 3-1 State Transition of MB91460 Series INIT pin = 0 (INIT) INIT pin = 1 (Cancel of INIT) Termination of oscillation-stabilization wait Cancel of reset (RST) Software reset (RST) Sleep (Writing instruction)
Page 151 3.1 RUN (Normal Operation) This is the state where program is executed with all clocks and all circuits are enabled. This state has various paths for a state transition. However, if the synchronous reset mode is selected the state transition operations for some requests are different from normal reset mode. For more information, see the chapter of “Chapter 9 Reset (Page 3.2 SLEEP...
Page 152 Chapter 8 Device State Transition 3.State Transition Diagram 3.5 Oscillation-stabilization-wait Reset This is the state where the device is stopped. This state is entered upon a setting-initialization reset (INIT). All internal circuits are stopped except for clock generation control parts (timebase counter and device state control parts).
Page 153 Chapter 8 Device State Transition 3.State Transition Diagram...
Page 154 Chapter 8 Device State Transition 3.State Transition Diagram...
Page 155: Chapter 9 Reset
Chapter 9 Reset 1. Overview When a reset is triggered, the device halts the program and all hardware operation, and then initializes all states. This state is called a reset. When the reset trigger condition is removed, the device changes from this initialized state to restart the program and hardware operation.
Page 156: Configuration
Chapter 9 Reset 3.Conﬁguration • A settings initialization reset (INIT) is followed by an operation reset (RST) after the oscillation stabilization time elapses. 3. Configuration State transition control circuit (reset related) OSCD1 STCR: bit1 STCR: bit1 Main clock continues to operate during stop mode Main clock halts during stop mode STCR: bit0 STCR: bit0...
Page 157: Registers
4. Registers 4.1 RSRR: Reset Cause Register Stores the cause of the previous reset, and sets the period and activation control for the watchdog timer. • RSRR: Address 0480h (Access: Byte, Half-word) INIT HSTB WDOG R/WX R/WX R/WX Note: See “Meaning of Bit Attribute Symbols (Page Reading the reset request cause returns the reset cause flags and then clears the flag values to “0”.
Page 158 Chapter 9 Reset 4.Registers Indicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST). SRST No RST has been triggered by a software reset. RST has been triggered by a software reset. The software reset occurred flag (SRST) is cleared to “0” after reading. •...
Page 159 4.2 STCR: Standby Control Register This register is used for software reset control (changing to standby mode, pin control in stop mode, and clock oscillation halted in stop mode), and specifies the oscillation stabilization wait time. Note: See also “Chapter 10 Standby (Page •...
Page 160 Chapter 9 Reset 4.Registers 4.3 MOD: Mode Pins These pins specify the location of the mode vector and reset vector that are read after the MCU is reset. Mode pins Mode name MD2 MD1 Internal ROM mode External ROM mode 4.4 Mode Vector The data written to the mode register (MODR) by the mode vector fetch operation is called the mode data.
Page 161 Initial value to load into PC. Mode 000FFFF8 XXXXXXXX XXXXXXXX XXXXXXXX Vector Reset 000FFFFC Vector 4.6 Device Mode Overview The following table gives an overview about supported device mode combinations on the MB91460 series: Mode pins Mode/Reset Vector MD2 MD1 MD0 access area Internal External...
Page 162: Init Pin Input (Init: Settings Initialization Reset)
Chapter 9 Reset 5.INIT Pin Input (INIT: Settings Initialization Reset) 5. INIT Pin Input (INIT: Settings Initialization Reset) 5.1 Trigger The pin is used to trigger a settings initialization reset. A settings initialization reset (INIT) request remains active while the pin remains at the “L” level. Keep the “L”...
Page 163 5.6 Reset Cancellation Sequence After the cancellation (removal) of the settings initialization reset (external INITX pin) request the device performs the following operations in the sequence listed. 1. Removal of settings initialization reset (INIT) 2. Set operation reset (RST) state and start internal clock 3.
Page 164: Watchdog Reset (Init: Settings Initialization Reset)
Chapter 9 Reset 6.Watchdog Reset (INIT: Settings Initialization Reset) 6. Watchdog Reset (INIT: Settings Initialization Reset) 6.1 Trigger Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a watchdog reset request is generated unless “A5 delay register (WPR) within the time specified by the watchdog period selection bits (RSRR.WT[1:0]).
Page 165: Software Reset (Rst: Operation Initialization Reset)
7. Software Reset (RST: Operation Initialization Reset) 7.1 Trigger Writing “0” to the software reset bit (STCR.SRST) generates a software reset request. A software reset requests an operation reset (RST). 7.2 Releasing the Reset Request The software reset request is released after the request is received and the operation reset (RST) generated. 7.3 Flag When software reset request triggers an operation reset (RST), the software reset flag (RSRR.SRST) is set to “1”.
Page 166: Reset Operation Modes
Chapter 9 Reset 8.Reset Operation Modes 8. Reset Operation Modes The following two different modes can be used for an operation reset (RST): • Normal (asynchronous) reset mode • Synchronous reset mode Which mode to use is specified by the synchronous reset operation enable bit (TBCR.SYNCR). Pin input resets and watchdog resets always use normal reset mode.
Page 167: Mcu Operation Mode
9. MCU Operation Mode After release of a reset, the MCU starts operation in the mode specified by the mode pins and mode data. Operation mode Bus mode Access mode 9.1 Bus Modes and Access Modes ■ Bus mode The bus mode controls internal ROM operation and the external access function. The bus mode is specified by the mode setting pins (MD2, MD1, MD0) and internal ROM enable bit (Mode-Vector.
Page 168: Caution
Chapter 9 Reset 10.Caution 10. Caution • INIT pin input Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also, after turning on the power, ensure a sufficient oscillation stabilization wait time is provided for the oscillation circuit by holding the input to the pin at the “L”...
Page 169 Chapter 9 Reset 10.Caution...
Page 170 Chapter 9 Reset 10.Caution...
Page 171: Chapter 10 Standby
Chapter 10 Standby 1. Overview Two standby modes (low power consumption modes) are available. • Sleep mode: Stops the program • Stop mode: Shuts down the device Note: It is possible to keep the Real Time Clock active in STOP mode (see chapter RTC). 2.
Page 172: Configuration
Chapter 10 Standby 3.Conﬁguration 3. Configuration SYNCS TB CR: bit0 Setting prohibited Synchronous standby OSCD1 STCR: bit0 Do not halt main clock oscillation during stop mode. Halt main clock oscillation during stop mode. STCR: bit5 Maintain same states during stop mode. Set pins to high impedance during stop mode.
Page 173: Registers
4. Registers 4.1 STCR: Standby Control Register Used to control transition to the stop and sleep standby modes, and to specify the pin states and whether to halt the oscillation during stop mode. Note: See “Chapter 9 Reset (Page • STCR: Address 0481h (Access: Byte) STOP SLEEP (See...
Page 174 Chapter 10 Standby 4.Registers • Bit0: Main clock oscillation halt OSCD1 4.2 TBCR: Timebase timer control register This register controls the timebase timer interrupts and the options for resets and standby operation. Note: See also “Chapter 19 Timebase Timer (Page •...
Page 175: Operation
5. Operation 5.1 Sleep Mode ■ Entering sleep mode Writing “1” to the sleep mode bit (STCR.SLEEP) changes to sleep mode. The device remains in this mode until an event occurs to wakeup the device from sleep mode. (See “8. Caution (Page No.165)”.) ■...
Page 176 Chapter 10 Standby 5.Operation 5.2 Stop mode ■ Entering stop mode Writing “1” to the stop mode bit (STCR.STOP) changes to stop mode. The device remains in this mode until an event occurs to wakeup the device from stop mode. (See “8.
Page 177: Settings
6. Settings Table 6-1 Settings Required to Change to Sleep Mode Setting Interrupt settings Synchronous standby settings Change to sleep mode Operational restrictions *:For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings Required to Change to Stop Mode Setting Selects the oscillation stabilization wait time...
Page 178 Chapter 10 Standby 7.Q&A 7.2 How do I change to stop mode? • When operating on the main PLL clock, the operating clock must be set to the main clock divided by two. “7.3 How do I select the operating clock source? (Page the operating clock.
Page 179 7.6 How do I recover from stop mode? The following events end stop mode: • The following four interrupts change the device to the oscillation stabilization wait state. • External level-detect interrupt or edge-detect interrupt. • Oscillation stabilization wait timer for the main clock when oscillation not halted. •...
Page 180 Chapter 10 Standby 7.Q&A...
Page 181: Caution
8. Caution • Points to note when changing to sleep mode When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”). Also, in order to change to sleep mode with synchronous standby operation enabled, the STCR register must be read after writing to the SLEEP bit.
Page 182 Chapter 10 Standby 8.Caution...
Page 183: Chapter 11 Memory Controller
Chapter 11 Memory Controller 1. Overview This module combines the interfaces to the F-Bus memory resources, FLASH and General Purpose RAM (also ref- erenced as I/D-RAM). These memories can be combined CODE and DATA storage. While code fetch is possible in general via the F-Bus at the FR core, due to performance reasons the code fetch is accellerated by a direct I-Bus connection in MB91460 series MCUs.
Page 184: Registers
Chapter 11 Memory Controller 7.Registers • Reset vector address: 0x000ffffc; return 0x00030000 at RAM execution mode (jump to test pro- gram) or return 0x0000bff8 in any other case (jump to Boot ROM) • If FMCS_FIXE is switched off, the FLASH memory can be accessed on addresses 0x000ffff8 and 0x000ffffc.
Page 185: Explanations Of Registers
8. Explanations of Registers ● FLASH Interface Control Register Control Register byte 0 Address : 7000 Read/write ⇒ (R/W) (R/W) (R/W) (R) Default value⇒ Control Register byte 1 Address : 7001 Read/write ⇒ Default value⇒ Control Register byte 2 Address : 7002 Read/write ⇒...
Page 186 Chapter 11 Memory Controller 8.Explanations of Registers • BIT[29]: BIRE - Burn-In ROM Enable Disable Burn-In ROM and enable FLASH access at Burn-In ROM address Enable access to the Burn-In ROM (default) The BIRE bit is a reserved bit and should not be used. •...
Page 187 It is recommended to always refer to the setting requirements of ATDIN, EQIN and waitcycles for each product which are provided by Fujitsu (see the related datasheets). (PHASE setting is not available on MB91460 series) Chapter 11 Memory Controller 8.Explanations of Registers...
Page 188 Some embedded FLASH memories supports switching the 64 bit read mode to increase the access per- formance. Please contact Fujitsu if this feature is available on the product you are using. This bit is cleared after reset. The 32 bit read and write access to the FLASH memory is enabled by de- fault.
Page 189 • BIT[7]: FLUSH - Flush instruction cache entries Flushing the instruction cache entries has been completed Actually ﬂushing the instruction cache entries This bit is set after reset. If the FLUSH bit is set, the instruction cache entries are flushed sequentially. During this initialization the cache is disabled.
Page 190 Chapter 11 Memory Controller 8.Explanations of Registers • BIT[4]: PFMC - Prefetch Miss Cache enable Standard cache algorithm (default) Prefetch misses are cached only This bit is cleared after reset. The prefetch miss cache is disabled by default. The instruction cache uses the stand- ard algorithm of writing cache entries for each accessed instruction word from FLASH.
Page 191 • BIT[1:0]: SZ[1:0] - Cache size configuration 0kByte - Cache disabled 4kByte (1024 entries) 8kByte (2048 entries) 16kByte (4096 entries) (default) The cache size is set to ’11’ after reset. The cache size can be configured on the evaluation device (EVA). Remark: The number of cache entries determines the TAG initialization period at device startup, see the explanai- tion of the FLUSH bit above.
Page 192 Chapter 11 Memory Controller 8.Explanations of Registers WTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. The WTP configuration is in units of clock cycles. The value of WTP should be set to the intra page access time (cycle time) of the FLASH memory in number of clock cycles, subtracted by one.
Page 193 FLASH access cycle waveform flash_start ATDIN EQIN flash_wait tATD Figure 8-1 Timing of a FLASH access cycle Figure shows the example of a FLASH access cycle. In the FMWT register the three parts of the FLASH timing tATD, tALEH, tEQ and tWTC can be configured independently. The table below lists the configuration values for this example.
Page 194 Chapter 11 Memory Controller 8.Explanations of Registers ● FLASH Memory Adddress Check register (FMAC) Address 7008 -------- This register captures the address at the begin of a FLASH access cycle for test purposes. The register could be read only. ● Non-cacheable area definition The non-cacheable area definition registers FCHA0 and FCHA1 define the FLASH region not to be cached.
Page 195: Chapter 12 Instruction Cache
Chapter 12 Instruction Cache This chapter describes the instruction cache memory included in MB91460 family members and its operation. 1. General description The instruction cache is a fast local memory for temporary storage. Once an instruction is accessed to be fetched from external slower memory, the instruction cache holds the instruction code inside to increase the speed of accessing the same code from then on.
Page 196 Chapter 12 Instruction Cache 2.Main body structure Way 1 Way 2 [Bits 31 to 9] Address tag This area stores the upper 23 bits of the memory address of the instruction cached in the corresponding block. For example, memory address IA of the instruction data stored in sub- block k in block i is obtained from the following equation: IA = address tag x 2 The address tag is used to check for a match with the instruction address requested for...
Page 197 FLUSHbit is set to "0" when the cache is flushed.) [Bit 1] LRU bit (way 1 only) This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed.
Page 198 Chapter 12 Instruction Cache 2.Main body structure [Bit 7] RAM: RAM Mode Setting this bit to "1" causes the cache to operate in RAM mode. By placing the cache in RAM mode, the cache RAM is mapped as shown in Figure I-CACHE-3 while the cache is enabled with the ENAB bit set to "1".
Page 199 Chapter 12 Instruction Cache 2.Main body structure Figure 2-3 I-Cache Address Map...
Page 200 Chapter 12 Instruction Cache 2.Main body structure Figure 2-4 I-Cacheable Area...
Page 201: Operating Mode Conditions
3. Operating mode conditions ● Cache status in various operating modes The table below indicates the prevailing state for disable and flush when the associated bit is changed by bit manipulation instruction, etc. Immediately after a Reset Contents Cache Memory undefined Address Contents...
Page 202: Cacheable Areas In The Instruction Cache
Chapter 12 Instruction Cache 4.Cacheable areas in the instruction cache ● Cache Entry Update Cache entries are updated as shown in the following table. Not updated Miss The memory data is loaded, and the cache entry data is updated. 4. Cacheable areas in the instruction cache •...
Page 203 To disable the I-Cache, set the ENAB bit to 0. Idi #0x000003e7,r0 Idi #0B00000000,r1 stb r1,@r0 In the resultant state (same as state prevailing after reset), there appears to be no cache. The cache can be turned off if the processing may experience problems due to cache overhead Locking all cached instructions To lock all the currently-cached instructions in the I-Cache, set the register GBLK bit to 1.
Page 204 Chapter 12 Instruction Cache 5.Settings for handling the I-Cache Only lock information is released; locked instructions are replaced sequentially with new instructions according to the state of the LRU bit.
Page 205: Chapter 13 Clock Control
Chapter 13 Clock Control 1. Overview The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator. The circuit supports a range of clock speeds from the high speed clock (100MHz maximum) to the low speed clock (32.768kHz).
Page 206: Configuration
Chapter 13 Clock Control 3.Conﬁguration • External bus clock (CLKT): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16 The clock used by the external bus expansion interface. The circuits that use this clock are as follows. • External bus expansion interface •...
Page 207: Registers
4. Registers 4.1 CLKR: Clock Source Control Register Selects the clock source for the base clock used to run the MCU and controls the PLL. • CLKR: Address 0484h (Access: Byte) R/W0 R/W0 R/W0 (See “Meaning of Bit Attribute Symbols (Page •...
Page 208 Chapter 13 Clock Control 4.Registers • After setting “11B” (subclock), insert one or more NOP instructions. • Selecting the subclock as the clock source is prohibited while the subclock selection enable bit (SCKEN) is “0”. (See table for details.) Table 4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modiﬁed Modify permitted “00”...
Page 209 4.2 DIV0R: Clock Division Setting Register 0 Sets the division ratio for the clocks used for internal device operation. DIVR0: Address 0486h (Access: Byte, Half-word) (See “Meaning of Bit Attribute Symbols (Page • Sets up the clock for the CPU and internal buses (CLKB), and the clock for the peripheral circuits and peripheral bus (CLKP).
Page 210 Chapter 13 Clock Control 4.Registers 1010 1011 1100 1101 1110 1111 • Sets the clock division ratio for the clock used by the peripheral circuits and peripheral bus (CLKP). The 16 options listed in the table are available. • Do not set a division ratio that exceeds the maximum operating frequency of the MCU. Φ/11 Φ/12 Φ/13...
Page 211 4.3 DIV1R: Clock Division Setting Register 1 Sets the division ratio for the clocks used for internal device operation. • DIVR1: Address 0487h (Access: Byte, Half-word) (See “Meaning of Bit Attribute Symbols (Page Sets the clock division ratio (relative to the base clock) for the clock used by the external bus interface (CLKT). •...
Page 212 Chapter 13 Clock Control 4.Registers 4.4 CSCFG: Clock Source Conﬁguration Register This register controls the main clock oscillation in subclock mode • CSCFG: Address 04AEh (Access: Byte) EDSUEN PLLLOCK RCSEL (See “Meaning of Bit Attribute Symbols (Page • bit7: EDSU/MPU Enable EDSUEN EDSU/MPU is (clock) disabled [Initial value] EDSU/MPU is (clock) enabled...
Page 213 Chapter 13 Clock Control 4.Registers -1-- Subclock Calibration is sourced by RC Oscillation 0--- LCD Controller is sourced by Sub Oscillation 1--- LCD Controller is sourced by RC Oscillation...
Page 214 Chapter 13 Clock Control 4.Registers 4.5 OSCCR: Oscillation Control Register This register controls the main clock oscillation in subclock mode • OSCCR: Address 04CCh (Access: Byte) – – – RX/WX RX/WX RX/WX (See “Meaning of Bit Attribute Symbols (Page • bit7-2: Undefined bit Writing does not affect the operation.
Page 215: Operation
5. Operation This section describes how to setup and switch between clocks. 5.1 Clock Setup Sequence (Example) Setup operating clocks. Setup base clock. 5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example) (1) Select sub clock mode. (2) Halt main PLL (PLL1EN = "0"), halt main clock oscillation (OSCDS1 = "0") Sub clock mode with main clock...
Page 216 Chapter 13 Clock Control 5.Operation 5.3 Notes ■ Main PLL control After initialization, the main PLL oscillation is halted. While halted, the output of the main PLL cannot be selected as the clock source. After the program starts, first set the multiplier for the main PLL that you want to use as the clock source and then, after allowing a time for the main PLL to lock, change the clock source.
Page 217: Settings
6. Settings Table 6-1 Settings for Operating at 1/2 of the Main Clock Setting Clock source selection *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings for Operating Using the Main PLL Setting Main PLL operation enable Clock source selection *: For the setting procedure, refer to the section indicated by the number.
Page 218 Chapter 13 Clock Control 7.Q & A 7. Q & A 7.1 How do I enable or disable clock operation? • There is no operation enable bit for the main clock. Main clock operation is always enabled. (Halting the oscillation in subclock mode or stop mode is handled separately.) •...
Page 219 7.4 How do I set the operation clock division ratios? • CPU clock setting The CPU clock setting is set using the CLKB division ratio selection bits (DIVR0.B[3:0]). PLL multiplier ratio To select no division To select divide by 2 To select divide by 3 To select divide by 4 To select divide by 5...
Page 220 Chapter 13 Clock Control 7.Q & A 7.5 How do I halt the main clock in sub clock mode? Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS1). Operation in subclock mode To not halt the main clock To halt the main clock (See “8.
Page 221: Caution
8. Caution • Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and division ratio setting result in a frequency that exceeds the maximum. • Take care with the sequence in which you set or modify the clock source selection. •...
Page 222 Chapter 13 Clock Control 8.Caution...
Page 223: Chapter 14 Pll Interface
Chapter 14 PLL Interface 1. Overview • This blockdiagram (simplified) shows the integration of the PLL and the PLL Interface with the multiplier control logic (1/M, 1/N for basic frequency multiplication and 1/G for clock auto gear). Interface MAIN Osc. Phase Correction 2.
Page 224: Registers
Chapter 14 PLL Interface 4.Registers 4. Registers 4.1 PLL Control Registers Controls the PLL multiplier ratio (divide-by-M and divide-by-N) and the automatic clock gear up/down function. • PLLDIVM: Address 048Ch (Access: Byte, Halfword, Word) R0/W0 R0/W0 R0/W0 (See “Meaning of Bit Attribute Symbols (Page •...
Page 225 (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bits.The read value is always “0”. • Bit5-0: PLL divide-by-N selection DVN5-DVN0 000000 000001 000010 000011 000100 000101 000110 000111 111111 (Note) The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”). (Note) It is strongly recommended to disable the PLL (CLKR.PLL1EN=0) while or after changing the PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR.PLL1EN=1) afterwards.
Page 226 Chapter 14 PLL Interface 4.Registers • PLLMULG: Address 048Fh (Access: Byte, Halfword, Word) MLG7 MLG6 MLG5 (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bitThe read value is always “0”. • Bit5-0: PLL auto gear divide-by-G step multiplier selection MLG5-MLG0 00000000 00000001...
Page 227 • While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-G counter reaches the programmed end value. • This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect. •...
Page 228: Recommended Settings
Chapter 14 PLL Interface 5.Recommended Settings 5. Recommended Settings PLL Input Frequency Parameter (CK) DIVM [MHz] • Important remark: Not all settings which are shown in this table are available for all devices. Please consult the available datasheet for each device for the maximum allowed PLL output and the allowed maximum frequencies for each clock domain (CLKB, CLKP and CLKT) respectively.
Page 229: Clock Auto Gear Up/Down
6. Clock Auto Gear Up/Down To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/ DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL interface. The main functionality is implemented using two divide-by counters (divide-by-M and divide-by-G counter), where one supplies the PLL feedback always with the target frequency (divide-by-M counter), and the other (divide-by-G counter) which increases the frequency from a programmable frequency divi-...
Page 230 Chapter 14 PLL Interface 6.Clock Auto Gear Up/Down this equals to (resolved closed arithmetic series of the first sum term): duration with i = G ; j = G - M ; mul = MULG ; t = 1/f(pllout) For the above given setting this equals 1483 PLL output clock cycles with a duration from the start fre- quency to the target frequency of 9262500 ps (about 9.3 us).
Page 231: Caution
7. Caution When using the clock auto-gear function it is strongly recommended to make use of the gear up and gear down flags (PLLCTRL.GRUP, PLLCTRL.GRDN) to evaluate the current state of this function to avoid malfunctions in the clock system due to setting changes prior to completion. Procedure example: •...
Page 232 Chapter 14 PLL Interface 7.Caution...
Page 233: Chapter 15 Can Clock Prescaler
Chapter 15 CAN Clock Prescaler 1. Overview • This blockdiagram (simplified) shows the integration of the CAN and the CAN Interface with the CAN clock prescaler logic (1/C) and clock source selector. MAIN Osc. Clock Unit • Remark: If the CLKCAN source is set either to main oscillator or to PLL output then the clock for the CAN is not influenced by the clock modulation.
Page 234: Registers
Chapter 15 CAN Clock Prescaler 3.Registers 3. Registers 3.1 CAN Clock Control Register Controls the CAN clock source, the clock division ratio and the clock disable. • CANPRE: Address 04C0h (Access: Byte) CPCKS1 CPCKS0 R0/W0 R0/W0 (See “Meaning of Bit Attribute Symbols (Page •...
Page 235 R/W0 R/W0 (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bitAlways write “0” to these register bits. • Bit5-0: CAN clock disable CANCKD5-CANCKD0 -----0 -----1 ----0- ----1- ---0-- ---1-- --0--- --1--- -0---- -1---- 0----- 1----- No.10)” for details of the attributes.) Function CAN controller 0 is enabled CAN controller 0 is disabled...
Page 236 Chapter 15 CAN Clock Prescaler 3.Registers...
Page 237: Chapter 16 Clock Supervisor
Chapter 16 Clock Supervisor 1.Overview Clock Supervisor Chapter 16 Clock Supervisor This section gives an overview of the Clock Supervisor. Purpose of the Clock Supervisor is the supervision of the main and sub oscillation clock. In case of main oscillation clock failure the Clock Supervisor control logic will take action, i.e.
Page 238: Clock Supervisor Register
Chapter 16 Clock Supervisor 2.Clock Supervisor Register 2. Clock Supervisor Register This section lists the Clock Supervisor Control Register and describes the function of each bit in detail. ■ Clock Supervisor Control Register (CSVCR) The Clock Supervisor Control Register (CSVCR) sets the operation mode of the Clock Supervisor. shows the configuration of the Clock Supervisor Control Register.
Page 239 Table 2-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR). Table 2-1 Functional Description of each bit of the Clock Supervisor Control Register Name SCKS (Sub-clock select) (Main clock missing) (Sub-clock missing) (RC-oscillator enable) MSVE (Main clock supervisor...
Page 240: Block Diagram Clock Supervisor
Chapter 16 Clock Supervisor 3.Block Diagram Clock Supervisor 3. Block Diagram Clock Supervisor This section presents a block diagram of the Clock Supervisor. The building blocks of the Clock Supervisor are: l Main Clock Supervisor l Sub-Clock Supervisor l Control Logic l RC-Oscillator ■...
Page 241: Operation Modes
4. Operation Modes This section describes all operation modes of the Clock Supervisor. ■ Operation mode with initial settings In case the clock supervisor control register (CSVCR) is not configured at the beginning of the user program, the RC-oscillator, the main clock supervisor and the sub-clock supervisor is enabled. •...
Page 242 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-1 Timing Diagram: Initial settings, main clock missing during power-on reset PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING...
Page 243 Figure 4-2 Timing Diagram: Initial settings, main clock missing during ’oscillation stabilisation wait time’ PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Chapter 16 Clock Supervisor 4.Operation Modes...
Page 244 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-3 Timing Diagram: Initial settings, main clock missing after ’oscillation stabilisation wait time’ PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING...
Page 245 Figure 4-4 Timing Diagram: Initial settings, sub-clock missing before timeout PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Chapter 16 Clock Supervisor 4.Operation Modes...
Page 246 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-5 Timing Diagram: Initial settings, sub-clock missing after timeout PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING...
Page 247 ■ Disabling the RC-oscillator and the clock supervisors The initial point of this scenario is that the RC-oscillator and main clock or sub-clock supervisor is enabled. • The RC-oscillator can be disabled by setting bit RCE (bit 4 of CSVCR) to ’0’. First disable the main clock and sub-clock supervisor.
Page 248 Chapter 16 Clock Supervisor 4.Operation Modes ■ Re-enabling the RC-oscillator and the clock supervisors The initial point of this scenario is that the RC-oscillator and both main clock and sub-clock supervisor are disabled. • The RC-oscillator can be enabled by setting RCE (bit 4 of CSVCR) to ’1’. •...
Page 249 ■ Sub-clock modes The main clock supervisor is automatically disabled in sub-clock modes. The enable bit MSVE remains unchanged. At transition from sub-clock mode to main clock mode the main clock supervisor is enabled after the ’oscillation stabilisation wait time’ with the rising edge of signal OSC_STAB or in case the main clock is missing before the completion of the ’oscillation stabilisation wait time’, after the ’main clock timeout’...
Page 250 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-9 Timing Diagram: Sub-clock missing in main clock mode, SRST=1 PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Clock Mode Main Main...
Page 251 Figure 4-10 Timing Diagram: Waking up from sub-clock mode PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Main Clock Mode Main Chapter 16 Clock Supervisor 4.Operation Modes...
Page 252: Stop Mode
Chapter 16 Clock Supervisor 4.Operation Modes ■ Stop mode RC-oscillator, main clock and sub-clock supervisors are enabled, they will be automatically disabled at transition into stop mode. The corresponding enable bits in the clock supervisor control register remain unchanged. So after wake-up from stop mode the RC-oscillator and the clock supervisors will be enabled again. If the corresponding enable bits are set to ’0’, the RC-oscillator and the clock supervisors will stay disabled after wake-up from stop mode.
Page 253 ■ Operation with single clock device In a single clock device the sub-clock supervisor can provide the RC-oscillation clock as sub-clock. To enable this feature, SCKS bit (bit7 of CSVCR) must be set to ’1’ (refer to Table 2-1for precautions when modifying this bit) and SRST must be ’0’...
Page 254 Chapter 16 Clock Supervisor 4.Operation Modes ■ Check if reset was asserted by the Clock Supervisor To find out whether the Clock Supervisor has asserted reset , the software must check the reset cause by reading the WDTC register at address A8 .
Page 255: Chapter 17 Clock Modulator
Chapter 17 Clock Modulator 1.Overview Chapter 17 Clock Modulator This chapter provides an overview of the Clock Modulator and its features. It describes the reg- ister structure and operation of the Clock Modulator. 1. Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies.
Page 256: Clock Modulator Registers
Chapter 17 Clock Modulator 2.Clock Modulator Registers 2. Clock Modulator Registers This section lists the clock modulator registers and describes the function of each register in de- tail. ● Clock modulator registers Figure 2-1 Clock modulator registers CMPRL (lower) Address: 0004B9 Initial value 1 1 1 1 1 1 0 1...
Page 257 ● Clock Modulator Control Register (CMCR) The Control Register (CMCR) has the following functions: Set the modulator to power down mode Modulator enable/disable in frequency modulation mode Indicates the status of the modulator Figure 2-2 Conﬁguration of the clock modulator control register (CMCR) 0004BB served served...
Page 258 Chapter 17 Clock Modulator 2.Clock Modulator Registers ● Clock modulator control register contents Table 2-1 Function of each bit of the clock modulator control register (1 / 2) Bit name bit7 undeﬁned bit 6 to 5 Reserved bit 4 Reserved bit 3 FMOD RUN: Modulator status...
Page 259 Table 2-1 Function of each bit of the clock modulator control register (2 / 2) Bit name bit 1 FMOD: Frequency modulation enable bit bit 0 PDX: Power down bit In the Table below the modulator states are summarized: Table 2-2 States of the modulator modulator disabled modulator power on, waiting modulator startup time (>...
Page 260 Chapter 17 Clock Modulator 2.Clock Modulator Registers Table 2-2 States of the modulator modulator enabled in frequency modulation mode, modulator is calibrating, modulation not active modulator is running in frequency modulation mode modulation is active ● Clock Modulation Parameter Register (CMPR) The Modulation Parameter Register (CMPR) determines the modulation degree in frequency modulation mode.
Page 261 Table 2-3 Function of each bit of the modulation parameter register (CMPR) Bit name bit 13 to 0 MP13 to 0: Modulation Parameter bits Depending on the PLL frequency the following modulation parameter settings are possible. The corresponding CMPR register value is stated in the most right column. Chapter 17 Clock Modulator 2.Clock Modulator Registers Function...
Page 262 Chapter 17 Clock Modulator 2.Clock Modulator Registers Frequency of unmodulated input clock (PLL frequency) Period of unmodulated input clock (PLL clock period) resolution: resolution of frequencies in the modulated clock. low (1) to high (7) minimal frequency occurring in the frequency modulated clock maximal frequency occurring in the frequency modulated clock phase skew: The maximal phase shift of the modulated clock relative to the unmodulated...
Page 263: Application Note
The table below shows the recommended setting for several MCU clocks and modulation parameters: Table 2-4 Modulation Parameter settings F0 (MHz) resolution degree Please refer to the datasheet of each device about modulation parameter settings. 3. Application Note Startup/stop sequence for frequency modulation mode. Modulation parameter for frequency modulation mode.
Page 264 Chapter 17 Clock Modulator 3.Application Note recommended. deﬁne the required PLL frequency based on performance needs determine the maximal allowed clock frequency of the MCU choose the setting with the highest resolution and the highest modulation degree, whose maximal frequency is below the maximal allowed clock frequency of the MCU.
Page 265: Chapter 18 Timebase Counter
Chapter 18 Timebase Counter 1. Overview The timebase counter is a 26-bit up-counter that counts the subclock or the main clock divided by two. When recovering from a state in which the selected clock source for the MCU has been, or may have been, halted, the MCU automatically changes to the oscillation stabilization wait state to avoid any unstable output from the oscillator.
Page 266: Configuration
Chapter 18 Timebase Counter 3.Conﬁguration ■ Events that invoke an oscillation stabilization wait using other than the timebase counter ● Wait time after power on: Provided by pin input ● Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait timer to generate this time is recommended.
Page 267: Registers
4. Registers 4.1 STCR: Standby Control Register Controls transition to standby modes, pin states during stop mode, whether to halt the clock during stop mode, the oscillation stabilization wait time, and software reset. Note: See also “Chapter 10 No.273)” chapters. •...
Page 268 Chapter 18 Timebase Counter 4.Registers 4.2 CLKR: Clock Source Control Register Selects the clock source for the base clock used to run the MCU and controls the PLL. Note: See also the “Chapter 13 Clock Control (Page • CLKR: Address 0484h (Access: Byte) R/W0 R/W0 R/W0...
Page 269: Operation
5. Operation This section describes the events that trigger an oscillation stabilization wait and the operation in each case. 5.1 INIT Pin Input An oscillation stabilization wait is required after power on. As the wait time provided by the initialized timebase counter is too short, the INIT pin input must be held at the “L”...
Page 270 Chapter 18 Timebase Counter 5.Operation 5.2 Watchdog Reset (The speciﬁed oscillation stabilization wait time is generated automatically) If a watchdog reset occurs while the main clock oscillation is halted, the oscillation stabilization wait time is generated automatically. (See figure below.) Figure 5-2 Using the time-base counter to provide the oscillation stabilization...
Page 271 ■ Watchdog reset when main clock operating Although no oscillation stabilization wait is required in this case, the specified wait time is generated automatically. 5.3 Recovering from Stop Mode via an Interrupt ■ When changing from main PLL operation to stop mode with the main clock oscillation halted (STCR.OSCD[2:1]=“11”): The main oscillation circuit generates the selected oscillation stabilization time automatically.
Page 272 Chapter 18 Timebase Counter 5.Operation ■ When changing to stop mode without halting the clock oscillation circuit (main PLL/main/ sub): Although no oscillation stabilization wait is required in this case, a wait is generated automatically. Accordingly, it is recommended that you set the interval time to its minimum value before changing to stop mode. •...
Page 273 5.7 Types of Oscillation Stabilization Wait ■ Timebase counter Automatically provides a count for the oscillation stabilization wait time. When a trigger occurs to change the device to the oscillation stabilization wait state, the timebase counter is cleared and then starts counting the specified oscillation stabilization wait time. ■...
Page 274 Chapter 18 Timebase Counter 5.Operation 5.8 Whether or not a Stabilization Wait is Required for Each State Transition See figure below.
Page 275: Settings
6. Settings Table 6-1 Settings Required to Specify the Oscillation Stabilization Wait Time Setting Oscillation stabilization wait time setting *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings Required to Setup an INITX Pin Reset Setting INITX pin input •...
Page 276 Chapter 18 Timebase Counter 7.Q&A 7. Q&A 7.1 How do I setup the oscillation stabilization wait time that is generated automatically? Use the oscillation stabilization wait time selection bits (STCR.OS[1:0]). (The following lists likely scenarios and the required settings.) Scenario To not halt the main PLL or oscillator during stop mode (No oscillation stabilization wait time required) To not stop the oscillator during external clock input or...
Page 277 7.2 How do I set the oscillation stabilization wait time without generating it automatically? The settings described below for various cases are required. State (before transition) × Wait time after power on Subclock operation × (main clock halted) Sub sleep, sub stop ×...
Page 278: Caution
Chapter 18 Timebase Counter 8.Caution 8. Caution • Clock source If the clock selected as the clock source is not stable, an oscillation stabilization wait time is required. • Oscillation stabilization wait time The wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) is not initialized by any reset except a reset triggered by the external INITX pin input, the RC based watchdog or the Clock Supervisor.
Page 279: Chapter 19 Timebase Timer
Chapter 19 Timebase Timer 1. Overview The timebase timer is a selector that uses the output from a 26-bit timebase counter using the base clock (F). The timebase timer is an interval-interrupt generating timer that is used to acquire main PLL lock wait time and to count a long time.
Page 280: Configuration
Chapter 19 Timebase Timer 3.Conﬁguration 3. Configuration Timebase timer Timebase timer Timebase counter (26-bit counter) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Base clock (φ) Timer clear CTBR CTBR Clears the counter after writing "A5h"...
Page 281: Register
4. Register 4.1 TBCR: Timebase Timer Control Register This register is used to set timebase timer interrupt control, reset/ standby operation option etc. Note: Refer also to “Chapter 10 Standby (Page • TBCR: Address 0482h (Access: Byte) TBIF TBIE TBC2 R(RM1),W (Refer to “Meaning of Bit Attribute Symbols (Page...
Page 282 Chapter 19 Timebase Timer 4.Register • Bit1: Enabling the synchronous reset operation SYNCR • Ordinary operation reset: Immediately resets the operation initialization when the operation initialization reset (RST) request is generated. Synchronous reset: Resets the operation initialization after all accesses to the bus have stopped. •...
Page 283: Operation
5. Operation Timebase timer operation is described. 5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait) Main PLL lock wait by the timebase timer Example of the Main PLL oscillation Timebase counter count 000h Clears the (CTBR) timebase counter Main PLL enable (PLL1EN) Timebase timer interrupt request enable (PLL1EN) Timebase timer interrupt...
Page 284: Setting
Chapter 19 Timebase Timer 6.Setting 6. Setting Table 6-1 Setting Required for the Timebase Timer Setting Setting the interval time Timebase counter clear *: Refer to the number for more information on the setting method. Table 6-2 Setting Required for Interrupting the Timebase Timer Setting Setting the timebase timer interrupt vector and interrupt level...
Page 285 7. Q & A 7.1 What are the types of interval time used in the timebase timer (and the timebase counter used by the timebase timer) and how to select them? There are eight types of interval time, and they are set using the interval selection bit (TBCR.TBC[2:0]). Timebase timer Interval time How to select Φ...
Page 286 Chapter 19 Timebase Timer 7.Q & A 7.7 What are the interrupt types? One type of interrupt is available, and an interrupt is generated when the interval time that is set using the interval selection bit (TBCR.TBC[2:0]) has elapsed. (Selection is unnecessary.) 7.8 How is an interrupt enabled? Interrupt request enable and interrupt request flag Setting interrupt enable is conducted using the interrupt request enable bit (TBCR.TBIE).
Page 287: Caution
8. Caution • The main PLL needs the PLL lock wait time after operation enable and after modifying the rate of multiply. We recommend that this main PLL lock wait time be acquired using the timebase interrupt. The lockup time of PLL is approximately 600us. Make sure that the PLL lock wait time is set to a value a little larger than 600us.
Page 288 Chapter 19 Timebase Timer 8.Caution...
Page 289: Chapter 20 Software Watchdog Timer
Chapter 20 Software Watchdog Timer 1. Overview The software watchdog timer consists of a selector that uses the output from a 26-bit timebase counter using the base clock (F) and a one-bit counter. The watchdog timer generates the watchdog reset (initial setting reset) if the generation delay operation (an interval watchdog reset) is disabled due to problems such as program runaway.
Page 290: Configuration
Chapter 20 Software Watchdog Timer 3.Conﬁguration 3. Configuration Timebase counter (26-bit counter) 13 14 15 16 17 18 19 20 21 22 23 24 25 Base clock (φ) Watchdog timer Timer clear CT BR CT BR Clears the counter after writing “A5h” and then “5Ah”.
Page 291: Register
4. Register 4.1 RSRR: Watchdog Timer Control Register This register is used to set watchdog timer periods, and execute the startup control. (This register also functions as the reset cause register that stores previously generated reset causes.) Note: Refer also to “Chapter 9 Reset (Page •...
Page 292 Chapter 20 Software Watchdog Timer 4.Register RST has been triggered by a software reset. The software reset occurred flag (SRST) is cleared to “0” after reading. • Bit2: Low voltage reset occurred flag Indicates whether a reset (INIT) was triggered by the low voltage detection. LINIT No INIT has been triggered by the low voltage detection.
Page 293 4.2 WPR: Watchdog Reset Generation Postponement Register This register is used to postpone the generation of watchdog reset. • WPR: Address 0485h (Access: Byte) RX,W RX,W RX,W (Refer to “Meaning of Bit Attribute Symbols (Page • If “A5 ” and “5A ”...
Page 294: Operation
Chapter 20 Software Watchdog Timer 5.Operation 5. Operation This section describes the watchdog operation. 5.1 Watchdog (Detecting Runaway) Count value of the timer counter Interval period selection Bit output of the timer counter (Bits 15, 17, 19 and 21) Watchdog Watchdog timer startup Reading from the RSRR...
Page 295 5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period The watchdog timer starts once it first writes data to the RSRR (Reset cause register/Watchdog timer control register) after the reset (RST). At this time, Bits 1 and 0 (WT1 and WT0 bits) set the watchdog timer interval time.
Page 296: Setting
Chapter 20 Software Watchdog Timer 6.Setting 6. Setting Table 6-1 Setting Required for Using the Watchdog Timer Setting Interval time setting Startup of the watchdog *: Refer to the number for more information on the setting method. Table 6-2 Setting Required for Delaying the Generation of the Watchdog Setting Setting required for delay the generation of the watchdog reset...
Page 297 7. Q & A 7.1 What are the types of watchdog interval time and how are they selected? There are four types of the interval period, and they are set using the interval selection bit (RSRR.WT[1:0]). Watchdog Interval time To select Φ × 2 To select Φ...
Page 298: Caution
Chapter 20 Software Watchdog Timer 8.Caution 8. Caution • Although the watchdog interval time corresponds to the one twice as long as the watchdog 1-bit counter, the watchdog timer clear operation only clears the 1-bit counter used for detecting the watchdog. As a result, the time margin to clear the watchdog timer is different from the interval time.
Page 299: Chapter 21 Hardware Watchdog Timer
Chapter 21 Hardware Watchdog Timer 1. Overview The hardware watchdog timer (R/C oscillation based) provides a system reset if an internal watchdog timer is not cleared within the postponement duration. ● Hardware watchdog timer This watchdog timer starts counting after the setting initialization reset (INIT) automatically. Clearing the counter in the postponement duration is necessary to continue running an application.
Page 300: Configuration
Chapter 21 Hardware Watchdog Timer 2.Conﬁguration 2. Configuration Hardware watchdog timer consists of two sub-blocks: • Watchdog timer • Timer control and status register ● Block diagram of the hardware watchdog timer Figure 2-1 Block Diagram of hardware watchdog timer Watchdog timer This is a timer to supervise CPU operation.
Page 301: Register
3. Register 3.1 Hardware watchdog timer control and status register Hardware watchdog timer control status register (with reset flag and clear bit). • HWWD: Address 04C7h (Access: Byte) RESV0 RESV0 RESV0 R/W0 R/W0 R/W0 (See “Meaning of Bit Attribute Symbols (Page •...
Page 302 Chapter 21 Hardware Watchdog Timer 3.Register 3.2 Hardware watchdog timer duration register Hardware watchdog timer duration register (elongation of the trigger duration). • HWWDE: Address 04C6h (Access: Byte) RX/W0 RX/W0 RX/W0 (See “Meaning of Bit Attribute Symbols (Page • Bit7-2: Reserved bits. Always write “0” to these bits. •...
Page 303: Functions
4. Functions If the watchdog timer is not cleared periodically, a setting initialization reset (INIT) occurs. In this case the value of registers in CPU is not guaranteed. ● Function of the hardware watchdog timer After releasing INITX the hardware watchdog timer starts immediately without stabilization time. If the timer is not cleared periodically, setting initialization (INIT) reset occurs.
Page 304: Caution
Chapter 21 Hardware Watchdog Timer 5.Caution 5. Caution ● Software disabling is not possible The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop the counting. ● Hardware disabling is only possible on the evaluation device MB91V460 The watchdog timer can be permanently disabled by setting the corresponding jumper of the evaluation board (this is not possible on flash devices with this watchdog timer).
Page 305: Chapter 22 Main Oscillation Stabilisation Timer
Chapter 22 Main Oscillation Stabilisation Timer 1. Overview The main clock oscillation stabilisation timer is a 23-bit counter that counts the main clock. This timer does not affect the selection of clock source operated by MCU/dividing setting. This timer is mainly used for acquiring main clock oscillation stability wait time to resume main clock oscillation after the main clock oscillation has been stopped (OSCCR.OSCDS1=1) while the subclock is being operated.
Page 306: Configuration
Chapter 22 Main Oscillation Stabilisation Timer 3.Conﬁguration 3. Configuration Main clock oscillation stability wait timer Timer operation enable OSCR:bit 5 Operation stop Operation enable 23-bit free run timer Main clock (Source oscillation) Timer clear OSCR:bit 2 Timer clear Does not affect the operation Note: Refer to “Chapter 24 Interrupt Control (Page Figure 3-1 Conﬁguration Diagram...
Page 307: Register
4. Register 4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer This register is used to select the interval time, clear the timer, control the interrupt, control the timer such as stop, and confirm the state of the timer. •...
Page 308: Operation
Chapter 22 Main Oscillation Stabilisation Timer 5.Operation 5. Operation This section describes the main clock oscillation stability wait timer operation. 5.1 Main Clock Oscillation Stability Wait (1) Selects the interval time. (WS[1:0]) (In this example, 2 (2) Sets timer clear (WCL=“0”) by the software. (3) Sets flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software.
Page 309 Chapter 22 Main Oscillation Stabilisation Timer 5.Operation 5.2 Interval Interrupt (1) Selects the interval time (WS[1:0]). (In this example, 2 is selected.) CL-MAIC (2) Clears the timer (WCL=“0”), clears flags (WIF=“0”), enables interrupt request (WIE=“1”), enables timer count (WEN=“1”) by the software. (3) The timer counts up using the main clock (source oscillation).
Page 310: Setting
Chapter 22 Main Oscillation Stabilisation Timer 6.Setting 6. Setting Figure 6-1 Settings Required for Using the Main Clock Oscillation Stability Wait Timer Setting Setting interval time Count clear Counting operation start *: Refer to the number for more information on the setting method. Figure 6-2 Settings Required for Enabling the Main Clock Oscillation Stability Wait Timer Interrupt Setting Sets the main clock oscillation stability wait timer...
Page 311 7. Q & A 7.1 What are the types of interval time (wait time) and how are they selected? There are 3 types of interval time, and they are set with the interval selection bit (OSCRH.WS[0:1]). Interval time To set the value to 2 CL-MAIN To set the value to 2 CL-MAIN...
Page 312 Chapter 22 Main Oscillation Stabilisation Timer 7.Q & A 7.6 What are the types of interrupt? There is one type of interrupt called the main clock oscillation stability wait timer interrupt. (Selection is unnecessary.) 7.7 how is an interrupt enabled? Interrupt request enable and interrupt request flag Setting the interrupt enable is performed with the interrupt request enable bit (OSCRH.WIE).
Page 313: Caution
8. Caution • To wait until the main clock oscillation stability is attained while the subclock is in operation, it is necessary to acquire wait time using the main clock oscillation stability wait timer. (An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the MCU operation mode is switched from the sub-RUN to the main RUN mode without waiting until the main clock oscillation becomes stable.) •...
Page 314 Chapter 22 Main Oscillation Stabilisation Timer 8.Caution...
Page 315: Chapter 23 Sub Oscillation Stabilisation Timer
Chapter 23 Sub Oscillation Stabilisation Timer 1. Overview The sub oscillation stabilisation timer is a 15-bit counter that is counted up with the subclock. This timer does not affect the selection/dividing setting of the MCU operating clock. This timer is used to acquire subclock oscillation stability wait time if the subclock oscillation is resumed mainly when the subclock oscillation is stopped while the main clock is in operation.
Page 316: Configuration
Chapter 23 Sub Oscillation Stabilisation Timer 3.Conﬁguration 3. Configuration Clock timer Clock timer (14-bit free run timer) Sub-clock (Source oscillation) 32.768 kHz Timer clear WPCR:bit 2 Timer clear Does not affect the operation Note: For the ICR register and interrupt vector, refer to Figure 3-1 Conﬁguration Diagram Interval time WS1-0...
Page 317: Register
4. Register 4.1 WPCRH: Sub oscillation stabilisation timer Control Register This register is used to select interval time, clear the timer, control interrupt, control timer stop etc., and confirm the states. • WPCRH: Address 04CAh (Access: Byte) R(RM1),W (For the attributes, refer to “Meaning of Bit Attribute Symbols (Page (Refer to “8.
Page 318 Chapter 23 Sub Oscillation Stabilisation Timer 4.Register watchdog reset), but the operation initialization reset (Software reset) holds the current value instead of initializing it. 2: If you set the interrupt request enable (WIE=“1”), and the interval period selection (WS[1:0]) after canceling the reset, be sure to simultaneously set the timer interrupt request flag (WIF) and the timer clear (WCL) “0”.
Page 319: Operation
5. Operation 5.1 Subclock Oscillation Stability Wait Interrupt Subclock oscillation example Clock timer counting 0400h 0000h (Bit 9) Subclock stop bit Operation clock mode (1) Selects the interval (WS[1:0]) (In this example, 2 (2) Sets the timer so that it is cleared (WCL=“0”) by software. (3) Sets the flag clear (WIF=“0”) and the interrupt request enable (WIE=“1”) by software.
Page 320 Chapter 23 Sub Oscillation Stabilisation Timer 5.Operation 5.2 Interval Interrupt (Clock Interrupt) Clock timer counting 4000h 2000h 0000h (Bit12) (1) Selects the interval time. (WS[1:0]) (In this example, 2 (2) Sets the timer clear (WCL=“0”), flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software. (3) The timer counts up with the subclock (Source oscillation).
Page 321 5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt) Clock timer counting 7FFFh 4000h 0000h (Bit 13) Interval time Main Sub- MCU state (1) The sub oscillation stabilisation timer is cleared by software. (Writes “0” to WCL.) (2) Counts up the sub oscillation stabilisation timer with the subclock.
Page 322: Setting
Chapter 23 Sub Oscillation Stabilisation Timer 6.Setting 6. Setting Table 6-1 Settings Required for Using the Sub oscillation stabilisation timer Setting Setting the interval time Count clear *: Refer to the number for more information on the setting method. Table 6-2 Items Required for Enabling the Sub oscillation stabilisation timer Interrupt Setting Setting the interrupt vector and the free run timer level of the sub oscillation stabilisation timer...
Page 323 7. Q & A 7.1 What are the types of interval time (wait time) and how are they selected? There are three types of interval time, and they are set with the interval selection bit (WPCRH.WS[1:0]). Interval time To set the interval time to CL-SUB To set the interval time to CL-SUB...
Page 324 Chapter 23 Sub Oscillation Stabilisation Timer 7.Q & A 7.6 How is the interrupt enabled? The interrupt request enable and the interrupt request flag The interrupt enable is set with the interrupt request enable bit (WPCRH.WIE). Interrupt disable Interrupt enable The interrupt request is cleared with the interrupt request bit (WPCRH.WIF).
Page 325: Caution
8. Caution • If the setting request (WIF=“1”) of the timer interrupt request flag and the writing timing where “0” is written to the flag by the software occur simultaneously, the flag is set to “1”. • If the interrupt request is enabled (WIE=“1”) after defeating a reset, and if the interval time is changed, be sure to simultaneously set “0”...
Page 326 Chapter 23 Sub Oscillation Stabilisation Timer 8.Caution...
Page 327: Chapter 24 Interrupt Control
Chapter 24 Interrupt Control 1. Overview Interrupt control manages interrupt reception and arbitration. Priority judging circuit NMI processing Interrupt priority Interrupt requests judging circuit (peripheral function, INT instruction, and delayed interrupt) 2. Features • Functions • Detection of interrupt requests •...
Page 328: Configuration
Chapter 24 Interrupt Control 3.Conﬁguration 3. Configuration The enabled interrupt request Interrupt request enable bit Interrupt Interrupt request cause flag External interrupt ( 16) Reload timer ( 4) UART receive ( 4) UART transmit ( 4) A/D ( 2) Real-time clock ( 1) Main clock oscillation Interrupt control register stabilization timer ( 1)
Page 329: Registers
4. Registers 4.1 ICR: Interrupt Control Register The register that specifies the interrupt level of an interrupt request. External Interrupt 0 ICR00 External Interrupt 1 External Interrupt 2 ICR01 External Interrupt 3 External Interrupt 4 ICR02 External Interrupt 5 External Interrupt 6 ICR03 External Interrupt 7 External Interrupt 8...
Page 330 Chapter 24 Interrupt Control 4.Registers I2C 0 / I2C 2 ICR29 I2C 1 / I2C 3 USART (LIN) 8 RX ICR30 USART (LIN) 8 TX USART (LIN) 9 RX ICR31 USART (LIN) 9 TX USART (LIN) 10 RX ICR32 USART (LIN) 10 TX USART (LIN) 11 RX ICR33 USART (LIN) 11 TX...
Page 331 #138 Low Voltage Detection ICR61 #139 SMC Comparator 0-5 #140 Timebase Overﬂow ICR62 #141 PLL Clock Gear #142 DMA Controller ICR63 #143 Main/Sub OSC stability wait (*1) : Used by REALOS (*2): ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0]) Chapter 24 Interrupt Control : Address 047D (Access: Byte)
Page 332 Chapter 24 Interrupt Control 4.Registers ICR (Interrupt Control Register) is a register in the interrupt controller, and it specifies the interrupt level for each interrupt request. ICR corresponds to each of interrupt request input. ICR is mapped to the I/O space. •...
Page 333: Interrupt Vector
4.2 Interrupt Vector Interrupt vector that corresponds to a vector number (#) with TBR register set to 0FFC00h (initial value): : Address : Address : Address : Address #143 : Address • Set the address of each interruption handling routine to the corresponding vector. •...
Page 334: Operation
Chapter 24 Interrupt Control 5.Operation 5. Operation The following section explains priority determination operation of interrupt control. The Flow of the Interrupt Process Interrupt cause generated The interrupt request flag is set to “1”. Are interrupt requests enabled? The interrupt request is transmitted to the interrupt control circuit.
Page 335: Setting
6. Setting Table 6-1 Setting Required to Use Interrupts Setting Setting the interrupt level Clearing the interrupt request ﬂags Enabling interrupt requests I ﬂag setting *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Setting that Requires the Setting within Interrupt Processing Setting Clearing the interrupt request ﬂags 7.
Page 336: Caution
Chapter 24 Interrupt Control 8.Caution 7.4 How can I set an I ﬂag? −>In C: I flag is set to “1” (interrupt enable) by writing __EI();. I flag is set to “0” (interrupt disable) by writing __DI();. 8. Caution Interrupt request flags are not cleared automatically. Make sure to clear them in the interrupt process. (They are usually cleared by writing “0”...
Page 337: Chapter 25 External Interrupt
Chapter 25 External Interrupt 1. Overview External interrupt detects a signal input to an external interrupt input pin, and generates an interrupt request. Pins 2. Features • Quantity : 16 (INT input -- 16 channels: INT0-INT15) • Interrupt levels: 4 levels •...
Page 338: Configuration
Chapter 25 External Interrupt 3.Conﬁguration 3. Configuration External interrupts 0 - 7 Detect level setting LB0, LA0 LB1, LA1 LB2, LA2 LB3, LA3 LB4, LA4 LB5, LA5 LB6, LA6 LB7, LA7 INT0/P24.0 INT1/P24.1 Pins INT2/P24.2 INT3/P24.3 INT4/SDA2/P24.4 INT5/SCL2/P24.5 INT6/SDA3/P24.6 (Inputs of other peripheral INT7/SCL3/P24.7 function macros) P24.0...
Page 339: External Interrupts
Figure 3-2 Conﬁguration Diagram External interrupts 8 - 15 Detect level setting LB8, LA8 ELVR1 : bit 1-0, LB9, LA9 ELVR1 : bit 3-2, LB10, LA10 ELVR1 : bit 5-4, LB11, LA11 ELVR1 : bit 7-6, LB12, LA12 ELVR1 : bit 9-8, LB13, LA13 ELVR1 : bit 11-10, LB14, LA14...
Page 340 Chapter 25 External Interrupt 3.Conﬁguration Figure 3-4 Register List Note: See “Chapter 24 Interrupt Control (Page No.311)” about ICR register and interrupt vectors.
Page 341: Registers
4. Registers 4.1 ELVR: Interrupt Request Level Register The register that selects request detection of external interrupts. • ELVR0 (INT0-INT7): Address 032H (access: Half-word, Word) (About attributes, see “Meaning of Bit Attribute Symbols (Page • ELVR1 (INT8-INT15): Address 036H (access: Half-word, Word) LB15 LA15 LB14...
Page 342 Chapter 25 External Interrupt 4.Registers 4.2 EIRR: Interrupt Request Register Status bit of a request of an external interrupt. • EIRR0 (INT0-INT7): Address 030H (access: Byte, Half-word, Word) R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W (About attributes, see “Meaning of Bit Attribute Symbols (Page •...
Page 343: Operation
5. Operation Level detection “H”) INT ( “L”) Valid edge Interrupt request (ER) Edge detection Internal clock (CLKP divided by two) INT (rising) (fallling) Valid edge Interrupt requests (ER) (1) External interrupt signal (INT) input (2) Detect interrupt signals (level/edge). (3) Valid edge signal (3xCLKP above required) (4) An interrupt request generated.
Page 344: Setting
Chapter 25 External Interrupt 6.Setting 6. Setting Table 6-1 Setting Required in Order to Use External Interrupts Setting Setting of detect level Set INT pin as the input. External interrupt Note: For the setting procedure, refer to the section indicated by the number. 7.
Page 345: Interrupt Types
7.3 What interrupt registers are used? Setting of interrupt vectors of external interrupts, and interrupt levels The relationship among external interrupt numbers, interrupt levels, and vectors is shown in the table below. “Chapter 24 Interrupt Control (Page Interrupt vectors (default) INT0 Address: 0FFFBCh INT1...
Page 346 Chapter 25 External Interrupt 7.Q & A 7.5 How do I enable, disable, and clear interrupts? Enable flag for interrupt requests, interrupt request flag Use interrupt enabling bits (ENIR0.ENx. x = 0-7) and (ENIR1.ENx. x = 8-15) to enable interrupts. To disable interrupt requests To enable interrupt requests Use interrupt request bits (EIRR0.ERx.
Page 347: Caution
8. Caution • When the request input is a level (LAn, LBn = “00” or “01”) and when the INT pin input is the set active level, the corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”. Note: n = 0 to 15 •...
Page 348 Chapter 25 External Interrupt 8.Caution...
Page 349: Chapter 26 Dma Controller
Chapter 26 DMA Controller 1. Overview of the DMA Controller (DMAC) The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various kinds of data can be transferred at high speed by bypassing the CPU, enhancing system performance.
Page 350 Chapter 26 DMA Controller 1.Overview of the DMA Controller (DMAC) ■ Block Diagram Figure 1-1"Block Diagram of the DMA Controller (DMAC)" is a block diagram of the DMA controller (DMAC). Figure 1-1 Block Diagram of the DMA Controller (DMAC) DMA transfer request to the bus controller Read Read/write...
Page 351: Dma Controller (Dmac) Registers
2. DMA Controller (DMAC) Registers This section describes the configuration and functions of the registers used by the DMA control- ler (DMAC). ■ DMA Controller (DMAC) registers Figure 2-1"DMA Controller (DMAC) Registers" shows the registers of the DMA controller (DMAC). (bit) 23 16 15 08 07 00 ch.0...
Page 352 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers If the bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of DMACA=0), the setting takes effect when start is enabled. If the bit is set while DMA transfer is temporarily stopped (DMAH[3:0] of DMACR not equal to 0000 DMACA=1), the setting takes effect when temporary stopping is canceled.
Page 353 [Bit 30] PAUS (PAUSe)*: Temporary stop instruction This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xx If this bit is set before starting, DMA transfer continues to be temporarily stopped.
Page 354 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer source selection These bits select the source of a transfer request note that the software transfer request by the STRG bit function is always valid regardless of the setting of these bits. As listed in Request Sources".
Page 355 Notes: • If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxx the selected peripheral function with the ICR register. • If demand transfer mode is selected, only IS[4:0]=01110 disabled. • External request input is valid only for CH0, 1, and 2. External request input cannot be selected for CH2, CH3 and 4.
Page 356 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers Table 2-2 Settings for Extended Transfer Request Sources 10110 0010 Reload Timer 6 10111 0010 Reload Timer 7 11000 0010 Free Run Timer 0 11001 0010 Free Run Timer 1 11010 0010 Free Run Timer 2 11011 0010...
Page 357 Table 2-2 Settings for Extended Transfer Request Sources 10110 0100 USART (LIN) 11 RX 10111 0100 USART (LIN) 11 TX 11000 0100 USART (LIN) 12 RX 11001 0100 USART (LIN) 12 TX 11010 0100 USART (LIN) 13 RX 11011 0100 USART (LIN) 13 TX 11100 0100...
Page 358 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers Table 2-2 Settings for Extended Transfer Request Sources 10110 0110 Programmable Pulse Generator 6 10111 0110 Programmable Pulse Generator 7 11000 0110 Programmable Pulse Generator 8 11001 0110 Programmable Pulse Generator 9 11010 0110 Programmable Pulse Generator 10...
Page 359 completed. XXXX Transfer count for the corresponding channel When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated transfer counter and is decremented by 1 (subtraction) after each transfer unit. When DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends.
Page 360 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers memory address. Table 2-3 Settings for the Transfer Types TYPE 2-cycle transfer (initial value) Fly-by: Memory --> I/O transfer Fly-by: I/O --> memory transfer Setting disabled • When reset: Initialized to 00 •...
Page 361 [Bits 29, 28] MOD (MODe)*: Transfer mode setting These bits are the transfer mode setting bits and set the operating mode of the corresponding channel. Table 2-4 Settings for Transfer Modes Block/step transfer mode (initial value) Burst transfer mode Demand transfer mode Setting disabled •...
Page 362 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification This bit specifies the address processing of the transfer source address of the corresponding channel in each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer source address count width (SASZ).
Page 363 [Bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification This bit controls reloading of the transfer count register for the corresponding channel. If reload operation is enabled by this bit, the count register value is restored to its initial value after the transfer is completed then DMAC stops and then waiting starts for new transfer requests (an activation request by STRG or IS setting).
Page 364 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification This bit controls reloading of the transfer destination address register for the corresponding channel. If this bit enables reloading, the transfer destination address register value is restored to its initial value after the transfer is completed.
Page 365 [Bits 18 to 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indication These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA transfer on the corresponding channel. For a list of end codes, see Table 2-6 End Codes Initial value Address error (underflow/overflow)
Page 366 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 7 to 0] DASZ (Des Addr count SiZe)*: Transfer destination address count size specification These bits specify the increment or decrement width for the transfer destination address (DMADA) of the corresponding channel in each transfer operation. The value set by these bits becomes the address increment/decrement for each transfer unit.
Page 367 [Bits 31 to 0] DMADA (DMA Destination Addr)*: Transfer destination address setting These bits set the transfer destination address. If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address counter and then the address is calculated according to the settings for the transfer operation. When the DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends.
Page 368 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers DMA operation can be forced to stop by writing 0 to this bit. However, be sure to force stopping (0 write) only after temporarily stopping DMA using the DMAH[3:0] bits [Bit27 to 24 of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMA stops, but the transfer data cannot be guaranteed.
Page 369 Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers ■ Pin Function of the DACK, and DEOP, and DREQ pins To use the DACK, DEOP, or DREQ pins for external transfer, a switch must be made from the port function to the DMA pin function.
Page 370: Dma Controller (Dmac) Operation
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation 3. DMA Controller (DMAC) Operation A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-func- tional DMAC that controls data transfer at high speed without the use of CPU instructions. This section describes the operation of the DMAC.
Page 371 ● Fly-by transfer (I/O --> memory) The DMA controller operates using a write operation as its unit of operation. Otherwise, operation is the same as fly-by transfer (memory --> I/O) operation. Access areas used for MB91460 series fly-by transfer must be external areas. ■...
Page 372 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation • End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end • A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error • An address error occurred => Error •...
Page 373 always be caused. If a software request occurs together with a start (transfer enable) request, the transfer is started by immediate output of a DMA transfer request to the bus controller. 3.2 Transfer Sequence The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently for each channel (Settings for TYPE[1:0] and MOD[1:0] of DMACB).
Page 374 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation Figure 3-1 Example of burst transfer for a start on an external pin rising edge, number of blocks =1, and Transfer request ( edge) Bus operation Transfer count Transfer end ● Burst fly-by transfer A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory -->...
Page 375 Table 3-3 Speciﬁable transfer addresses (demand transfer 2-cycle transfer) Transfer source address External area External area External area Built-in IO Built-in RAM Note: For a demand transfer, be sure to set an external area address for the transfer source or transfer destination or both.
Page 376 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if transfer requests occur simultaneously.
Page 377 ● Transfer count register reloading After transfer is performed the specified number of times, the initial value is set in the transfer count register again and waiting for a start request starts. Set this type of reloading when the entire transfer sequence is to be performed repeatedly. If reload is not specified, the count register value remains 0 after the transfer is performed the specified number of times and no further transfer is performed.
Page 378 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ Features of the Address Register This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed. ■ Function of the Address Register • The address register is read in each access operation and the read value is sent to the address bus.
Page 379 ■ Transfer Count Control Set the transfer count value in the transfer count register (DTC of DMACA). The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the transfer counter. When the counter value becomes 0, end of transfer end for the specified count is detected, and the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified).
Page 380 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation Note: • Since the register has only four bits, this function cannot be used for multiple interrupts exceeding 15 levels. • Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt levels.
Page 381 If edge detection is selected for the external pin start source and a transfer request is detected, the request is retained within DMAC until the clear conditions are met (when the external pin start source is selected for block, step, or burst transfer). If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the transfer until all transfer requests are cleared.
Page 382 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ● Disabling all channels If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations, including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again, no transfer is performed unless a channel is restarted.
Page 383 ■ Occurrence of an Address Error If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error is detected (if an overflow or underflow occurs in the address counter when a 32-bit address is specified). If an address error is detected, "An address error occurred"...
Page 384 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation 3.11 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority Among Channels Since DMA transfer is possible only on one channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (described later).
Page 385 ■ Channel Group The order of priority is set as shown in the following table. MODE Priority Fixed ch0 > ch1 ch0 > ch1 Rotation ch0 < ch1 3.12 Supplement on External Pin and Internal Operation Timing This section provides supplementary information about external pins and internal operation tim- ing.
Page 386 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation Figure 3-7 Negate timing example of the DREQ pin input for 2-cycle external transfer --> internal transfer Bus operation Area External D bus DACK DEOP DREQ (H level) • If the transfer is internal <--> external: Negate before the last sense timing of the clock in the L section of the external WRn pin output when accessing the transfer source for the last DMA transfer (Section of DACK = 1and WRn = L).
Page 387 Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when the DACK pin output is asserted. ■...
Page 388 Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ AC Characteristics of DMAC DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins related to the DMAC,. Output timing is synchronized with external bus access (refer to the AC standard for the DMAC).
Page 389: Operation Flowcharts
4. Operation Flowcharts This section contains operation flowcharts for the following transfer modes: • Block transfer • Burst transfer • Demand transfer ■ Block Transfer Figure 4-1"Operation Flowchart for Block Transfer" shows the flowchart for block transfer. Figure 4-1 Operation Flowchart for Block Transfer DENB=>0 Reload enable Load the initial address,...
Page 390 Chapter 26 DMA Controller 4.Operation Flowcharts Figure 4-2 Operation Flowchart for Burst Transfer DENB=>0 Reload enable Calculate the address for transfer source address access Calculate the address for transfer destination address access Burst transfer - Can be activated by all activation sources (selection). - Can access to all areas.
Page 391 Figure 4-3 Operation Flowchart for Demand Transfer DMA stop DENB=>0 DENB=1 None Activation request wait Reload enable Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access Calculate the address for transfer destination address access Number of transfer - 1 Write back the address,...
Page 392: Data Bus
Chapter 26 DMA Controller 5.Data Bus 5. Data Bus This section shows the flow of data during 2-cycle transfer and fly-by transfer. ■ Flow of Data During 2-Cycle Transfer Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer. Figure 5-1 Examples of 2-Cycle Transfer (Continued on next page) MB91460 DMAC...
Page 393 MB91460 DMAC Read cycle I-bus Bus controller D-bus Data buffer MB91460 DMAC Read cycle I-bus Bus controller D-bus Data buffer MB91460 DMAC Read cycle I-bus Bus controller D-bus Data buffer ■ Flow of Data During Fly-By Transfer Figure 5-2"Examples of Fly-By Transfer" shows examples of two types of transfer during fly-by transfer. Built-in I/O area =>...
Page 394 Chapter 26 DMA Controller 5.Data Bus MB91460 DMAC Read cycle I-bus Bus controller D-bus Data buffer MB91460 DMAC Read cycle I-bus Bus controller D-bus Data buffer Figure 5-2 Examples of Fly-By Transfer Fly-by transfer (memory to I/O) X-bus F-bus Fly-by transfer (I/O to memory) X-bus F-bus Memory read by RD or CSn...
Page 395: Dma External Interface
6. DMA External Interface This section provides operation timing charts for the DMA external interface. ■ DMA External Interface Pins DMA channels 0-3 have the following DMA-dedicated pins (DREQ, DACK, and DEOP): • DREQ: DMA transfer request input pin for demand transfer. A transfer is requested with an input. •...
Page 396 Chapter 26 DMA Controller 6.DMA External Interface ■ Timing of Demand Transfer For demand transfer, set the DMA start source to level detection. Although there is no rule for starting, synchronize with RD/WRn of the DMA transfer when stopping a transfer. The sense timing is the rise of MCLK in the final external access.
Page 397 Figure 6-3 Timing Chart in 2-Cycle Transfer Mode DQMU/L WR/WRn DACK (AKxx=111 DACK (AKxx=001 DACK (AKxx=010 DACK (AKxx=011 DACK (AKxx=100 DACK (AKxx=101 DACK (AKxx=110 * : AKxx is the setting value in the PFR register that corresponds to the DMA channel. ●...
Page 398 Chapter 26 DMA Controller 6.DMA External Interface...
Page 399: Chapter 27 Delayed Interrupt
Chapter 27 Delayed Interrupt 1. Overview The delayed interrupt, or the delayed interrupt module is used to generate an interrupt used for task switching. Software request 2. Features • Type: Interrupt request bit (There is no interrupt request enable bit) •...
Page 400: Register
Chapter 27 Delayed Interrupt 4.Register 4. Register 4.1 DICR: Delayed Interrupt Control Register This register controls to generate/clear the delayed interrupt. • DICR: Address 0038h (Access: Byte) – – – – – – RX/WX RX/WX RX/WX (Refer to “Meaning of Bit Attribute Symbols (Page •...
Page 401: Setting
6. Setting Table Setting required for the delayed interrupt generation/clear Table 6-1 Setting required for the delay interrupt generation/clear Setting Vector for delay interrupt Delayed interrupt setting. Generating interrupt request/Releasing interrupt request *: Refer to the number for the setting method. 7.
Page 402 Chapter 27 Delayed Interrupt 8.Caution...
Page 403: Chapter 28 Bit Search
Chapter 28 Bit Search 1. Overview The bit search module is used to detect 0, 1 or changing position for data written in specific registers. 0-position register 1-position register Changing-pos. register 2. Features • Function: Detects the first changing position by scanning data written in data register from MSB to LSB. •...
Page 404: Configuration
Chapter 28 Bit Search 3.Conﬁguration 3. Configuration Bit search Address decoder 0-/1-/Changing-position-detection data register Write only BSD0/ BSD1/ BSDC Run only Detection data (BSD1) Bit search Figure 3-1 Conﬁguration Diagram Detection mode selection Lowest four bits Operation selection of the address for BSD0/BSD1/BSDC 0-detection 0000...
Page 405: Register
4. Register 4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing position Detection Data Register This is a register for setting the bit search detection data. • BSD0: Address 03F0 (Access: Word) • BSD1: Address 03F4 (Access: Word) •...
Page 406 Chapter 28 Bit Search 4.Register 4.2 BSRR: Detection Result Register This register is used to read a bit search result. • BSRR: Address 03FC (Access: Word) (For the attributes, refer to “Meaning of Bit Attribute Symbols (Page • Detection result for data written in the 0 detection register BSD0, the 1-detection register BSD1 and the changing-position-detection register BSDC can be read.
Page 407: Operation
5. Operation 5.1 Zero detection Bit position from MSB Data Scan Detection result (1) Bit position from MSB (2) Written data (Starts to search once data is written.) (3) Detects “0” by scanning from MSB. (4) Detected bit position (5) Detection result If ‘0’...
Page 408 Chapter 28 Bit Search 5.Operation 5.3 Changing Position Detection Bit position from MSB Data Scan Detection result (1) Bit position from MSB (2) Written data (Detection starts once data is written.) (3) Detects the changing position by scanning from MSB. (4) Detected bit position (5) Detection result A value of ‘32’...
Page 409: Setting
6. Setting Table 6-1 Settings Required for “Zero” Position Detection Setting Data write & scan start Converted value read *: For detailed description contents, refer to the reference destination number. Table 6-2 Setting Required for Using “One” Position Detection Setting Data write &...
Page 410 Chapter 28 Bit Search 7.Q & A 7. Q & A 7.1 How is data written? Writes data with the detection data registers (BSD0, BSD1, BSDC). Operation mode “Zero” position detection write “One” position detection write Changing position detection write 7.2 How is scanning started? Scanning is started once data is written in the detection data registers (BSD0, BSD1, BSDC).
Page 411: Caution
8. Caution The following are the remarks on using the bit search module. • The macros are for REALOS(OS), and the user cannot use them when using REALOS. • If the relevant detection is not found, a detection result of 32(decimal), 10(hexadecimal) or 10000(binary) is returned.
Page 412 Chapter 28 Bit Search 8.Caution...
Page 413: Chapter 29 Mpu / Edsu
Chapter 29 MPU / EDSU 1. Overview Memory Protection Unit (MPU) and Embedded Debug Support Unit (EDSU) for MB91460 series. Remark: The MPU/EDSU module features a clock disable function. For enabling the MPU/EDSU module it is necessary to set the EDSUEN bit in the CSCFG register. See chapter tion Register (Page No.196)”...
Page 414: Features
Chapter 29 MPU / EDSU 2.Features 2. Features One Comparator Group offers up to 4 Breakpoints. One Group consists of two full-featured range comparators with the option to use two point registers as mask information. The following features could be partially mixed-up: 4 Instruction Address Breakpoints Up to 4 instruction address breakpoints can be defined.
Page 415: Break Functions
3. Break Functions 3.1 Instruction address break The instruction address point break is the most basic break that occurs when an instruction is fetched at the address specified by the break address data registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to ’00’ provides this mode.
Page 416 Chapter 29 MPU / EDSU 3.Break Functions Break occurs at 0x02345200 to 0x02345300,or at 0x12345200 to 0x12345300,or at 0x22345200 to 0x22345300, etc. The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has oc- cured.
Page 417 Example: BAD0 0x12345200 BAD1 0x12345300 BAD2 0xF0000000 Break occurs at 0x02345200 to 0x02345300,or at 0x12345200 to 0x12345300,or at 0x22345200 to 0x22345300, etc. The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has oc- cured.
Page 418 Chapter 29 MPU / EDSU 3.Break Functions Table 3-3 Operand size and operand address relations Access data Access length address 4n + 0 4n + 1 32 bit 4n + 2 4n + 3 In Operand address break mode the Operand Address, causing the break is captured in the BOAC register. Addi- tional BIAC holds the instruction address of the instruction, which was executed one cycle before the break causing data operation.
Page 419 2) The EDSU data break does not always occur immediately after completion of execution of the instruction causing the break event. 3) Please see also information at chapter Table 3-4 Access data Address set length to BAD3/2 4n + 0 4n + 1 8 bit 4n + 2...
Page 420: Memory Protection
Chapter 29 MPU / EDSU 3.Break Functions On break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operand break exception routine. Table 3-5 Operand address and data value break combinations EP3/2 EP1/0 COMB...
Page 421 Permissions can be set for the comparator channel CMP1 and CMP0 separately, indicated by the symbol index. Table 3-7 Meaning of the permission conﬁg bits Symbol SRX[1:0] SuperVisor Read permission SW[1:0] SuperVisor Write permission URX[1:0] User Read permission UW[1:0] User Write permission At each time an instruction is executed or an operand is accessed, the actual valid permissions were evaluated.
Page 422 Chapter 29 MPU / EDSU 3.Break Functions Break factors and corresponding interrupt numbers and vectors: Table 3-8 Interrupt numbers and vectors of break factors Interrupt CPU supervisor mode (INT #5 instruction) Memory protection exception INTE instruction Instruction break exception Operand break exception Step trace trap NMI interrupt (tool)
Page 423: Registers
4. Registers 4.1 List of EDSU Registers Table 4-1 EDSU Registers Summary Address F000 BCTRL -------- -------- 11111100 00000000 F004 BSTAT -------- -----000 00000000 10--0000 F008 BIAC 00000000 00000000 00000000 00000000 F00C BOAC 00000000 00000000 00000000 00000000 F010 BIRQ 00000000 00000000 00000000 00000000 F014 ...F01F reserved...
Page 424 Chapter 29 MPU / EDSU 4.Registers Table 4-1 EDSU Registers Summary Address F080 BAD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F084 BAD1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F088 BAD2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F08C BAD3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F090 BAD4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F094 BAD5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
Page 425 Table 4-1 EDSU Registers Summary Address F0C0 BAD16 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0C4 BAD17 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0C8 BAD18 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0CC BAD19 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0D0 BAD20 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0D4 BAD21 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0D8 BAD22 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
Page 426 Chapter 29 MPU / EDSU 4.Registers 4.2 Explanations of Registers ● EDSU Control Register (BCTRL) EDSU Control Register byte 2 Address : F002 Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value⇒ EDSU Control Register byte 3 Address : F0 03 Read/write ⇒...
Page 427 BIT[11]: UW - User default Write permission register User is not permitted to write data User is permitted to write data (default) BIT[10]: UX - User default eXecute permission register User is not permitted to execute code User is permitted to execute code (default) CPU and DMA Filter Option Register BIT[9]: FCPU - Filter CPU access Trigger on CPU accesses (default)
Page 428 Chapter 29 MPU / EDSU 4.Registers Enable emulation mode If EEMM is set to ’1’ then the emulation mode is entered during Step Trace Mode and EDSU exceptions Instruction Break, Operand Break and Tool NMI. During emulation mode the Watchdog Timer (WDT) is disabled. EDSU trig- gered emulation mode is left with the RETI instruction.
Page 429 BIT[3]: EINT1 - Enable extended INTerrupt 1 Disable extended interrupt source 1 (default) Enable extended interrupt source 1 If EINT1 is set to ’1’ then a Tool NMI will be generated on an extended interrupt event at source channel 1. Set to ’0’...
Page 430 Chapter 29 MPU / EDSU 4.Registers ● EDSU Status Register (BSTAT) EDSU Status Register byte 2 Address : F006 Read/write ⇒ Default value⇒ EDSU Status Register byte 3 Address : F0 07 Read/write ⇒ Default value⇒ BIT[15:11]: IDX[4:0] - Channel Index Indication of MPUPV Trigger In the case of triggering a memory protection violation (MPUPV), the index of the channel pair 0...15 is saved in The IDX register, which caused the trigger.
Page 431 BIT[9:8]: CSZ[1:0] - Capture Operand Size The operand has a bit size of 8 The operand has a bit size of 16 The operand has a bit size of 32 reserved BIT[7:6]: CRW[1:0] - Capture Operand Access Type The operand has been read The operand has been read by read-modify-write indicated The operand has been written no operand access...
Page 432 Chapter 29 MPU / EDSU 4.Registers BIT[3]: INT1 - INTerrupt on extended source 1 Interrupt on extended source channel 1 not detected (default) Interrupt on extended source channel 1 detected INT1 reflects the status of the extended interrupt source channel 1. It is set to ’1’ if a high level on the extended interrupt signal line has been occured.
Page 433 ● EDSU Instruction Address Capture Register (BIAC) Address F008 00000000 This register captures the address of the instruction (IA), which has caused the protection violation or the operand/ data value break. This register could be read only. ● EDSU Operand Address Capture Register (BOAC) Address F00C 00000000...
Page 434 Chapter 29 MPU / EDSU 4.Registers • operand address break, • data value break, • combined operand address and data value break and • memory protection violation. Writing ’0’ resets the BD[31:0] bits to ’0’. Writing ’1’ to these bits is ignored. On a Read Modify Write instruction all BD bits are read as ’1’.
Page 435 ● EDSU Channel Configuration Register (BCR0...BCR7) EDSU Ch. Config Register 0, byte 0 Address : F020 Read/write ⇒ Default value⇒ EDSU Ch. Config Register 0, byte 1 Address : F0 21 Read/write ⇒ Default value⇒ EDSU Ch. Config Register 0, byte 2 Address : F022 Read/write ⇒...
Page 436 Chapter 29 MPU / EDSU 4.Registers Table 4-3 Relationship of BCR, BAD and BIRQ registers Group Conﬁg Address/Data BCR3 BAD12 BAD13 BAD14 BAD15 BCR4 BAD16 BAD17 BAD18 BAD19 BCR5 BAD20 BAD21 BAD22 BAD23 BCR6 BAD24 BAD25 BAD26 BAD27 BCR7 BAD28 BAD29 BAD30 BAD31...
Page 437 • CTC=2: IA range 0 deﬁnes execute permissions and OA range 1 deﬁnes read/write permissions. Data value (DT) detection by setting CTC=3 is not possible to use in MPU mode. Permission configurations exist for read, write and execute for two CPU modes, the super visor mode and the user mode.
Page 438 Chapter 29 MPU / EDSU 4.Registers BIT[19]: URX1 - User Read/eXecute permission register for range 1 Setting valid for CTC == 0 (Instruction address range comparator): User has no execute permission on address range 1(default) User has execute permission on address range 1 Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator): User has no read permission on address range 1 (default) User has read permission on address range 1...
Page 439 The group of channels operates in memory protection mode Some restrictions apply with the setting of the MPE bit. MPE=0 (break unit): • permission registers are don’t care (BCRx bits [23:16]) MPE=1 (memory protection unit): • OBS and OBT should be set to ’3’ (BCRx bits [11:8], any size and any type) •...
Page 440 Chapter 29 MPU / EDSU 4.Registers The COMB bit set to ’1’ causes the IA comparator CMP0 to use the same BADx point definitions as the OA com- parator CMP1. Point 3 and Point 2 define the address range for both comparators CMP0 and CMP1. This has the effect that the entry of Point 0/Mask 0 is not allocated for the Point set-up and could be used for masking either one or both comparators.
Page 441 Datasize OBS1 OBS0 All (Byte, Hword, Word) The operand break size register OBS configures the datasize and the operand break type register OBT configures the access type if the channel is configured to operand address break or data value break detection. Setting to ’all’...
Page 442 Chapter 29 MPU / EDSU 4.Registers The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep- tion.
Page 443 The selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at least one of both bits are enabled, the mask usage switches to point 2 due to the allocation of point 0. Otherwise the default mask stored in point 0 applies for CMP0.
Page 444 Chapter 29 MPU / EDSU 4.Registers Address F084 XXXXXXXX This register sets the 32 bit comparison value for break point 1 of CMP0. In range mode (set with ER0) the register value of BAD1 functions as upper address limit. In the special case of MPE=1 and COMB=1 BAD1 is not used for the point definition. CMP0 gets its point configu- ration then from BAD3.
Page 445: Quick Reference
Chapter 29 MPU / EDSU 5.Quick Reference 5. Quick Reference Figure 5-1 Register Quick Reference...
Page 446 Chapter 29 MPU / EDSU 5.Quick Reference BCR1 BAD7 BAD6 BAD5 BAD4 BCR0 BAD3 BAD2 BAD1 BAD0 Figure 5-2 Comparator Group Structure (drawn for two groups) OBS−Match Point 3 Point 2 IA/OA Mask 1 CMP1 Value Comparator GROUP 1 Point 1 Point 0 IA/OA/DT Mask 0...
Page 447: Chapter 30 I/O Ports
Chapter 30 I/O Ports 1. I/O Ports Functions For enabling the resource functions, please refer to section ... Circuit Pin Name I/O Signal Type INITX INITX TC02_0 RSTX RSTX TC01_0 HSTX HSTX TC00_0 NMIX NMIX TC01_0 TC02_1 TC02_1 TC02_1 TO00_0 TO00_1 TO01_0 TO01_1...
Page 448 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P00_3 P00_3 TP04_0 P00_2 P00_2 TP04_0 P00_1 P00_1 TP04_0 P00_0 P00_0 TP04_0 P01_7 P01_7 TP04_0 P01_6 P01_6 TP04_0 P01_5 P01_5 TP04_0 P01_4 P01_4 TP04_0 P01_3 P01_3 TP04_0 P01_2 P01_2 TP04_0...
Page 449 Circuit Pin Name I/O Signal Type P01_0 P01_0 TP04_0 P02_7 P02_7 TP04_0 P02_6 P02_6 TP04_0 P02_5 P02_5 TP04_0 P02_4 P02_4 TP04_0 P02_3 P02_3 TP04_0 P02_2 P02_2 TP04_0 P02_1 P02_1 TP04_0 P02_0 P02_0 TP04_0 P03_7 P03_7 TP04_0 P03_6 P03_6 TP04_0 Function General purpose I/O.
Page 450 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P03_5 P03_5 TP04_0 P03_4 P03_4 TP04_0 P03_3 P03_3 TP04_0 P03_2 P03_2 TP04_0 P03_1 P03_1 TP04_0 P03_0 P03_0 TP04_0 P04_7 P04_7 TP04_0 P04_6 P04_6 TP04_0 P04_5 P04_5 TP04_0 P04_4 P04_4 TP04_0...
Page 451 Circuit Pin Name I/O Signal Type P04_2 P04_2 TP04_0 P04_1 P04_1 TP04_0 P04_0 P04_0 TP04_0 P05_7 P05_7 TP04_0 P05_6 P05_6 TP04_0 P05_5 P05_5 TP04_0 P05_4 P05_4 TP04_0 P05_3 P05_3 TP04_0 P05_2 P05_2 TP04_0 P05_1 P05_1 TP04_0 P05_0 P05_0 TP04_0 Function General purpose I/O.
Page 452 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P06_7 P06_7 TP04_0 P06_6 P06_6 TP04_0 P06_5 P06_5 TP04_0 P06_4 P06_4 TP04_0 P06_3 P06_3 TP04_0 P06_2 P06_2 TP04_0 P06_1 P06_1 TP04_0 P06_0 P06_0 TP04_0 P07_7 P07_7 TP04_0 P07_6 P07_6 TP04_0...
Page 453 Circuit Pin Name I/O Signal Type P07_4 P07_4 TP04_0 P07_3 P07_3 TP04_0 P07_2 P07_2 TP04_0 P07_1 P07_1 TP04_0 P07_0 P07_0 TP04_0 P08_7 P08_7 TP04_0 P08_6 P08_6 TP04_0 P08_5 P08_5 TP04_0 BGRNTX P08_4 P08_4 TP04_0 P08_3 P08_3 TP04_0 WRX3 P08_2 P08_2 TP04_0 WRX2 Function...
Page 454 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P08_1 P08_1 TP04_0 WRX1 P08_0 P08_0 TP04_0 WRX0 P09_7 P09_7 TP04_0 CSX7 P09_6 P09_6 TP04_0 CSX6 P09_5 P09_5 TP04_0 CSX5 P09_4 P09_4 TP04_0 CSX4 P09_3 P09_3 TP04_0 CSX3 P09_2 P09_2...
Page 455 Circuit Pin Name I/O Signal Type P10_6 P10_6 TP04_0 MCLKE P10_5 P10_5 MCLKI TP04_0 MCLKI P10_4 P10_4 MCLKO TP04_0 MCLKO P10_3 P10_3 TP04_0 P10_2 P10_2 TP04_0 BAAX P10_1 P10_1 TP04_0 P10_0 P10_0 SYSCLK TP04_0 SYSCLK P11_7 P11_7 TP04_0 P11_6 P11_6 TP04_0 P11_5 P11_5...
Page 456 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P11_0 P11_0 TP04_0 IORDX P12_7 P12_7 TP04_0 DEOP3 P12_6 P12_6 DEOTX3 TP04_0 DEOP3 P12_5 P12_5 TP04_0 DACKX3 P12_4 P12_4 TP04_0 DREQ3 P12_3 P12_3 TP04_0 DEOP2 P12_2 P12_2 DEOTX2 TP04_0 DEOP2...
Page 457 Circuit Pin Name I/O Signal Type P14_7 ICU7 P14_7 TP00_0 TIN7 TTG15/7 P14_6 ICU6 P14_6 TP00_0 TIN6 TTG14/6 P14_5 ICU5 P14_5 TP00_0 TIN5 TTG13/5 P14_4 ICU4 P14_4 TP00_0 TIN4 TTG12/4 P14_3 ICU3 P14_3 TP00_0 TIN3 TTG11/3 P14_2 ICU2 P14_2 TP00_0 TIN2 TTG10/2 P14_1...
Page 458 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P15_5 P15_5 OCU5 TP00_0 TOT5 P15_4 P15_4 OCU4 TP00_0 TOT4 P15_3 P15_3 OCU3 TP00_0 TOT3 P15_2 P15_2 OCU2 TP00_0 TOT2 P15_1 P15_1 OCU1 TP00_0 TOT1 P15_0 P15_0 OCU0 TP00_0 TOT0...
Page 459 Circuit Pin Name I/O Signal Type P17_7 P17_7 TP00_0 PPG7 P17_6 P17_6 TP00_0 PPG6 P17_5 P17_5 TP00_0 PPG5 P17_4 P17_4 TP00_0 PPG4 P17_3 P17_3 TP00_0 PPG3 P17_2 P17_2 TP00_0 PPG2 P17_1 P17_1 TP00_0 PPG1 P17_0 P17_0 TP00_0 PPG0 P18_7 P18_7 TP00_0 P18_6 SCK7...
Page 460 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P19_7 P19_7 TP00_0 P19_6 P19_6 SCK5 TP00_0 P19_5 P19_5 TP00_0 SOT5 P19_4 P19_4 TP00_0 SIN5 P19_3 P19_3 TP00_0 P19_2 P19_2 SCK4 TP00_0 P19_1 P19_1 TP00_0 SOT4 P19_0 P19_0 TP00_0 SIN4...
Page 461 Circuit Pin Name I/O Signal Type P21_7 P21_7 TP00_0 P21_6 P21_6 SCK1 TP00_0 P21_5 P21_5 TP00_0 SOT1 P21_4 P21_4 TP00_0 SIN1 P21_3 P21_3 TP00_0 P21_2 P21_2 SCK0 TP00_0 P21_1 P21_1 TP00_0 SOT0 P21_0 P21_0 TP00_0 SIN0 P22_7 P22_7 TP02_0 SCL1 P22_6 P22_6 SDA1...
Page 462 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P23_7 P23_7 TP00_0 P23_6 P23_6 TP00_0 INT11 P23_5 P23_5 TP00_0 P23_4 P23_4 TP00_0 INT10 P23_3 P23_3 TP00_0 P23_2 P23_2 TP00_0 INT9 P23_1 P23_1 TP00_0 P23_0 P23_0 TP00_0 INT8 P24_7 P24_7...
Page 463 Circuit Pin Name I/O Signal Type P25_7 P25_7 TP05_0 SMC2M5 P25_6 P25_6 TP05_0 SMC2P5 P25_5 P25_5 TP05_0 SMC1M5 P25_4 P25_4 TP05_0 SMC1P5 P25_3 P25_3 TP05_0 SMC2M4 P25_2 P25_2 TP05_0 SMC2P4 P25_1 P25_1 TP05_0 SMC1M4 P25_0 P25_0 TP05_0 SMC1P4 P26_7 P26_7 SMC2M3 TP05_0 AN31...
Page 464 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P26_0 P26_0 SMC1P2 TP05_0 AN24 P27_7 P27_7 SMC2M1 TP05_0 AN23 P27_6 P27_6 SMC2P1 TP05_0 AN22 P27_5 P27_5 SMC1M1 TP05_0 AN21 P27_4 P27_4 SMC1P1 TP05_0 AN20 P27_3 P27_3 SMC2M0 TP05_0 AN19...
Page 465 Circuit Pin Name I/O Signal Type P28_3 P28_3 TP03_0 AN11 P28_2 P28_2 TP03_0 AN10 P28_1 P28_1 TP03_0 P28_0 P28_0 TP03_0 P29_7 P29_7 TP03_0 P29_6 P29_6 TP03_0 P29_5 P29_5 TP03_0 P29_4 P29_4 TP03_0 P29_3 P29_3 TP03_0 P29_2 P29_2 TP03_0 P29_1 P29_1 TP03_0 P29_0 P29_0...
Page 466 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P30_0 P30_0 TP06_0 COM0 P31_7 P31_7 TP06_0 SEG39 P31_6 P31_6 TP06_0 SEG38 P31_5 P31_5 TP06_0 SEG37 P31_4 P31_4 TP06_0 SEG36 P31_3 P31_3 TP06_0 SEG35 P31_2 P31_2 TP06_0 SEG34 P31_1 P31_1...
Page 467 Circuit Pin Name I/O Signal Type P32_0 P32_0 SEG24 TP06_0 SIN14 P33_7 P33_7 TP06_0 SEG23 P33_6 P33_6 SEG22 TP06_0 SCK13 P33_5 P33_5 SEG21 TP06_0 SOT13 P33_4 P33_4 SEG20 TP06_0 SIN13 P33_3 P33_3 TP06_0 SEG19 P33_2 P33_2 SEG18 TP06_0 SCK12 P33_1 P33_1 SEG17 TP06_0...
Page 468 Chapter 30 I/O Ports 1.I/O Ports Functions Circuit Pin Name I/O Signal Type P34_2 P34_2 SEG10 TP06_0 SCK10 P34_1 P34_1 SEG9 TP06_0 SOT10 P34_0 P34_0 SEG8 TP06_0 SIN10 P35_7 P35_7 TP06_0 SEG7 P35_6 P35_6 SEG6 TP06_0 SCK9 P35_5 P35_5 SEG5 TP06_0 SOT9 P35_4...
Page 469: I/O Circuit Types
2. I/O Circuit Types 2.1 I/O Cell List MB91V460 Type Pull Up / Down (50 kOhm) TP00_0 Up/Down switch TP01_0 TP02_0 TP03_0 Up/Down switch TP04_0 Up/Down switch TP05_0 TP06_0 TP07_0 TP08_0 TC00_0 TC01_0 TC02_0 TC02_1 TC10_0 TO00_0 TO00_1 TO01_0 TO01_1 TA02_0 Note: This table shows the I/O cells used for MB91V460.
Page 470: Port Register Settings
Chapter 30 I/O Ports 3.Port Register Settings 3. Port Register Settings 3.1 General Rules For all ports, the following rules are valid: 1. All port inputs are disabled by default to avoid transverse current floating before the ports are configured by software. After configuring each port pin according to its function it is necessary to enable the port inputs with the global port enable (PORTEN.GPORTEN).
Page 471 14.Resource output lines are enabled by setting the corresponding PFR and/or EPFR bit in the port. Details see section Port Function Register Setup on page additionally by setting the SOE bit in the LIN-USART control. 15.Resource bidirectional signals (e.g. SCK of the LIN-USART) are enabled by setting the corresponding PFR and/or EPFR bit in the port.
Page 472 Chapter 30 I/O Ports 3.Port Register Settings 3.2 I/O Port Block Diagram Port Bus PILR EPILR PDRD read PDR read PPER PPCR 1. Peripheral output 2. Peripheral output EPFR PODR PDR: Port Data Register PDRD: Port Data Direct Register DDR: Data Direction Register PFR: Port Function Register...
Page 473 3.3 Port Input Enable This section describes the Port Input Enable function. ■ PORTEN: Port Input Enable. Addr PORTEN 0498h All port inputs are disabled by default to avoid transverse current floating in the IO input stages and the subsequent logic. After configuring all ports according to their functional specification (input level, output drive, pull-up or pull-down resistor, etc.) it is mandatory to globally enable the inputs by setting the port input enable bit.
Page 474 Chapter 30 I/O Ports 3.Port Register Settings 3.4 Port Function Register Setup This section describes the Port Function Registers of each port. ■ P00: The functions of Port 00 are controlled by PFR00 Addr PFR00 0D80h PFR00.7 EPFR00 0DC0h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P00[7:0] is input/output for data lines D[31:24].
Page 475 ■ P01: The functions of Port 01 are controlled by PFR01 Addr PFR01 0D81h PFR01.7 EPFR01 0DC1h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P01[7:0] is input/output for data lines D[23:16]. Otherwise, the port can be used as general purpose port. PFR01.7 0 - Port is in general purpose port mode.
Page 476 Chapter 30 I/O Ports 3.Port Register Settings ■ P02: The functions of Port 02 are controlled by PFR02 Addr PFR02 0D82h PFR02.7 EPFR02 0DC2h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P02[7:0] is input/output for data lines D[15:8].
Page 477 ■ P03: The functions of Port 03 are controlled by PFR03 Addr PFR03 0D83h PFR03.7 EPFR03 0DC3h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P03[7:0] is input/output for data lines D[7:0]. Otherwise, the port can be used as general purpose port. PFR03.7 0 - Port is in general purpose port mode.
Page 478 Chapter 30 I/O Ports 3.Port Register Settings ■ P04: The functions of Port 04 are controlled by PFR04 Addr PFR04 0D84h PFR04.7 EPFR04 0DC4h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P04[7:0] is input/output for address lines A[31:24].
Page 479 ■ P05: The functions of Port 05 are controlled by PFR05 Addr PFR05 0D85h PFR05.7 EPFR05 0DC5h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P05[7:0] is input/output for address lines A[23:16]. Otherwise, the port can be used as general purpose port. PFR05.7 0 - Port is in general purpose port mode.
Page 480 Chapter 30 I/O Ports 3.Port Register Settings ■ P06: The functions of Port 06 are controlled by PFR06 Addr PFR06 0D86h PFR06.7 EPFR06 0DC6h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P06[7:0] is input/output for address lines A[15:8].
Page 481 ■ P07: The functions of Port 07 are controlled by PFR07 Addr PFR07 0D87h PFR07.7 EPFR07 0DC7h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P07[7:0] is input/output for address lines A[7:0]. Otherwise, the port can be used as general purpose port. PFR07.7 0 - Port is in general purpose port mode.
Page 482 Chapter 30 I/O Ports 3.Port Register Settings ■ P08: The functions of Port 08 are controlled by PFR08 Addr PFR08 0D88h PFR08.7 EPFR08 0DC8h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P08[7:0] is input/output for external bus control signals RDY, BRQ, BGRNTX, RDX, WRX[3:0].
Page 483 ■ P09: The functions of Port 09 are controlled by PFR09 Addr PFR09 0D89h PFR09.7 EPFR09 0DC9h If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P09[7:0] is input/output for external bus control signals CSX[7:0]. Otherwise, the port can be used as general purpose port. PFR09.7 0 - Port is in general purpose port mode.
Page 484 Chapter 30 I/O Ports 3.Port Register Settings ■ P10: The functions of Port 10 are controlled by PFR10 and EPFR10 Addr PFR10 0D8Ah EPFR10 0DCAh If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P10[7:0] is input/output for external bus control signals MCLKE, MCLKI, MCLKO, WEX, BAAX, ASX, SYSCLK.
Page 485 ■ P11: The functions of Port 11 are controlled by PFR11 Addr PFR11 0D8Bh EPFR11 0DCBh P11[7:0] is input/output for DMA control signals IOWRX, IORDX. Otherwise, the port can be used as general purpose port. PFR11.1 0 - Port is in general purpose port mode. 1 - Port is in DMA function mode: DMA function is IOWRX output PFR11.0...
Page 486 Chapter 30 I/O Ports 3.Port Register Settings ■ P12: The functions of Port 12 are controlled by PFR12 and EPFR12 Addr PFR12 0D8Ch PFR12.7 EPFR12 0DCCh P12[7:0] is input/output for DMA control signals DEOP, DEOTX, DACKX, DREQ for DMA channels 2 and 3. Otherwise, the port can be used as general purpose port.
Page 487 ■ P13: The functions of Port 13 are controlled by PFR13 and EPFR13 Addr PFR13 0D8Dh PFR13.7 EPFR13 0DCDh P13[7:0] is input/output for DMA control signals DEOP, DEOTX, DACKX, DREQ for DMA channels 0 and 1. Otherwise, the port can be used as general purpose port. PFR13.7 0 - Port is in general purpose port mode.
Page 488 Chapter 30 I/O Ports 3.Port Register Settings ■ P14: The functions of Port 14 are controlled by PFR14 and EPFR14 Addr PFR14 0D8Eh PFR14.7 EPFR14 0DCEh EPFR14.7 EPFR14.6 EPFR14.5 EPFR14.4 EPFR14.3 EPFR14.2 EPFR14.1 EPFR14.0 P14[7:0] is input/output for Input Capture inputs ICU[7:0], Reload Timer triggers TIN[7:0] and PWM inputs TTG[15:0].
Page 489 Resource function is TIN1 and TTG9/1 input, and EPFR14.1 0 - Resource function is ICU1 input 1 - ICU1 is internally connected to LSYN of LIN-UART 1/9 PFR14.0 0 - Port is in general purpose port mode. 1 - Port is in resource function mode: Resource function is TIN0 and TTG8/0 input, and EPFR14.0 0 - Resource function is ICU0 input 1 - ICU0 is internally connected to LSYN of LIN-UART 0/8...
Page 490 Chapter 30 I/O Ports 3.Port Register Settings ■ P15: The functions of Port 15 are controlled by PFR15 and EPFR15 Addr PFR15 0D8Fh PFR15.7 EPFR15 0DCFh EPFR15.7 EPFR15.6 EPFR15.5 EPFR15.4 EPFR15.3 EPFR15.2 EPFR15.1 EPFR15.0 P15[7:0] is input/output for Output Compare outputs OCU[7:0] and Reload Timer outputs TOT[7:0]. Otherwise, the port can be used as general purpose port.
Page 491 ■ P16: The functions of Port 16 are controlled by PFR16 and EPFR16 Addr PFR16 0D90h PFR16.7 EPFR16 0DD0h EPFR16.7 EPFR16.6 EPFR16.5 EPFR16.4 P16[7:0] is input/output for Programmable Pulse Generator outputs PPG[15:8], external ADC trigger ATGX, Pulse Frequency Modulator output PFM, and Sound Generator outputs SGO/SGA. Otherwise, the port can be used as general purpose port.
Page 492 Chapter 30 I/O Ports 3.Port Register Settings ■ P17: The functions of Port 17 are controlled by PFR17 Addr PFR17 0D91h PFR17.7 EPFR17 0DD1h P17[7:0] is input/output for Programmable Pulse Generator outputs PPG[15:8]. Otherwise, the port can be used as general purpose port. PFR17.7 0 - Port is in general purpose port mode.
Page 493 ■ P18: The functions of Port 18 are controlled by PFR18 and EPFR18 Addr PFR18 0D92h EPFR18 0DD2h P18[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 6 and 7, Up-/ Down-Counter inputs ZIN, BIN, AIN of channels 2 and 3, and Free Run Timer FRT inputs CK of channels 6 and 7.
Page 494 Chapter 30 I/O Ports 3.Port Register Settings ■ P19: The functions of Port 19 are controlled by PFR19 and EPFR19 Addr PFR19 0D93h EPFR19 0DD3h P19[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 4 and 5, and Free Run Timer FRT inputs CK of channels 4 and 5.
Page 495 ■ P20: The functions of Port 20 are controlled by PFR20 and EPFR20 Addr PFR20 0D94h EPFR20 0DD4h P20[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 2 and 3, Up-/ Down-Counter inputs ZIN, BIN, AIN of channels 0 and 1, and Free Run Timer FRT inputs CK of channels 2 and 3.
Page 496 Chapter 30 I/O Ports 3.Port Register Settings ■ P21: The functions of Port 21 are controlled by PFR21 and EPFR21 Addr PFR21 0D95h EPFR21 0DD5h P21[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 0 and 1, and Free Run Timer FRT inputs CK of channels 0 and 1.
Page 497 ■ P22: The functions of Port 22 are controlled by PFR22 Addr PFR22 0D96h PFR22.7 EPFR22 0DD6h P22[7:0] is input/output for I2C serial communication signals SCL, SDA of channels 0 and 1, CAN serial communication signals TX, RX of channels 4 and 5, and External Interrupt Triggers INT[15:12]. Otherwise, the port can be used as general purpose port.
Page 498 Chapter 30 I/O Ports 3.Port Register Settings Resource function is RX4 input, and INT12 input Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and interrupt is enabled with ENIR1.EN12 set to ‘1’.
Page 499 ■ P23: The functions of Port 23 are controlled by PFR23 Addr PFR23 0D97h PFR23.7 EPFR23 0DD7h P23[7:0] is input/output for CAN serial communication signals TX, RX of channels 0 to 3, and External Interrupt Triggers INT[11:8]. Otherwise, the port can be used as general purpose port. PFR23.7 0 - Port is in general purpose port mode.
Page 500 Chapter 30 I/O Ports 3.Port Register Settings Resource function is RX0 input, and INT8 input Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and interrupt is enabled with ENIR1.EN8 set to ‘1’.
Page 501 ■ P24: The functions of Port 24 are controlled by PFR24 Addr PFR24 0D98h PFR24.7 EPFR24 0DD8h P24[7:0] is input/output for I2C serial communication signals SCL, SDA of channels 2 and 3, and External Interrupt Triggers INT[7:0]. Otherwise, the port can be used as general purpose port. PFR24.7 0 - Port is in general purpose port mode.
Page 502 Chapter 30 I/O Ports 3.Port Register Settings Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and interrupt is enabled with ENIR0.EN2 set to ‘1’.
Page 503 ■ P25: The functions of Port 25 are controlled by PFR25 Addr PFR25 0D99h PFR25.7 EPFR25 0DD9h P25[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P, SMC1M, SMC1P of channels 4 and 5. Otherwise, the port can be used as general purpose port. PFR25.7 0 - Port is in general purpose port mode.
Page 504 Chapter 30 I/O Ports 3.Port Register Settings ■ P26: The functions of Port 26 are controlled by PFR26 and EPFR26 Addr PFR26 0D9Ah PFR26.7 EPFR26 0DDAh EPFR26.7 EPFR26.6 EPFR26.5 EPFR26.4 EPFR26.3 EPFR26.2 EPFR26.1 EPFR26.0 P26[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P, SMC1M, SMC1P of channels 2 and 3, and A/D converter analogue inputs AN[31:24].
Page 505 ■ P27: The functions of Port 27 are controlled by PFR27 and EPFR27 Addr PFR27 0D9Bh PFR27.7 EPFR27 0DDBh EPFR27.7 EPFR27.6 EPFR27.5 EPFR27.4 EPFR27.3 EPFR27.2 EPFR27.1 EPFR27.0 P27[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P, SMC1M, SMC1P of channels 0 and 1, and A/D converter analogue inputs AN[23:16].
Page 506 Chapter 30 I/O Ports 3.Port Register Settings ■ P28: The functions of Port 28 are controlled by PFR28 Addr PFR28 0D9Ch PFR28.7 EPFR28 0DDCh P28[7:0] is input/output for A/D converter analogue inputs AN[15:8], and D/A converter analogue outputs DA[1:0]. Otherwise, the port can be used as general purpose port. PFR28.7 0 - Port is in general purpose port mode.
Page 507 ■ P29: The functions of Port 29 are controlled by PFR29 Addr PFR29 0D9Dh PFR29.7 EPFR29 0DDDh P29[7:0] is input/output for A/D converter analogue inputs AN[7:0]. Otherwise, the port can be used as general purpose port. PFR29.7 0 - Port is in general purpose port mode. 1 - Port is in resource function mode: Resource function is AN7 input PFR29.6...
Page 508 Chapter 30 I/O Ports 3.Port Register Settings ■ P30: The functions of Port 30 are controlled by PFR30 Addr PFR30 0D9Eh PFR30.7 EPFR30 0DDEh P30[7:0] is input/output for LCD controller reference voltage analogue inputs V[3:0], and LCD controller common driver outputs COM[3:0]. Otherwise, the port can be used as general purpose port. PFR30.7 0 - Port is in general purpose port mode.
Page 509 ■ P31: The functions of Port 31 are controlled by PFR31 Addr PFR31 0D9Fh PFR31.7 EPFR31 0DDFh P31[7:0] is input/output for LCD controller segment driver outputs SEG[39:32]. Otherwise, the port can be used as general purpose port. PFR31.7 0 - Port is in general purpose port mode. 1 - Port is in resource function mode: Resource function is SEG39 output PFR31.6...
Page 510 Chapter 30 I/O Ports 3.Port Register Settings ■ P32: The functions of Port 32 are controlled by PFR32 and EPFR32 Addr PFR32 0DA0h PFR32.7 EPFR32 0DE0h P32[7:0] is input/output for LCD controller segment driver outputs SEG[31:24], and LIN-UART serial communication signals SCK, SOT, SIN of channels 14 and 15. Otherwise, the port can be used as general purpose port.
Page 511 ■ P33: The functions of Port 33 are controlled by PFR33 and EPFR33 Addr PFR33 0DA1h PFR33.7 EPFR33 0DE1h P33[7:0] is input/output for LCD controller segment driver outputs SEG[23:16], and LIN-UART serial communication signals SCK, SOT, SIN of channels 12 and 13. Otherwise, the port can be used as general purpose port.
Page 512 Chapter 30 I/O Ports 3.Port Register Settings ■ P34: The functions of Port 34 are controlled by PFR34 and EPFR34 Addr PFR34 0DA2h PFR34.7 EPFR34 0DE2h P34[7:0] is input/output for LCD controller segment driver outputs SEG[15:8], and LIN-UART serial communication signals SCK, SOT, SIN of channels 10 and 11. Otherwise, the port can be used as general purpose port.
Page 513 ■ P35: The functions of Port 35 are controlled by PFR35 and EPFR35 Addr PFR35 0DA3h PFR35.7 EPFR35 0DE3h P35[7:0] is input/output for LCD controller segment driver outputs SEG[7:0], and LIN-UART serial communication signals SCK, SOT, SIN of channels 8 and 9. Otherwise, the port can be used as general purpose port.
Page 514 Chapter 30 I/O Ports 3.Port Register Settings 3.5 Port Input Level Selection The input levels of each port can be programmed bit-wise between CMOS Hysteresis type A and B, Automotive Hysteresis and TTL level. CMOS Hysteresis type A: CMOS Hysteresis type B: Automotive Hysteresis: For setup, the Port Input Level Registers (PILR, EPILR) of each port are used.
Page 515 PILR20 0E54h PILR20.7 PILR20.6 PILR21 0E55h PILR21.7 PILR21.6 PILR22 0E56h PILR22.7 PILR22.6 PILR23 0E57h PILR23.7 PILR23.6 PILR24 0E58h PILR24.7 PILR24.6 PILR25 0E59h PILR25.7 PILR25.6 PILR26 0E5Ah PILR26.7 PILR26.6 PILR27 0E5Bh PILR27.7 PILR27.6 PILR28 0E5Ch PILR28.7 PILR28.6 PILR29 0E5Dh PILR29.7 PILR29.6 PILR30 0E5Eh PILR30.7...
Page 516 Chapter 30 I/O Ports 3.Port Register Settings EPILR16 0E90h EPILR17 0E91h EPILR18 0E92h EPILR19 0E93h EPILR20 0E94h EPILR21 0E95h EPILR22 0E96h EPILR23 0E97h EPILR24 0E98h EPILR25 0E99h EPILR26 0E9Ah EPILR27 0E9Bh EPILR28 0E9Ch EPILR29 0E9Dh EPILR30 0E9Eh EPILR31 0E9Fh EPILR32 0EA0h EPILR33 0EA1h...
Page 517 PPER02 0EC2h PPER02.7 PPER02.6 PPER03 0EC3h PPER03.7 PPER03.6 PPER04 0EC4h PPER04.7 PPER04.6 PPER05 0EC5h PPER05.7 PPER05.6 PPER06 0EC6h PPER06.7 PPER06.6 PPER07 0EC7h PPER07.7 PPER07.6 PPER08 0EC8h PPER08.7 PPER08.6 PPER09 0EC9h PPER09.7 PPER09.6 PPER10 0ECAh PPER10.7 PPER10.6 PPER11 0ECBh PPER11.7 PPER11.6 PPER12 0ECCh PPER12.7...
Page 518 Chapter 30 I/O Ports 3.Port Register Settings PPCRx.y Pull Down is selected Addr PPCR00 0F00h PPCR00.7 PPCR00.6 PPCR00.5 PPCR00.4 PPCR00.3 PPCR00.2 PPCR00.1 PPCR00.0 PPCR01 0F01h PPCR01.7 PPCR01.6 PPCR01.5 PPCR01.4 PPCR01.3 PPCR01.2 PPCR01.1 PPCR01.0 PPCR02 0F02h PPCR02.7 PPCR02.6 PPCR02.5 PPCR02.4 PPCR02.3 PPCR02.2 PPCR02.1 PPCR02.0 PPCR03 0F03h PPCR03.7 PPCR03.6 PPCR03.5 PPCR03.4 PPCR03.3 PPCR03.2 PPCR03.1 PPCR03.0...
Page 519 PPCR28 0F1Ch PPCR28.7 PPCR28.6 PPCR28.5 PPCR28.4 PPCR28.3 PPCR28.2 PPCR28.1 PPCR28.0 PPCR29 0F1Dh PPCR29.7 PPCR29.6 PPCR29.5 PPCR29.4 PPCR29.3 PPCR29.2 PPCR29.1 PPCR29.0 PPCR30 0F1Eh PPCR30.7 PPCR30.6 PPCR30.5 PPCR30.4 PPCR30.3 PPCR30.2 PPCR30.1 PPCR30.0 PPCR31 0F1Fh PPCR31.7 PPCR31.6 PPCR31.5 PPCR31.4 PPCR31.3 PPCR31.2 PPCR31.1 PPCR31.0 PPCR32 0F20h PPCR32.7 PPCR32.6 PPCR32.5 PPCR32.4 PPCR32.3 PPCR32.2 PPCR32.1 PPCR32.0...
Page 520 Chapter 30 I/O Ports 3.Port Register Settings PODR14 0E0Eh PODR14.7 PODR14.6 PODR14.5 PODR14.4 PODR14.3 PODR14.2 PODR14.1 PODR14.0 0000 0000 PODR15 0E0Fh PODR15.7 PODR15.6 PODR15.5 PODR15.4 PODR15.3 PODR15.2 PODR15.1 PODR15.0 0000 0000 PODR16 0E10h PODR16.7 PODR16.6 PODR16.5 PODR16.4 PODR16.3 PODR16.2 PODR16.1 PODR16.0 0000 0000 PODR17 0E11h PODR17.7 PODR17.6 PODR17.5 PODR17.4 PODR17.3 PODR17.2 PODR17.1 PODR17.0 0000 0000...
Page 521 Chapter 30 I/O Ports 3.Port Register Settings...
Page 522 Chapter 30 I/O Ports 3.Port Register Settings...
Page 523: Chapter 31 External Bus
Chapter 31 External Bus The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface and its operation. 1. Overview of the External Bus Interface 1.1 Features ●...
Page 524 Chapter 31 External Bus 1.Overview of the External Bus Interface • Capable of setting timing values such as the CAS latency and RAS - CAS delay (SDRAM area) • Capable of controlling the distributed/centralized auto - refresh, self - refresh, and other refresh timings (SDRAM area) ●...
Page 525 1.2 Block Diagram Figure 1-1 Block Diagram of the External Bus Interface Internal address bus Internal data bus write buffer switch read buffer switch +1 or +2 address buffer comparator SDRAM control refresh counter External terminal controller all-block control registers control Chapter 31 External Bus 1.Overview of the External Bus Interface...
Page 526 Chapter 31 External Bus 1.Overview of the External Bus Interface 1.3 I/O Pins The I/O pins are external bus interface pins (Some pins have other uses). The following lists the I/O pins for each interface: ● Ordinary bus interface • A31 to A00, D31 to D00 (AD15 to AD00) •...
Page 527 Figure 1-2 List of External Bus Interface Registers 24 23 Address 00000640 ASR0 00000644 ASR1 00000648 ASR2 0000064c ASR3 00000650 ASR4 00000654 ASR5 00000658 ASR6 0000065c ASR7 00000660 AWR0 00000664 AWR2 00000668 AWR4 0000066c AWR6 00000670 MCRA 00000674 Reserved Reserved 00000678 IOWR0 0000067c...
Page 528: External Bus Interface Registers
Chapter 31 External Bus 2.External Bus Interface Registers 2. External Bus Interface Registers This section explains the registers used in the external bus interface. ■ Register Types The following registers are used by the external bus interface: • Area select registers (ASR0-7) •...
Page 529 Figure 2-1 Conﬁguration of the Area Select Registers (ASR0-7) ASR0 00000640 ASR1 00000644 ASR2 00000648 ASR3 0000064C ASR4 00000650 ASR5 00000654 ASR6 00000658 ASR7 0000065C ■ Functions of Bits in the Area Select Registers (ASR0-7) The start address can be set in the high-order 16 bits (bits A31-A16). Each chip select area starts with the address set in this register and covers the range set by the four bits ASZ3-0 of the ASR0-7 registers.
Page 530 Chapter 31 External Bus 2.External Bus Interface Registers select area. Figure 2-2 "Configuration of Area Configuration Registers 0-7 (ACR0-7)" shows the configuration of area configuration registers 0-7 (ACR0-7). Figure 2-2 Conﬁguration of Area Conﬁguration Registers 0-7 (ACR0-7) (Continued on next page) ACR0H 0000 0642 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 1111**00...
Page 531 ACR4H 0000 0652 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 ACR4L 0000 0653 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 ACR5H 0000 0656 ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0 ACR5L 0000 0657 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 ACR6H 0000 065A ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0...
Page 532 Chapter 31 External Bus 2.External Bus Interface Registers Table 2-1 Area Size Settings ASZ3 ASZ2 ASZ1 ASZ3-0 are used to set the size of each area by modifying the number of bits for address comparison to a value different from ASR. Thus, an ASR contains bits that are not compared. Bits ASZ3-0 of ACR0 are initialized to 1111 ) by RST.
Page 533 Table 2-3 Setting of the Maximum Burst Length of Each Chip Select BST1 BST0 In areas for which a burst length other than the single access is set, continuous burst access is performed within the address boundary determined by the burst length only when prefetch access is performed or data having a size exceeding the bus width is read.
Page 534 Chapter 31 External Bus 2.External Bus Interface Registers WREN Enable write If an area for which write operations are disabled is accessed for a write operation from the internal bus, the access is ignored and no external access at all is performed. Set the WREN bit of areas for which write operations are not required, such as data areas, to 0.
Page 535 Table 2-4 Access Type Settings for Each Chip Select Area TYP3 TYP2 TYP1 *1: If this setting is made, WR0-WR3 can be used as the enable of each bit. *2: Only the ACR6 and ACR7 registers are valid. The ACR0, ACR1, ACR2, ACR3, ACR4, and ACR5 registers are disabled.
Page 536 Chapter 31 External Bus 2.External Bus Interface Registers 2.3 Area Wait Register (AWR0-7) This section explains the configuration and functions of the area wait registers (AWR0-7). ■ Configuration of the Area Wait Registers (AWR0-7) The area wait registers (AWR0-7: Area Wait Register 0-7) specify various kinds of waits for each chip select area. Figure 2-3 "Configuration of the Area Wait Registers (AWR0-7)"...
Page 537 AWR5H 0000 066A AWR5L 0000 066B AWR6H 0000 066C AWR6L 0000 066D AWR7H 0000 066E AWR7L 0000 066F The function of each bit changes according to the access type (TYP(3-0) bits) setting of the ACR0-7 registers,. A chip select area determined by either of the following settings becomes the area for normal access or a address/ data multiplex access operation.
Page 538 Chapter 31 External Bus 2.External Bus Interface Registers [Bits 15-12] W15-12 (First Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle. Except for the burst access cycles, only this wait setting is used. Table 2-5 "Settings for the Number of Auto-Wait Cycles (During First Access)"...
Page 539 [Bits 7,6] W07-06 (Read -> Write Idle Cycle) The read -> write idle cycle is set to prevent collision of read data and write data on the data bus when a write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals maintain the high impedance state.
Page 540 Chapter 31 External Bus 2.External Bus Interface Registers [Bits 3] W03 (WR0-WR3, WRn Output Timing Selection) The WR0-WR3, WRn output timing setting selects whether to use write strobe output as an asynchronous strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO. The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an ASIC).
Page 541 [Bits 2] W02 (Address -> CSn Delay) The address -> CSn delay setting is made when a certain type of setup is required for the address when CSn falls or CSn edges are needed for successive accesses to the same chip select area. Set the address and set the delay from AS output to CS0-CS7 output.
Page 542 Chapter 31 External Bus 2.External Bus Interface Registers [Bits 0] W00 (RD/WRn -> CSn Hold Extension Cycle) The RD/WRn -> CSn hold extension cycle is set to extend the period before negating CSn after the read/write strobe is negated. One hold extension cycle is inserted before CSn is negated after the read/write strobe is negated.
Page 543 Table 2-10 Setting the Number of Cycles from RAS Output to CAS Output For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS - CAS delay cycle. [Bit 11] W11: Reserved bit Be sure to set this bit to 0. [Bits 10 - 8] W10 to W08 (CAS latency Cycle): CAS latency Set these bits to the CAS latency.
Page 544 Chapter 31 External Bus 2.External Bus Interface Registers Table 4.2 - 22 lists the settings for the write recovery cycle. Table 2-13 Write recovery cycle For all the areas connected to SDRAM/FCRAM, set these bits to the same write recovery cycle. [Bits 3 - 2] W03 and W02 (RAS Active time): RAS active time Set these bits to the minimum number of cycles for RAS active time.
Page 545 ■ Structure of the Memory Setting Register (MCRA for SDRAM/FCRAM auto - precharge OFF mode) Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode) The memory setting register (MCRA: Memory Setting Register for extend type - A for SDRAM/FCRAM auto - precharge OFF mode) is used to make various settings for SDRAM/FCRAM connected to the chip select area.
Page 546 Chapter 31 External Bus 2.External Bus Interface Registers Table 2-27 lists the settings for burst write. Table 2-18 Settings for burst write WBST Settings for burst write Single write Burst write For connecting FCRAM, be sure to set the bit to 1. FCRAM supports neither burst read nor single write mode.
Page 547 Figure 2-5 Structure of the Memory Setting Register (MCRB for FCRAM auto - precharge ON mode) 00000671 H Address Reserved The register serves as the area for making various settings for FCRAM connected to the chip select area for which the access type (TYP3 to TYP0 bits) in the ACR6 and ACR7 registers has been set as in Table 2-30 lists the access type settings (TYP3 to TYP0 bits).
Page 548 Chapter 31 External Bus 2.External Bus Interface Registers ■ Functions of Bits in the I/O Wait Registers for DMAC (IOWR0-3) The following explains the functions of the bits in the I/O wait registers for DMAC. [Bits 31, 23] RYE0,1 (RDY enable 0,1) These bits set the wait control, using RDY, of channels 0-3 during DMAC fly-by access.
Page 549 Chapter 31 External Bus 2.External Bus Interface Registers is set to the high impedance state.
Page 550 Chapter 31 External Bus 2.External Bus Interface Registers [Bits 27-24, 19-16, 11-8] IW03-00,IW13-10 (I/O Access Wait) These bits set the number of auto-wait cycles for I/O access during DMA fly-by access. Table 2-23 "Settings for the Number of I/O Wait Cycles" lists the settings for the number of I/O wait cycles. Table 2-23 Settings for the Number of I/O Wait Cycles IWn3 IWn2...
Page 551 Before setting this register, be sure to make all settings required for the corresponding chip select areas. CSE7-0 Area control Table 2-24 " CSn Corresponding to the Chip Select Enable Bits" lists the corresponding CSn for the chip select enable bits. Table 2-24 CSn Corresponding to the Chip Select Enable Bits CSE bit Corresponding CSn...
Page 552 Chapter 31 External Bus 2.External Bus Interface Registers [Bits 23-16] CHE7-0 (Cache Enable 7-0) These bits enable and disable each chip select area for transfers to the built-in cache. CHEn Not a cache area (data read from the applicable area is not saved in the cache) Cache area (data read from the applicable area is saved in the cache) 2.9 Pin/Timing Control Register (TCR) This section explains the configuration and functions of the pin/timing control register and its...
Page 553 [Bit 6] PSUS (Prefetch suspend) This bit controls temporary stopping of prefetch to all areas. PSUS Enable prefetch Suspend prefetch If 1 is set, no new prefetch operation is performed before 0 is written. Since during this time the contents of the prefetch buffer are not deleted unless a prefetch buffer occurs, clear the prefetch buffer using the PCLR bit function (bit 5) before restarting prefetch.
Page 554 Chapter 31 External Bus 2.External Bus Interface Registers 2.10 Refresh Control Register (RCR) This section describes the bit configuration and functions of the refresh control register (RCR). ■ Structure of the Refresh Control Register (RCR) The refresh control register (RCR) is used to make various refresh control settings for SDRAM. The setting of this register is meaningless as long as SDRAM control is not set for any area, in that case the register value must not be updated from the initial state.
Page 555 When read by a Read - modify - Write instruction, the SELF, RRLD, and PON bits always return to 0. (Bit 30) RRLD (Refresh counter ReLoaD): Refresh counter start control This bit is used to start and reload the fresh counter. Table 4.2-43 shows the function of refresh counter startup control.
Page 556 Chapter 31 External Bus 2.External Bus Interface Registers [Bits 22 - 20] RFC2, RFC1, RFC0 (ReFresh Count): Refresh count Set these bits to the number of times a refresh must be performed to refresh all SDRAM. Table 4.2-45 shows the number of times to refresh. Table 2-29 Number of times to refresh RFC2 RFC1...
Page 557 Table 4.2-47 lists the settings for the refresh cycle (tRC). Table 2-31 Settings for the refresh cycle (tRC) TRC2 TRC1 TRC0 Refresh cycle (tRC) Chapter 31 External Bus 2.External Bus Interface Registers...
Page 558: Setting Example Of The Chip Select Area
Chapter 31 External Bus 3.Setting Example of the Chip Select Area 3. Setting Example of the Chip Select Area In the external bus interface, a total of eight chip select areas can be set. This section presents an example of setting the chip select area. ■...
Page 559: Endian And Bus Access
4. Endian and Bus Access There is a one-to-one correspondence between the WR0-WR3 control signal and the byte loca- tion regardless of the endian method (big or little) and the data bus width. The following sum- marizes the location of bytes on the data bus of the MB91460 series used according to the specified data bus width and the corresponding control signal for each bus mode.
Page 560 Chapter 31 External Bus 4.Endian and Bus Access ● SDRAM Interface Figure 4-3 Data bus width of the SDRAM (FCRAM) interface and its control signals a)32-bit bus width Data bus Control signal 4.1 Big Endian Bus Access With the exception of the CS0 area of the MB91460 series, either the big endian method or the little endian method can be selected for each chip select area.
Page 561 Figure 4-5 Relationship between the Internal Register and External Data Bus for Halfword Access a) Output address low-order digits "00" Internal register External bus Figure 4-6 Relationship between Internal Register and External Data Bus for Byte Access a) Output address b) Output address low-order digits "00"...
Page 562 Chapter 31 External Bus 4.Endian and Bus Access ● 16-bit bus width Figure 4-8 Relationship between Internal Register and External Bus Having 16-Bit Bus Width Output address low-order digits ● 8-bit bus width Figure 4-9 Relationship between Internal Register and External Bus having 8-Bit bus Width Internal register Output address low-order digits ■...
Page 563 ● 32-bit bus width Figure 4-10 External bus Access for 32-Bit Bus Width (a) PA1/PA0="00" (b) PA1/PA0="01" →(1) Output A1/A0="00" →(1) Output A1/A0="00" 32bit ● 16-bit bus width Figure 4-11 External bus Access for 16-Bit Bus Width (A) Word access (a) PA1/PA0="00"...
Page 564 Chapter 31 External Bus 4.Endian and Bus Access ● 8-bit bus width Figure 4-12 External Bus Access for 8-Bit Bus Width (A) Word access (a) PA1/PA0="00" (1) Output A1/A0="00" (2) Output A1/A0="01" (3) Output 1/A0="10" (4) Output 1/A0="11" 8bit (B) Halfword access (a) PA1/PA0="00"...
Page 565 Figure 4-13 Example of Connecting the MB91460 Series to External Devices This LSI D24 D23 D16 D15 32-bit device (low-order 2 bits of the address 00 to 11) 4.2 Little Endian Bus Access Little endian (LER) external bus access is performed for an area for which the little endian meth- od is set.
Page 566 Chapter 31 External Bus 4.Endian and Bus Access ● Halfword access The byte data on the MSB side for the big endian address 0 becomes byte data on the LSB side when the little endian method is used. For halfword access, the byte locations of two bytes are reversed. 0 ->...
Page 567 Figure 4-16 Relationship between Internal Register and External Data Bus for Byte Access (3) Halfword access (when executing the LDUB/STB instructions) a) Output address b) Output address low-orderdigits "00" Internal External register ■ Data Bus Width The following shows the relationships between the internal register and external data bus for each data bus width. ●...
Page 568 Chapter 31 External Bus 4.Endian and Bus Access ● 8-bit bus width Figure 4-19 Relationship between the Internal Register and External Data Bus in the 8-bit Bus Width Internal register Output address low-order digits ■ Examples of Connection with External Devices The following shows examples of connecting the MB91460 series to external devices for each bus width.
Page 569 ● 16-bit bus width Figure 4-21 Example of Connecting the MB91460 Series to External Devices (16-Bit Bus Width) D15 D08 D07 big endian area ● 8-bit bus width Figure 4-22 Example of Connecting the MB91460 Series to External Devices (8-Bit Bus Width) big endian area This LSI D15 D08 D07...
Page 570 Chapter 31 External Bus 4.Endian and Bus Access 4.3 Comparison of Big Endian and Little Endian External Access This section shows a comparison of big endian and little endian external access in word access, halfword access, and byte access for each bus width.
Page 571 ■ Word Access Big endian mode 32-bit bus Internal External width address: Lower 2-bit: "0" 16-bit bus Internal width address: "0" "2" 8-bit bus Internal width address: Control terminal terminal External Control terminal terminal AA CC BB DD External Control terminal terminal "0"...
Page 572 Chapter 31 External Bus 4.Endian and Bus Access ■ Halfword Access Big endian mode 32-bit bus Internal External width terminal address : "0" Internal address : "2" Control terminal External Control terminal terminal Little endian mode Internal External Control terminal terminal address : "0"...
Page 573 Big endian mode 16-bit bus Internal External width terminal address: "2" Internal External terminal address: "2" 8-bit bus Internal External width terminal address: "0" "1" Internal External terminal address: "2" "3" Control terminal Control terminal Control terminal Control terminal Chapter 31 External Bus 4.Endian and Bus Access Little endian mode Internal...
Page 574 Chapter 31 External Bus 4.Endian and Bus Access ■ Byte Access...
Page 575 Big endian mode 32-bit bus Internal width address : "0" Internal address : "1" Internal address : "2" Internal address : "3" External Control terminal terminal External Control terminal terminal External Control terminal terminal External Control terminal terminal Chapter 31 External Bus 4.Endian and Bus Access Little endian mode Internal...
Page 576 Chapter 31 External Bus 4.Endian and Bus Access Big endian mode 16-bit bus Internal width address: "0" Internal address: "1" Internal address: "2" Internal address: "3" External Control terminal terminal External Control terminal terminal External Control terminal terminal External Control terminal terminal Little endian mode...
Page 577 Big endian mode 8-bit bus Internal width address: "0" Internal address: "1" Internal address: "2" Internal address: "3" External Control terminal terminal External Control terminal terminal External Control terminal terminal External Control terminal terminal Chapter 31 External Bus 4.Endian and Bus Access Little endian mode Internal External...
Page 578: Operation Of The Ordinary Bus Interface
Chapter 31 External Bus 5.Operation of the Ordinary bus interface 5. Operation of the Ordinary bus interface This section explains operation of the ordinary bus interface. ■ Ordinary Bus Interface For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access and write access. The following operational phases of the ordinary bus interface are explained below with the use of a timing chart.
Page 579 Figure 5-1 Basic Timing (For Successive Accesses) MCLK A[31:0] READ D[31:0] WRITE D[31:0] • AS is asserted for one cycle in the bus access start cycle. • A31-0 continues to output the address of the location of the start byte in word/halfword/byte access from the bus access start cycle to the bus access end cycle.
Page 580 Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-2 Timing Chart for the WRn + Byte Control Type MCLK A[31:0] CSn * WR0,WR1 READ WR2,WR3 D[31:0] WR0,WR1 WRITE WR2,WR3 D[31:0] • Operation of AS, CSn, RD, A31-0, and D31-16 is the same as that described in asserted from the 2nd cycle of the bus access.
Page 581 5.3 Read -> Write Operation This section shows the operating timing for read -> write. ■ Operation Timing of Read -> Write Figure 5-3 "Timing Chart for Read -> Write" shows the operation timing for (TYP3-0=0000 MCLK A[31:0] D[31:0] • Setting of the W07/W06 bits of the AWR register enables 0-3 idle cycles to be inserted.
Page 582 Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-4 Timing Chart for the Write -> Write Operation MCLK A[31:0] D[31:0] • Setting of the W05/W04 bits of the AWR register enables 0-3 write cycles to be inserted. •...
Page 583 Figure 5-5 Timing Chart for the Auto-Wait Cycle MCLK A[31:0] D[31:0] D[31:0] Setting of the W15-12 bits (first wait cycles) of the AWR register enables 0-15 auto-wait cycles to be set. Figure 5-5 "Timing Chart for the Auto-Wait Cycle", two auto-wait cycles are inserted, making a total of four cycles for access.
Page 584 Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-6 Timing Chart for the External Wait Cycle MCLK A[31:0] D[31:0] D[31:0] Setting 1 for the TYP0 bit of the ACR register and enabling the external RDY input pin enables external wait cycles to be inserted.
Page 585 Figure 5-7 Timing Chart for Synchronous Write Enable Output MCLK A[31:0] CSn * Read D[31:0] Write D[31:0] • If synchronous write enable output is enabled (If the W03 bit of the AWR is 1), operation is as follows. • WR0-WR3 and WRn pin output asserts synchronous write enable output at the timing at which AS pin output is asserted.
Page 586 Chapter 31 External Bus 5.Operation of the Ordinary bus interface • If synchronous write enable output is used, the following restrictions apply: Do not set the following additional wait because the timing for synchronous write enable output becomes meaningless: - CS -> RD/WRn setup (Always write 0 to the W01 bit of AWR) - First wait cycle setting (Always write 0000 to bits W15-W12 of AWR) Do not set the following access types (TYPE3-0 bits (Bits 3-0) in the ACR register) because the timing for synchronous write enable output becomes meaningless:...
Page 587 5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting This section shows the operation timing for the CSn -> RD/WRn setup and RD/WRn -> CSn hold settings. ■ Operation Timing for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings Figure 5-9 "Timing Chart for the CSn ->...
Page 588 Chapter 31 External Bus 5.Operation of the Ordinary bus interface ■ Operation Timing for DMA Fly-By Transfer (I/O -> Memory) Figure 5-10 "Timing Chart for DMA Fly-By Transfer (I/O -> Memory)" shows the operation timing for (TYP3- 0=0000 , AWR=0008 , IOWR=51 side.
Page 589 Figure 5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O) Basic cycle MCLK A[31:0] D[31:0] IOWR • Setting 1 for the HLD bit of the IOWR0-3 registers enables the I/O read cycle to be extended by one cycle. • Setting the WR1,0 bits of the IOWR0-3 registers enables 0-3 write recovery cycles to be inserted.
Page 590: Burst Access Operation
Chapter 31 External Bus 6.Burst Access Operation 6. Burst Access Operation In the external bus interface, the operation that transfers successive data items in one access sequence is called burst access. The normal access cycle (that is, not burst access) is called single access.
Page 591 the minimum number of the first access cycles is the wait cycles + 2 cycles (three cycles in the timing chart shown in Figure 6-1 "Timing Chart for Burst Access"). • Setting of the W11-W08 bits of the AWR register enables 0-15 page wait cycles to be inserted. At this point, the page access cycles can be obtained from the page wait cycles + 1 cycle (Two cycles in the timing chart shown in Figure 6-1...
Page 592: Address/Data Multiplex Interface
Chapter 31 External Bus 7.Address/data Multiplex Interface 7. Address/data Multiplex Interface This section explains the following three cases of operation of the address/data multiplex inter- face: • Without external wait • With external wait • CSn -> RD/WRn setup ■ Without External Wait Figure 7-1 "Timing Chart for the Address/Data Multiplex Interface (without External Wait)"...
Page 593 • As with the normal interface, auto-wait (AWR15-12), read -> write idle cycle (AWR7-6), write recovery (AWR5- 4), address -> CSn delay (AWR2), CSn -> RD/WRn setup delay (AWR1), and RD/WRn -> CSn hold delay (AWR0) can be set. • In areas for which the address/data multiplex interface is set, set 1(DBW1-0=00 ■...
Page 594 Chapter 31 External Bus 7.Address/data Multiplex Interface Figure 7-3 Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn Setup) MCLK A[31:0] READ D[31:16] WRITE D[31:16] Setting 1 for the CSn -> RD/WRn setup delay (AWR1) enables the multiplex address output cycle to be extended by one cycle as shown in Figure 7-3 Setup)", allowing the address to be latched directly to the rising edge of AS.
Page 595: Prefetch Operation
8. Prefetch Operation This section explains the prefetch operation. ■ Prefetch Operation The external bus interface controller contains a prefetch buffer consisting of 16 x 8 bits. If the PSUS bit of the TCR register is 0 and read access to an area to which the PFEN bit of the ACR register is set to 1 occurs, the subsequent address is prefetched and then stored in the prefetch buffer.
Page 596 Chapter 31 External Bus 8.Prefetch Operation During burst access, successive accesses occur only within the address boundary that that is determined by the burst length. Thus, if the boundary is crossed, for example, 4 bytes of free space are available in the buffer, these 4 bytes cannot be accessed in one operation (If the prefetch buffer starts at xxxxxx0E space are available in the buffer, and two bursts are set even though the bus width is 16 bits, only 2 bytes, xxxxxx0E...
Page 597 • If a buffer read error occurs. A buffer read error is if any of the following events occurs: • When no address is found in the buffer that matches in an to read from a prefetch-enabled area. In this case, the external bus is accessed again.
Page 598: Sdram/Fcram Interface Operation
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation 9. SDRAM/FCRAM Interface Operation This section describes the operations of the SDRAM/FCRAM interface. ■ SDRAM/FCRAM interface The chip select areas can be used as SDRAM/FCRAM interface by setting the TYP3 to TYP0 bits in the area configuration register (ACR) to 100X This section provides timing charts to describe the following operations of the SDRAM/FCRAM interface.
Page 599 MCLK SRAS,SCAS, READ Set the W07 and W06 bits in the area wait register (AWR) to the read - to - write idle cycle according to the SDRAM/FCRAM standards. ■ Single Read Operation Timing Figure 9-3 shows the operation timings assuming that page misses, CAS latency 3, and no auto - precharge are set.
Page 600: Self Refresh
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation MCLK SRAS,SCAS, ACTV • Setting TYP to 1001 causes a read/write command with auto - precharge to be issued. Since the cycle from READA/WRITA issuance to ACTV issuance is fixed at CL + BL - 1, however, TYP can be set to 1001 when FCRAM is connected.
Page 601 ■ Self Refresh Writing 1 to the SELF bit in the refresh control register (RCR) causes the SDRAM/FCRAM interface to initiate the self - refresh transition sequence. After executing auto - refreshing the number of times set in the RFC2 to RFC0 bits, the SDRAM/FCRAM interface issues the SELF command to SDRAM/FCRAM to enter the self - refresh mode.
Page 602 Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation 9.3 Connecting SDRAM/FCRAM to Many Areas This section shows the connecting SDRAM/FCRAM to many areas. ■ Connecting SDRAM/FCRAM to Many Areas SDRAM/FCRAM can basically be set for all chip select areas. When connecting SDRAM/FCRAM to several areas, connect the same type of modules.
Page 603 Figure 9-6 Examples of combinations of access addresses and Row/BANK/Column addresses 4M bytes (set ASZ to 0110 256 column (set PSZ to 000 Access address bit External address pin 16M bytes (set ASZ to 1000 512 column (set PSZ to 001 Access address bit External address pin 64M bytes (set ASZ to 1010...
Page 604 Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation Table 9-1 SDRAM/FCRAM Interface to SDRAM/FCRAM Connection Table SDRAM/ SDRAM/ FCRAM FCRAM pin interface SWE (WR) CS0 to CS7 A0 to A9 A0 to A9 A10/AP A10/AP A11 to A13 A11 to A13 D31 to D0 DQMUU, DQMUL,...
Page 605 IA11-IA0 IA11-IA0 IA11-IA0 IA11-IA0 When SDRAM modules are used with a total data width of 16 bits, SDRAMs No. 3 and No. 4 are not required and DQ15 to DQ0 must be left open. ● Using 16 - bit SDRAM/FCRAM Total data width of 32 bits: Use two or four SDRAM modules.
Page 606 Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation A15 A14 CS7 CS6 BA1BA0 BA1BA0 BA1BA0 When using one SDRAM module with a data width of 16 bits, SDRAMs No. 2, No. 3, and No. 4 are not required and DQ15 to DQ0 must be left open. When two SDRAM modules are used with a data width of 16 bits, SDRAMs No.
Page 607 Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation SDRAM No. 2 is not required when the device is used with only one SDRAM module.
Page 608: Dma Access Operation
Chapter 31 External Bus 10.DMA Access Operation 10. DMA Access Operation This section explains DMA access operation. ■ DMA Access Operation This section explains the following five DMA operations: • DMA fly-by transfer (I/O -> memory) • DMA fly-by transfer (memory -> I/O) •...
Page 609 Figure 10-1 Timing Chart for DMA Fly-By Transfer (I/O -> Memory) MCLK A[31:0] D[31:0] DACKn FR30 compatible mode DEOPn DACKn Basic mode DEOPn IORD DREQn n = 0, 1, 2 • Setting 1 for the W01 bit of the AWR register enables the CSn -> RD/WRn setup delay to be set. Set this bit to extend the period between assertion of chip select and the read/write strobe.
Page 610 Chapter 31 External Bus 10.DMA Access Operation 10.2 DMA Fly-By Transfer (Memory -> I/O) This section explains DMA fly-by transfer (memory -> I/O). ■ DMA Fly-By Transfer (Memory -> I/O) Figure 10-2 "Timing chart for DMA Fly-By Transfer (Memory -> I/O)" shows the operation timing chart for (TYP3- 0=0000 , AWR=0008 , IOWR=41...
Page 611 Reference: For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus cycles extended by the I/ O wait cycle is generated.
Page 612 Chapter 31 External Bus 10.DMA Access Operation Figure 10-3 Timing Chart for DMA Fly - by Transfer (I/O to SDRAM/FCRAM) MCLK A31 to 0 SRAS SCAS WRn(SWE) D31 to 0 DACKn FR30 compatible mode DEOPn DACKn Basic mode DEOPn IORD DREQn I/O wait I/O hold...
Page 613 • For the I/O device on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. • For SDRAM/FCRAM on the receiving side, a WRIT command is issued at the timing that allows writing after the I/O wait cycle.
Page 614 Chapter 31 External Bus 10.DMA Access Operation ● At SDRAM page hit (Shortest) Figure 10-4 Timing Chart for DMA Fly - by Transfer (SDRAM/FCRAM to I/O) with Page Hits (Shortest) MCLK A31 to 0 SRAS SCAS WRn(SWE) MCLKE D31 to 0 DACKn Basic mode...
Page 615 If SDRAM access is shorter than I/O access, the SDRAM access is extended by the I/O access (base access plus I/O wait). Figure 4.10 - 5 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and IOWR set to 42H.
Page 616 Chapter 31 External Bus 10.DMA Access Operation • For the I/O device on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. • The I/O hold wait cycle does not affect the write strobe. •...
Page 617 MCLK A31 to 0 SRAS SCAS WRn(SWE) MCLKE D31 to 0 DACKn Basic mode DEOPn IOWR DREQn The rise of the IOWR signal can be delayed one cycle by extending SDRAM read access one cycle when the signal resulting from OR (negative - logic AND) operation of the CAS signal and the chip select signal for the SDRAM area subject to transfer is input t As the external wait signal is generated based on the CAS signal rise timing in this case, the data setup time from the SDRAM data output to the I/O device can be reserved for one cycle, regardless of a page hit or miss in...
Page 618 Chapter 31 External Bus 10.DMA Access Operation 10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM) This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation. The timing is the same as for external I/O, RAM -> internal RAM. ■...
Page 619 ■ 2-Cycle Transfer (External -> I/O) Figure 10-9 "Timing Chart for 2-Cycle Transfer (External -> I/O" shows the operation timing chart for (TYP3- 0=0000 , AWR=0008 , IOWR=00 Figure 10-9 "Timing Chart for 2-Cycle Transfer (External -> I/O" shows a case in which a wait is not set for memory and I/O.
Page 620 Chapter 31 External Bus 10.DMA Access Operation ■ 2-Cycle Transfer (I/O -> External) Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -> External)" shows the operation timing chart for (TYP3- 0=0000 , AWR=0008 , IOWR=00 Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -> External)" shows a case in which a wait is not set for memory and I/O.
Page 621 ■ 2-Cycle Transfer (I/O -> SDRAM/FCRAM) Figure 4.10 - 11 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and IOWR set to 00H. Figure 10-11 Timing Chart for Two - cycle Transfer (I/O to SDRAM/FCRAM) MC LK A31 to 0 CS n...
Page 622 Chapter 31 External Bus 10.DMA Access Operation Figure 10-12 Timing Chart for Two - cycle Transfer (SDRAM/FCRAM to I/O) MCLK A31 to 0 SRAS SCAS WRn(SWE) D31 to 0 DACKn FR30 compatible mode DEOPn DACKn Basic mode DEOPn DREQn memory I/O address address...
Page 623 • Bus access is the same as that of the interface for non - DMA transfer. • In base mode, DACKn/DEOPn is output at both of transfer source bus access and transfer destination bus access. Chapter 31 External Bus 10.DMA Access Operation...
Page 624: Bus Arbitration
Chapter 31 External Bus 11.Bus Arbitration 11. Bus Arbitration This section shows timing charts for releasing the bus right and for acquiring the bus right. ■ Releasing the Bus Right Figure 11-1 "Timing Chart for Releasing the Bus Right" shows the timing chart for releasing the bus right. 11-2 "Timing Chart for Releasing the Bus Right"...
Page 625 Figure 11-2 Timing Chart for Acquiring the Bus Right MCLK A23 to A0 CSn * Read D31 to D16 BGRNT • Setting 1 for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed. • When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle later.
Page 626: Procedure For Setting A Register
Chapter 31 External Bus 12.Procedure for Setting a Register 12. Procedure for Setting a Register This section explains the procedure for setting a register. ■ Procedure for Setting a Register Using the following procedures to make external bus interface settings: 1.
Page 627: Notes On Using The External Bus Interface
13. Notes on Using the External Bus Interface This section explains some notes when using the external bus interface. ■ Notes for Use If settings are made so that the area (TYP3-0=0x0x (TYP3-0=0x1x ) where WR is used as a write strobe are mixed, be sure to make the following setting in all areas that will be used: •...
Page 628 Chapter 31 External Bus 13.Notes on Using the External Bus Interface...
Page 629: Chapter 32 Usart (Lin / Fifo)
Chapter 32 USART (LIN / FIFO) 1. Overview This chapter explains the function and operation of the USART. The USART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. 16 bytes transmission and reception FIFOs are available for selected channels.
Page 630 Chapter 32 USART (LIN / FIFO) 1.Overview Table 1-1 USART functions (continued) Master-slave communication function (multiprocessor mode) Synchronous mode Transceiving pins LIN bus options Synchronous serial clock Clock delay option 16 word deep FIFO ■ USART operation modes The USART operates in four different modes, which are determined by the MD0- and the MD1-bit of the Serial mode register (SMR04).
Page 631: Usart Interrupts
Table 1-3 Mode Bit Setting ■ USART Interrupts Table 1-4 USART interrupts Interrupt Interrupt cause number USART04 #66 (42 reception interrupt USART04 #67 (43 transmission interrupt Mode Description Asynchronous (normal mode) Asynchronous (multiprocessor mode) Synchronous (normal mode) Asynchronous (LIN mode) Interrupt control register Register name Address...
Page 632: Usart Configuration
Chapter 32 USART (LIN / FIFO) 2.USART Conﬁguration 2. USART Configuration ■ USART consists of the following blocks: • Reload Counter • Reception Control Circuit • Reception Shift Register • Reception Data Register • Transmission Control Circuit • Transmission Shift Register •...
Page 633 SCK0 SIN0 Over- sampling Unit Signal to ICU Signal to EI RDRF register TDRE ■ Explanation of the different blocks • Reload Counter The reload counter functions as the dedicated baud rate generator. It can select external input clock or internal clock for the transmitting and receiving clocks.
Page 634 Chapter 32 USART (LIN / FIFO) 2.USART Conﬁguration • Reception Data Register This register retains reception data. Serial input data is converted and stored in this register. If the FIFO is enabled up to 16 receptions can be saved, the trigger level is progammable. •...
Page 635 • Specifying a data length • Selecting a frame data format in mode 1 • Clearing the error flags • Specifying whether to enable transmission • Specifying whether to enable reception • Serial Status Register This register checks the transmission and reception status and error status, and enables and disables transmission and reception interrupt requests.
Page 636: Usart Pins
Chapter 32 USART (LIN / FIFO) 3.USART Pins 3. USART Pins ■ USART Pins The USART pins also serve as general ports. Table required to use USART. Table 3-1 USART04 Pins Pin name Pin function Port I/O or serial SIN04 data input Port I/O or serial SOT04...
Page 637: Usart Registers
4. USART Registers The following table defines the USART04 registers: Table 4-1 USART04 Registers Address bit 15 , 061 SCR04 (Serial Control Register) , 063 SSR04 (Serial Status Register) , 065 ESCR04 (Extended Status/Control Reg.) , 067 FSR04 (FIFO status register) , 089 BGR104 (Baud Rate Generator Reg.
Page 638 Chapter 32 USART (LIN / FIFO) 4.USART Registers R/W R/W R/W R/W Readable and writable Write only Initial value Figure 4-1 Serial Control Register 04 (SCR04) Initial value 0 0 0 0 0 0 0 0 R/W R/W bit8 Disable Transmission Enable Transmission bit9 Disable Reception...
Page 639 Table 4-2 Functions of each bit of control register 04 (SCR04) Bit name bit15 PEN: Parity enable bit14 P: Parity selection bit bit13 SBL: Stop bit length selection bit bit12 CL: Data length selection bit bit11 AD: Address/Data selection bit * bit10 CRE: Clear reception error flags bit...
Page 640 Chapter 32 USART (LIN / FIFO) 4.USART Registers 4.2 Serial Mode Register 04 (SMR04) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. Figure 4-2 Conﬁguration of the Serial Mode register 04 (SMR04) R/W R/W R/W R/W Readable and writable Write only...
Page 641 Table 4-4 Bit function of the Serial Mode register 04 (SMR04) Bit name bit7 MD1 and MD0: bit6 Operation mode selection bits bit5 OTO: One-to-one external clock selection bit bit4 EXT: External clock selection bit bit3 REST: Restart of transmission reload counter bit bit2 UPCL: USART...
Page 642 Chapter 32 USART (LIN / FIFO) 4.USART Registers Figure 4-3 Conﬁguration of the Serial Status register 04 (SSR04) Readable and writable Flag is read only, writing to it has no effect Initial value Initial value 0 0 0 0 1 0 0 0 R/W R/W bit8 Disables Transmission Interrupt...
Page 643 Table 4-5 Functions of each bit of status register 04 (SSR04) Bit name • This bit is set to 1 when a parity error occurs during reception and is bit15 PE: Parity error flag bit • A reception interrupt request is output when this bit and the RIE bit are 1. •...
Page 644 Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-5 Functions of each bit of status register 04 (SSR04) Bit name bit8 TIE: Transmission interrupt request enable bit 4.4 Reception and Transmission Data Register (RDR04 / TDR04) The reception data register (RDR04) holds the received data. The transmission data register (TDR04) holds the transmission data.
Page 645 enabled, a transmission interrupt is generated. Write the next part of transmission data when a transmission interrupt is generated or the TDRE bit is 1. 4.5 Extended Status/Control Register (ESCR04) This register provides several LIN functions, direct access to the SIN04 and SOT04 pin and setting for USART synchronous clock mode.
Page 646 Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-6 Function of each bit of the Extended Status/Control Register (ESCR4) Bit name bit15 LBIE: LIN break detection interrupt enable bit bit14 LBD: LIN break detected flag bit13 LBL1/0: LIN break bit12 length selection bit11...
Page 647 Figure 4-6 Conﬁguration of the Extended Communication Control Register (ECCR04) W R/W R/W Readable and writable Flag is read only Flag is write only Indeterminate Initial value Initial value 0 0 0 0 0 0 X X bit0 TBI * Transmission bus idle Transmission is ongoing no transmission activity...
Page 648 Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-8 Function of each bit of the Extended Communication Control Register (ECCR04) Bit name bit7 INV: Invert serial data bit6 LBR: Set LIN break bit5 MS: Master/Slave mode selection bit bit4 SCDE: Serial clock delay enable bit bit3...
Page 649 Figure 4-7 Baudrate Reload Counter Register 0 and 1 (BGR04 / 14) R/W R/W R/W Readable and writable The Baud Rate / Reload Counter Registers determine the division ratio for the serial clock. Both registers can be read or written via byte or word access. R/W R/W R/W R/W R/W bit 0 - 7...
Page 650 Chapter 32 USART (LIN / FIFO) 4.USART Registers 4.8 FIFO Control Register (FCR04) R/W R/W R/W R/W Readable and writable Flag is read only, writing to it has no effect Initial value Figure 4-8 Configuration of FIFO control registe Initial value 0 0 0 0 0 0 0 0 R/W R/W bit 0...
Page 651 Table 4-9 Functions of each bit of ﬁfo control register (FCR4) Bit name bit 0 SVD: select Valid Data Fifo read bit 1 ETX: enable TX fifo bit 2 ERX: enable RX fifo bit 3 bit 4 RXL0: RX Triggerlevel bit 0 bit 5 RXL1: RX Triggerlevel bit 1...
Page 652 Chapter 32 USART (LIN / FIFO) 4.USART Registers 4.9 FIFO Status Register (FSR04) Figure 4-9 Conﬁguration of FIFO status register Flag is read only, writing to it has no effect Initial value (Note) The FSR04[4:0] FIFO valid data bits indicates the number of stored receptions (SVD=0) or pending transmissions (SVD=1) in the FIFO buffer.
Page 653 Table 4-10 Functions of each bit of FIFO status Register Bit name • shows the number of valid FIFO - Data bit 0 FIFO: number of valid Data • shows the number of valid FIFO - Data bit 1 FIFO: number of valid Data •...
Page 654: Usart Interrupts
Chapter 32 USART (LIN / FIFO) 5.USART Interrupts 5. USART Interrupts The USART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDR04), or a reception error occurs. •...
Page 655 • - Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE • - Parity error, i. e. a wrong parity bit was detected: PE If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR04: RIE = 1), a reception interrupt request is generated.
Page 656: Reception Interrupt Generation And Flag Set Timing
Chapter 32 USART (LIN / FIFO) 5.USART Interrupts Transmission data Reception data Reception IRQ : Start bit 5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: Completion of reception (SSR04: RDRF) and occurrence of a reception error (SSR04: PE, ORE, or FRE).
Page 657: Transmission Interrupt Generation And Flag Set Timing
"7p1" and "8N1" (p = "E" [even] or "O" [odd]), all in NRZ data format (ECCR04: INV = 0). (Note) **ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and another data frame is read.
Page 658: Usart Baud Rates
Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates ■ Transmission Interrupt Request Generation Timing If the TDRE flag is set to 1 when a transmission interrupt is enabled (SSR04: TIE=1) a transmission interrupt request is generated. A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to 1 as its initial value.
Page 659: Setting The Baud Rate
Figure 6-1 Baud rate selection circuit (reload counter) SCK04 (external clock input) REST 6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the baud rate The both 15-bit Reload Counters are programmed by the Baud Rate Generator Registers 1 and 0 (BGR14, 04).
Page 660 Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates ■ Suggested Division Ratios for different machine speeds and baud rates The following settings are suggested for different MCU clock speeds and baud rates: Table 6-1 Suggested Baud Rates and reload values at different machine speeds. 8 MHz 10 MHz Baud...
Page 661: Restarting The Reload Counter
Figure 6-2 Counting example of the reload counters Transmission/ Reception Clock Reload Count Transmission/ Reception Clock Reload Count (Note) The falling edge of the Serial Clock Signal always occurs after | (v + 1) / 2 |. 6.2 Restarting the Reload Counter The Reload Counter can be restarted because of the following reasons: Transmission and Reception Reload Counter: •...
Page 662 Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates Clock Reload Counter Clock Outputs REST Reload Value Read BGR0/1 Data In this example the number of MCU clock cycles (cyc) after REST is then: cyc = v - c + 1 = 100 - 90 + 1 = 11, where v is the reload value and c is the read counter value.
Page 663: Usart Operation
7. USART Operation USART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. ■ Operation of USART •...
Page 664 Chapter 32 USART (LIN / FIFO) 7.USART Operation TXE) and reception (SCR04: RXE). If each of the operations is disabled, stop it as follows: • If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and read the received data of the reception data register (RDR04).
Page 665 If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur immediately. ■...
Page 666 Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ Transfer data format In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR04) is 0. A special clock signal belongs to the data format in mode 2. The figure below illustrates the data format during a transmission in the synchronous operation mode.
Page 667: Error Detection
SPI). This will make sure, that the transmission data is valid and stable at any falling clock edge. (Necessary, if the receiving device samples the data at falling clock edge). This function is disabled when CCO is enabled. If the Serial Clock Edge Select (SCES) bit of the ESCR is set, the USARTs clock is inverted and thus samples the reception data at the falling clock edge.
Page 668 Chapter 32 USART (LIN / FIFO) 7.USART Operation • BDS: "0" for LSB first, "1" for MSB first • RIE: "1" if interrupts are used "0" if not • TIE: "1" if interrupts are used "0" if not • Extended Communication Register (ECCR04): •...
Page 669 LIN break Interrupt is enabled (LBIE = 1) USART will generate a reception interrupt, if a synchronization break of the LIN master is detected, and indicates it with the LBD flag of the ESCR04. Writing a "0" to this bit clears the interrupt.
Page 670: Direct Access To Serial Pins
Chapter 32 USART (LIN / FIFO) 7.USART Operation old serial clock (SIN) (IRQ0) LBIE Internal Signal to ICU IRQ from RDRF (IRQ0) Read by CPU Reception Interrupt enable LIN break begins LIN break detected and Interrupt IRQ cleared by CPU (LBD -> 0) IRQ cleared: Begin of Input Capture IRQ cleared: Calculate &...
Page 671 7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in figure Figure 7-8 Settings for USART operation mode 0 and 2 SMR0 SCR04,...
Page 672 Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ Master-slave Communication Function The settings shown in figure Figure 7-10 Settings for USART operation mode 1 SMR0 SCR04, Mode 1 SSR04, PE ORE FRE RDRF TDRE BDS RIE TDR04/RDR04 Mode 1 Bit is used x Bit is not used 0 / 1 Set bit to 0 / 1...
Page 673 Table 7-3 Selection of the master-slave communication function Operation mode Master Address transmis- sion and Mode 1 reception (send AD- Data trans- bit) mission and recep- tion ■ Communication Procedure When the master CPU transmits address data, communication starts. The A/D bit in the address data is set to 1, and the communication destination slave CPU is selected.
Page 674 Chapter 32 USART (LIN / FIFO) 7.USART Operation Figure 7-12 Master-slave communication ﬂowchart (Master CPU) Start Set operation mode 1 Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits.
Page 675 7.7 LIN Communication Function USART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-Master-Slave Communication Function The settings shown in the figure below are required to operate USART in LIN communication mode (operation mode 3).
Page 676 Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ USART as master device START Initialization: Set Operat. mode 3 (8N1 data format) TIE = 0, RIE = 0 Send Message? Send Synch Break: write "1" to ECCR: LBR; TIE = 1; Send Synch Field: TDR = 0x55 TDRE = 1...
Page 677 ■ USART as slave device Figure 7-16 USART LIN slave ﬂow chart (part1) START Initialization: Set Operat. mode 3 (8N1 data format) RIE = 0; LBIE = 1; RXE = 0 waiting (slave action) LBD = 1 LIN break interrupt Awaiting message from LIN master.
Page 678 Chapter 32 USART (LIN / FIFO) 7.USART Operation Figure 7-17 USART LIN slave ﬂow chart (part 2) continuation from previous page Send Wake up signal RIE = 0 Wake up TIE = 1 from CPU? TDR = 0x80 RIE = 1 0x00, 0x80, RIE = 0 or 0xC0...
Page 679: Notes On Using Usart
This is needed to detect safely the minimum of 11 bit times of a LIN synch break. ■ Software compatibility Although USART is similar to older Fujitsu-UARTs it is not software compatible to them. The programming models may be the same, but the structure of the registers differ. Furthermore the setting of the baud rate is now determined by a reload value instead of selecting a preset value.
Page 680 Chapter 32 USART (LIN / FIFO) 8.Notes on using USART ■ Baud Rate Detection Using the Input Capture Units The USARTs provide the signal LSYN that can be connected to the ICU so that LSYN’s pulse length can be measured to derive the baud rate. The connection of the LSYN signals to the ICUs is controlled by the Port 14 function register PFR and EPFR : Pin IN4 LIN-UART4...
Page 681: Chapter 33 I2C Controller
Chapter 33 I C Controller 1. Overview The I C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I bus. ■ Features • Master/slave transmitting and receiving functions • Arbitration function •...
Page 682 Chapter 33 I2C Controller 1.Overview ■ Block Diagram ICCR ICCR IBSR IBCR BEIE INTE IBCR Start Master ACK enable GC-ACK enable GCAA IBSR ISMK ENSB ITMK ENTB C enable R-Bus Clock (CLKP) Clock Divider 1 2 3 4 5 ... 32 Clock Selector Clock Divider 2 (by 12) SCL Duty Cycle Generator...
Page 683: I2C Interface Registers
2. I C Interface Registers This section describes the function of the I ■ Bus Control Register (IBCR0) Bus control register Address : 0000D0 Read/write ⇒ (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value⇒ ■ Bus Status Register (IBSR0) Bus status register Address : 0000D1 Read/write ⇒...
Page 684 Chapter 33 I2C Controller 2.I2C Interface Registers ■ Seven bit slave address MasK register (ISMK0) Seven Bit Address Mask register Address : 0000D6 Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value⇒ ■ Seven Bit slave Address register (ISBA0) Seven Bit Address register Address : 0000D7 Read/write ⇒...
Page 685 2.1 Bus Control Register (IBCR0) The bus control register (IBCR0) has the following functions: • Interrupt enabling flags • Interrupt generation flag • Bus error detection flag • Repeated start condition generation • Master / slave mode selection • General call acknowledge generation enabling •...
Page 686 Chapter 33 I2C Controller 2.I2C Interface Registers [bit 14] BEIE (Bus Error Interrupt Enable) This bit enables the bus error interrupt. It can only be changed by the user. Bus error interrupt disabled. Bus error interrupt enabled. Setting this bit to ‘1’ enables MCU interrupt generation when the BER bit is set to ‘1’. [bit 13] SCC (Start Condition Continue) This bit is used to generate a repeated start condition.
Page 687 This bit is not valid when receiving address bytes in slave mode - if the interface detects its 7 or 10 bit slave address, it will acknowledge if the corresponding enable bit (ENTB in ITMK0 or ENSB in ISMK0) is set. Write access to this bit should occur during an interrupt (INT=‘1’) or if the bus is idle (BB=‘0’...
Page 688 Chapter 33 I2C Controller 2.I2C Interface Registers While this bit is ‘1’ the SCL line will hold an ‘L’ level signal. Writing ‘0’ to this bit clears the setting, releases the SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated. Additionally, this bit is cleared if a ‘1’...
Page 689 2.2 Bus Status Register (IBSR0) The bus status register (IBSR0) has the following functions: • Bus busy detection • Repeated start condition detection • Arbitration loss detection • Acknowledge detection • Data transfer direction indication • Addressing as slave detection •...
Page 690 Chapter 33 I2C Controller 2.I2C Interface Registers • a repeated start condition is generated by another master in the first bit of a data byte • the interface could not generate a start or stop condition because another slave pulled the SCL line low before [bit 4] LRB (Last Received Bit) This bit is used to store the acknowledge message from the receiving side at the transmitter side.
Page 691 General call address received as slave. This bit is cleared by a (repeated-) start or stop condition. [bit 0] ADT (Address Data Transfer) This bit indicates the detection of an address data transfer. Incoming data is not address data (or bus is not in use). Incoming data is address data.
Page 692 Chapter 33 I2C Controller 2.I2C Interface Registers 2.3 Ten Bit Slave Address Register (ITBA0) This register (ITBAH0 / ITBAL0) designates the ten bit slave address. Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0). Ten Bit Address high byte Address : 0000D2 Read/write ⇒...
Page 693 2.4 Ten Bit Address Mask Register (ITMK0) This register contains the ten bit slave address mask and the ten bit slave address enable bit. Ten Bit Address Mask high byte Address : 0000D4 Read/write ⇒ (R/W) (R) Default value⇒ Ten Bit Address Mask low byte Address : 0000D5 Read/write ⇒...
Page 694 Chapter 33 I2C Controller 2.I2C Interface Registers IBSR0 register is ‘1’. Note: If the address mask is changed after the interface had been enabled, the slave address should also be set again since it could have been overwritten by a previously received slave address.
Page 695 2.5 Seven Bit Slave Address Register (ISBA0) This register designates the seven bit slave address. Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0). Seven Bit Address register Address : 0000D7 Read/write ⇒ Default value⇒...
Page 696 Chapter 33 I2C Controller 2.I2C Interface Registers 2.6 Seven Bit Slave Address Mask Register (ISMK0) This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0). Seven Bit Address Mask register Address : 0000D6 Read/write ⇒...
Page 697 2.7 Data Register (IDAR0) Data register Address : 0000D9 Read/write ⇒ Default value⇒ [bit 15] - [bit 8] Not used. These bits always read ‘0’. [bit 7] - [bit 0] Data bits (D7-D0) The data register is used in serial data transfer, and transfers data MSB-first. This register is double buffered on the write side, so that when the bus is in use (BB=‘1’), write data can be loaded to the register for serial transfer.
Page 698 Chapter 33 I2C Controller 2.I2C Interface Registers 2.8 Clock Control Register (ICCR0) The clock control register (ICCR0) has the following functions: • Enable IO pad noise filters • Enable I C interface operation • Setting the serial clock frequency Clock Control register Address : 0000DA Read/write ⇒...
Page 699 Bitrate = (Note) Because of the noise filter (depending on relationship between external signal and internal clock it will cause different delays ) the divider in the second formula can vary between (12n + 19) and (12n + 20). ■ Prescaler settings: Table 2-1 I2C Prescaler Settings Do not use n=0 prescaler setting, it violates SDA/SCL timings! The table below shows SCL frequency measurement results for the most common R-bus clock settings and...
Page 700 Chapter 33 I2C Controller 2.I2C Interface Registers ■ SCL Waveforms Address sending Data sending Time unit: Prescaler cycles Figure shows the SCL waveform for sending of address and data bits. The timings given in the figure are prescaler periods (e.g. ‘9’ means 9 times the prescaler count based on the R-Bus clock).
Page 701: I2C Interface Operation
3. I C Interface Operation The I C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial clock line (SCL). The I C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines, enabling wired logic applications.
Page 702 Chapter 33 I2C Controller 3.I2C Interface Operation ■ Slave Address Masking Only the bits set to ‘1’ in the mask registers (ITMK0 / ISMK0) are used for address comparision, all other bits are ignored. The received slave address can be read from the ITBA0 (if ten bit address received, RAL=‘1’) or ISBA0 (if seven bit address received, RAL=‘0’) register if the AAS bit in the IBSR0 register is ‘1’.
Page 703: Programming Flow Charts
4. Programming Flow Charts ■ Example Of Slave Addressing And Sending Data Addressing a 7 bit slave Clear BER bit (if set); Enable Interface EN:=1; IDAR0 := sl.address<<1+RW; MSS := 1; INT := 0 Ready to send data Slave did not ACK Generate repeated start or stop condition...
Page 704 Chapter 33 I2C Controller 4.Programming Flow Charts ■ Example Of Receiving Data Start Address slave for read Clear ACK bit in IBCR0 if it’s the last byte to read from slave; INT := 0 INT=1? Bus error BER=1? reenable IF Last byte transferred? Transfer End...
Page 705 ■ Example Of An Interrupt Handler Transfer failed remember to retry New data transfer starts at next INT Change ACK bit if necessary Read received byte from IDAR0 register Change ACK bit if necessary Start INT=1? BER=1? GCA=1? AAS=1? AL=1? ADT=1? TRX=1? Put next byte to be...
Page 706 Chapter 33 I2C Controller 4.Programming Flow Charts...
Page 707: Chapter 34 Can Controller
Chapter 34 CAN Controller 1. Overview The CAN performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer additional transceiver hardware is required.
Page 708: Register Description
Chapter 34 CAN Controller 2.Register Description 2. Register Description This section lists the CAN registers and describes the function of each register in detail. 2.1 Programmer’s Model The CAN module allocates an address space of 256 bytes (64 words). The CAN registers can be accessed from the CPU in byte, halfword and word.
Page 709 Address Base-addr + IF1 Command Request 0x10 bit[15:8] Busy Reset: 0x00 Base-addr + IF1 Mask 2 0x14 bit[15:8] MXtd,MDir,Msk[28:24] Reset: 0xFF Base-addr + IF1 Arbitration 2 0x18 bit[15:8] MsgVal,Xtd,Dir,ID[28:24] Reset: 0x00 Base-addr + IF1 Message Control 0x1C bit[15:8] see descr. IF1MCTR Reset: 0x00 Base-addr + IF1 Data A1...
Page 710 Chapter 34 CAN Controller 2.Register Description Address Base-addr + IF2 Command Request 0x40 bit[15:8] Busy Reset: 0x00 Base-addr + IF2 Mask 2 0x44 bit[15:8] MXtd,MDir,Msk[28:24] Reset: 0xFF Base-addr + IF2 Arbitration 2 0x48 bit[15:8] MsgVal,Xtd,Dir,ID[28:24] Reset: 0x00 Base-addr + IF2 Message Control 0x4C bit[15:8] see descr.
Page 711 Address Base-addr + Transmission Request Register 2 0x80 bit[15:8] TxRqst[32-25] Reset: 0x00 Base-addr + 0x84 Base-addr + New Data 2 0x90 bit[15:8] NewDat[32-25] Reset: 0x00 Base-addr + 0x94 Base-addr + Interrupt Pending 2 0xA0 bit[15:8] IntPnd[32-25] Reset: 0x00 Base-addr + 0xA4 Base-addr + Message Valid 2...
Page 712 Chapter 34 CAN Controller 2.Register Description Additionally the busoff state is reset and the output CAN_TX is set to recessive(HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialisation. The CAN does not influence the CAN bus until the CPU resets Init to ‘0’.
Page 713 ■ Function of the CAN Control Register (CTRLR) [bit15 - bit8] Reserved Bits [bit7] Test Test Mode Enable Normal Operation. Test Mode. [bit6] Conﬁguration Change Enable The CPU has no write access to the Bit Timing Register. The CPU has write access to the Bit Timing Register (while Init = 1) [bit5] Disable Automatic Retransmission Automatic Retransmission of disturbed messages enabled.
Page 714 Chapter 34 CAN Controller 2.Register Description recovery sequence, the Error Management Counters will be reset. (Note) During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the busoff recovery sequence.
Page 715 ■ Function of the Status Register (STATR) [bit15 - bit8] Reserved Bits [bit7] BOff Busoff Status The CAN module is not busoff. The CAN module is in busoff state. [bit6] EWarn Warning Status oth error counters are below the error warning limit of 96. At least one of the error counters in the EML has reached the error warning limit of 96.
Page 716 Chapter 34 CAN Controller 2.Register Description Bit0Error CRCError unused The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error. The unused code ‘7’...
Page 717 ■ Function of the Error Counter (ERRCNT) [bit15] Receive Error Passive The Receive Error Counter is below the error passive level. The Receive Error Counter has reached the error passive level as deﬁned in the CAN Speciﬁcation. [bit14 - bit8] REC6-0 Receive Error Counter Actual state of the Receive Error Counter.
Page 718 Chapter 34 CAN Controller 2.Register Description ■ Function of the Bit Timing Register (BTR) [bit15] Reserved bit [bit14 - bit12] TSeg2 The time segment after the sample point 0x0-0x7 Valid values for TSeg2 are [ 0 … 7 ]. The actual interpretation by the hard- ware of this value is such that one more than the value programmed here is used.
Page 719 ■ Function of the Test Register (TESTR) [bit15-bit8] Reserved bits [bit7] Monitors the actual value of the CAN_RX Pin The CAN bus is dominant (CAN_RX = ‘0’). The CAN bus is recessive (CAN_RX = ‘1’). [bit6-bit5] Tx1-0 Control of CAN_TX pin Reset value, CAN_TX is controlled by the CAN Core.
Page 720 Chapter 34 CAN Controller 2.Register Description ■ BRP Extension Register (BRPER) BRP Extension Register high byte Address : Base + 0x0C Read/write ⇒ Default value⇒ BRP Extension Register low byte Address : Base + 0x 0D Read/write ⇒ Default value⇒ ■...
Page 721 Address CAN Base + 0x10 CAN Base + 0x12 CAN Base + 0x14 CAN Base + 0x16 CAN Base + 0x18 CAN Base + 0x1A CAN Base + 0x1C CAN Base + 0x20 CAN Base + 0x32 CAN Base + 0x22 CAN Base + 0x30 CAN Base + 0x24 CAN Base + 0x36...
Page 722 Chapter 34 CAN Controller 2.Register Description ■ Function of the IFx Command Request Registers (IFxCREQ) [bit15] BUSY Busy Flag Reset to zero when read/write action has ﬁnished Set to one when writing to the IFx Command Request Register [bit14-bit8] Reserved Bits [bit5-bit0] Message Number (for 32 message buffer CANs) 0x00...
Page 723 ■ Function of the IFx Command Mask Register (IFxCMSK) [bit15-bit8] Reserved Bits [bit7] WR/RD Write / Read Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
Page 724 Chapter 34 CAN Controller 2.Register Description Data Bytes 4-7 unchanged. Transfer Data Bytes 4-7 to Message Object. (Note) If a transmission is requested by programming bit TxRqst/NewDat in the IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will be ignored. •...
Page 725 IFx Mask 2 Register high byte Address : Base + 0x14 H & IFx Mask 2 Register low byte Address : Base + 0x 15 H & IFx Mask 1 Register high byte Address : Base + 0x16 H & IFx Mask 1 Register low byte Address : Base + 0x 17 H &...
Page 726 Chapter 34 CAN Controller 2.Register Description IFx Arbitration 1 Register high byte Address : Base + 0x1A H & IFx Arbitration 1 Register low byte Address : Base + 0x 1B H & ■ IFx Message Control Register (IFxMCTR) IFx Message Control Register high byte Address : Base + 0x1C Base + 0x4C H &...
Page 727 2.5 Message Object in the Message Memory There are 32 Message Objects (up to 128 depending on the implementation) in the Message RAM. To avoid conflicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers.
Page 728 Chapter 34 CAN Controller 2.Register Description The 29-bit (“extended”) Identiﬁer will be used for this Message Object. MXtd Mask Extended Identiﬁer The extended identiﬁer bit (IDE) has no effect on the acceptance ﬁltering The extended identiﬁer bit (IDE) is used for acceptance ﬁltering. (Note) When 11-bit (“standard”) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18.
Page 729 MsgLst Message Lost (only valid for Message Objects with direction = receive) No message lost since last time this bit was reset by the CPU. The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
Page 730 Chapter 34 CAN Controller 2.Register Description (Note) Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a reception, byte Data 7 is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
Page 731 0x8001- unused. 0xFFFF If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If IntId is different from 0x0000 and IE is set, the interrupt line to the CPU is active. The interrupt line remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
Page 732 Chapter 34 CAN Controller 2.Register Description If more than 32 message buffers are implemented, the following table gives an overview about the additional flags: Table 2-1 Additional ﬂags when more than 32 message buffers exist TREQR 4 & 3 TxRqst 64-33 (address 0x84) TREQR 6 &...
Page 733 These registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the CPU can check for which Message Object the data portion was updated. The NewDat bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.
Page 734 Chapter 34 CAN Controller 2.Register Description This message object is the source of an interrupt. These registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the CPU can check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame.
Page 735 MsgVal32-1 Message Valid Bits (of all Message Objects) This Message Object is ignored by the Message Handler. This Message Object is conﬁgured and should be considered by the Message Handler. These registers hold the MsgVal bits of the 32 Message Objects. By reading out the MsgVal bits, the CPU can check which Message Object is valid.
Page 736: Functional Description
Chapter 34 CAN Controller 3.Functional Description 3. Functional Description This chapter provides an overview of the CAN module’s operating modes and how to use them. 3.1 Software Initialisation The software initialization is started by setting the bit Init in the CAN Control Register, either by software or by a hardware reset, or by going Bus_Off.
Page 737 Automatic Retransmission mode is enabled by setting the bit DAR in the CAN Control Register to one. In this operation mode the programmer has to consider the different behaviour of bits TxRqst and NewDat in the Control Registers of the Message Buffers: When a transmission starts bit TxRqst of the respective Message Buffer is reset, while bit NewDat remains set.
Page 738 Chapter 34 CAN Controller 3.Functional Description This mode is provided for self-test functions. To be independent from external stimulation, the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop Back Mode. In this mode the CAN Core performs an internal feedback from its Tx output to its Rx input. The actual value of the CAN_RX input pin is disregarded by the CAN Core.
Page 739 Chapter 34 CAN Controller 3.Functional Description The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is requested by writing the Busy bit of the IF1 Command Request Register to ‘1’. The IF1 Registers are locked while the Busy bit is set.
Page 740: Can Application
Chapter 34 CAN Controller 4.CAN Application 4. CAN Application This section describes how to use the CAN module in the application 4.1 Management of Message Objects The configuration of the Message Objects in the Message RAM will (with the exception of the bits MsgVal, NewDat, IntPnd, and TxRqst) not be affected by resetting the chip.
Page 741 Chapter 34 CAN Controller 4.CAN Application Figure 4-1 Data Transfer between IFx Registers and Message RAM After the partial write of a Message Object, that Message Buffer Registers that are not selected in the Command Mask Register will set to the actual contents of the selected Message Object. After the partial read of a Message Object, that Message Buffer Registers that are not selected in the Command Mask Register will be left unchanged.
Page 742 Chapter 34 CAN Controller 4.CAN Application 4.5 Acceptance Filtering of Received Messages When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the Message Handler FSM starts the scanning of the Message RAM for a matching valid Message Object.
Page 743 MsgVal Data Mask appl. appl. appl. The Arbitration Registers (ID28-0 and Xtd bit) are given by the application. They define the identifier and type of the outgoing message. If an 11-bit Identifier (“Standard Frame”) is used, it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded.
Page 744 Chapter 34 CAN Controller 4.CAN Application ID18, ID17 - ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received, ID17 - ID0 will be set to ‘0’. If the RxIE bit is set, the IntPnd bit will be set when a received Data Frame is accepted and stored in the Message Object.
Page 745 4.15 Reading from a FIFO Buffer When the CPU transfers the contents of Message Object to the IFx Message Buffer registers by writing its number to the IFx Command Request Register, the corresponding Command Mask Register should be programmed the way that bits NewDat and IntPnd are reset to zero (TxRqst/NewDat = ‘1’ and ClrIntPnd = ‘1’).
Page 746 Chapter 34 CAN Controller 4.CAN Application The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s interrupt priority decreases with increasing message number. A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by reading the Status Register.
Page 747 Parameter Sync_Seg Prop_Seg Phase_Seg1 Phase_Seg2 Table 4-1 Parameters of the CAN Bit Time (Note) This table describes the minimum programmable ranges required by the CAN protocol. Figure 4-5 Bit Timing Range Remark [1..32] deﬁnes the legth of the time quantum tq 1 tq ﬁxed length, synchronisation of us into system clock [1..8] tq...
Page 748 Chapter 34 CAN Controller 4.CAN Application...
Page 749: Chapter 35 Free-Run Timer
Chapter 35 Free-Run Timer 1. Overview The free-run timer consists of a 16-bit timer (up counter) and control circuits. The free-run timer can be used with the input capture and the output compare. Internal clock External clock 2. Features • Format: 16-bit up counter •...
Page 750: Configuration Diagram
Chapter 35 Free-Run Timer 3.Conﬁguration Diagram 3. Configuration Diagram Free-run Timer Count clock CLK1-0 TCCS: bit 1-0 CLKP / 4 CLKP / 4 CLKP / 16 CLKP / 16 CLKP / 32 CLKP / 32 CLKP / 64 CLKP / 64 Peripheral clock Divider C LKP...
Page 751: Registers
4. Registers 4.1 TCCS: Timer Control Register A register for controlling the operation of the free-run timer. • TCCS0 (free-run timer 0): Address 01F3h (access: • TCCS1 (free-run timer 1): Address 01F7h (access: • TCCS2 (free-run timer 2): Address 01FBh (access: •...
Page 752 Chapter 35 Free-Run Timer 4.Registers • bit4: Stop counting STOP Enable counting Disable count (stop) • When the count stop bit is set to “1”, the free-run timer stops. • When the output compare is being used, if the free-run timer stops, the output compare also stops. Operation...
Page 753 • bit3: Clear mode MODE Clear the free-run timer by the reset and the clear bit (CLR). Clear the free-run timer by the match with the reset, the clear bit (CLR), and the compare register value of the output compare (OCCP). •...
Page 754 Chapter 35 Free-Run Timer 4.Registers 4.2 TCDT: Timer Data Register This register can read 16-bit free-run timer count values. • TCDT0 (free-run timer 0): Address 01F0h (access: • TCDT1 (free-run timer 1): Address 01F4h (access: • TCDT2 (free-run timer 2): Address 01F8h (access: •...
Page 755: Operation
5. Operation 5.1 Count Operation of the Free-run Timer (Internal clock) Peripheral clock (CLKP) Count timing The count of the free-run timer FFFFh The count of the free-run timer 0000 h Reset The overflow and the interrupt request Clearing the free-run timer (1) Reset (2) Clearing of the free-run timer by reset.
Page 756 Chapter 35 Free-Run Timer 5.Operation 5.2 Various Clear Operations of the Free-run Timer The count of the free-run timer 0000 h Reset Clear The enable/disable of the operation (software) Peripheral clock (CLKP) Count timing Count value Compare value Compare-match Clear operations of the free-run timer (4 types) (1) Reset (2) Clear by software (3) Clear by the compare-match...
Page 757: Setting
6. Setting Table 6-1 Setting Required in Order to Use the Free-run Timer Setting Setting of the initialization conditions of the timer Setting of the count clock Selection of the internal clock Selection of the external clock Start the count operation In the case of the external clock Set the clock input pin (CK) as the input.
Page 758 Chapter 35 Free-Run Timer 7.Q & A 7. Q & A 7.1 What are the types of the internal clock, and how do I select? There are 4 types of internal clocks, and these are set by the clock selection bit (TCCS.ECLK) and the count clock bit (TCCS.CLK [1:0]).
Page 759 7.4 How do I clear the free-run timer? You can clear the free-run timer by performing the following operations: • Set with clear bit (TCCS.CLR). Operation To clear the free-run timer • How to clear the free-run timer when the free-run timer value and the compare-register value match Set with the timer initialization condition bit (TCCS.MODE).
Page 760 Chapter 35 Free-Run Timer 7.Q & A Use interrupt request enable bit (TCCS.IVFE) to enable interrupts. Disable interrupts Enable interrupts Use interrupt request bit (TCCS.IVF) to clear interrupt requests. Clear interrupt requests 7.8 How do I stop the free-run timer? Set with count operation bit (TCCS.STOP).
Page 761: Caution
8. Caution • Clearing the free-run timer • When you reset (the INIT pin input, the watchdog reset, the software reset), the counter is initialized to “0000” and the counting is stopped. • When the free-run timer is cleared by software, the counter is cleared and the clear request is generated almost at the same time.
Page 762 Chapter 35 Free-Run Timer 8.Caution...
Page 763: Chapter 36 Input Capture
Chapter 36 Input Capture 1. Overview Input Capture records the free-run timer count value using timing detected from an external signal. It is then possible to calculate the time between signals using the record of the repeated count. 2. Features •...
Page 764: Configuration
Chapter 36 Input Capture 3.Conﬁguration 3. Configuration Input capture 0-1 Edge detection polarity EG01 -00 No edge detection Rising edge detection From port Falling edge detection data register Both edges detection P14 PFR: bit 0 GP Port ICU input Edge detection circuit ICU0 / P14.0 Port read Port read...
Page 765: Register
4. Register 4.1 IPCP: Input Capture Data Register A register that, using changes in an external signal as a trigger, stores the free-run timer count and can read it out later. • IPCP0 (Input capture 0): Address 0184h (Access: • IPCP1 (Input capture 1): Address 0186h (Access: •...
Page 766 Chapter 36 Input Capture 4.Register 4.2 ICS: Input Capture Control Register A register for controlling input capture • ICS01 (Input capture 0-1): Address 0181h (Access: • ICS23 (Input capture 2-3): Address 0183h (Access: • ICS45 (Input capture 4-5): Address 02D1h (Access: •...
Page 767 • bit3-bit2: Input capture 1 active edge selection EG11 EG10 Stop input capture Rising edge Falling edge Both edges (rising edge and falling edge) • Select the active capture edge for the input capture signal from external pin (ICU1) • If the active edge selection bit is “00”, input capture 1 is stopped. •...
Page 768: Operation
Chapter 36 Input Capture 5.Operation 5. Operation The input capture operation is described below. 5.1 Capture Timing, Interrupt Timing Input capture Peripheral clock (CLKP) Active edge Free-run timer 0 Capture register Interrupt request FFFFh Free-run timer 0 count 0000 h Reset Input capture...
Page 769 5.2 Input Capture Edge Speciﬁcation and Operation Overflow (IVF) FFFFh Count value C Free-run timer 0 Count value B count value Count value A 0000 h Reset Input capture Capture data Rising Indeterminate register edge Interrupt request Input capture Capture data Falling register edge...
Page 770: Settings
Chapter 36 Input Capture 6.Settings 6. Settings Table 6-1 Settings Necessary for Using Input Capture Settings Free-run timer settings Free-run timer activation Input pin ICU0-ICU7 settings Active edge polarity selection for external input *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Required Settings for ICU Interrupt Settings Input Capture interrupt vector,...
Page 771 7. Q&A 7.1 What are the varieties of active edge polarity for external input, and how do I select them? The active edge polarity varieties consist of rising, falling, and both, for a total of 3, and are set using the external input active edge selection bit (ICS01.EG[01:00]) and (ICS01:EG[11:10]), (ICS23.EG[01:00]) and (ICS23:EG[11:10]), (ICS45.EG[01:00]) and (ICS45:EG[11:10]), (ICS67.EG[01:00]) and (ICS67:EG[11:10]).
Page 772 Chapter 36 Input Capture 7.Q&A Input Capture 6 Address: 0FFE74h Input Capture 7 Address: 0FFE70h Interrupt request flags (ICS01.ICP0), (ICS01.ICP1), (ICS23.ICP0), (ICS23.ICP1), (ICS45.ICP0), (ICS45.ICP1), (ICS67.ICP0), (ICS67.ICP1) are not automatically cleared, so please set the input capture interrupt request flag (ICP1, ICP0) to “0” to clear them before returning from interrupt processing. 7.4 What are the types of interrupts? There is only one kind of interrupt, and it is generated by input signal edge detection.
Page 773 7.6 How do I measure the pulse width of the input signal? • "H" Width measurement: Specify both edges for edge detection. First detect the rising edge, then detect the falling edge. Pulse width = {value recorded during falling (input capture register value) + “10000h”...
Page 774: Caution
Chapter 36 Input Capture 8.Caution 8. Caution • Input capture register The value of the input capture register during reset is indeterminate. Read out of the input capture register must always be done using 16 or 32 bit access. • Read modify write Input capture interrupt request bit (ICP0), (ICP1) will be read as “1”...
Page 775: Chapter 37 Output Compare
Chapter 37 Output Compare 1. Overview Output compare is a feature that compares the value set to the compare register with the count value of the free-run timer, and reverses the level of the pins when they are equal. Compare 0 Free-run Timer Compare 1 2.
Page 776: Configuration Diagram
Chapter 37 Output Compare 3.Conﬁguration Diagram 3. Configuration Diagram Output Compare 0-1 Compare register 0 OCCP0 TCCS2: bit6 0 Overflow not present Overflow present Free-run timer 2 TCDT2 CLR TCCS2:bit2 No effect Clear Compare register 0 OCCP1 CST 1 OCS01: bit1 Disable compare operation Enable compare operation MODE...
Page 777: Registers
4. Registers 4.1 OCS: Output Control Register A register for controlling the operation of output compare. • OCS01 (Output compare 0-1): Address 018Ch (Access: • OCS23 (Output compare 2-3): Address 018Eh (Access: • OCS45 (Output compare 4-5): Address 02DCh (Access: •...
Page 778 Chapter 37 Output Compare 4.Registers • bit7: Interrupt request flag (output compare 1) ICP1 Interrupt request not present Interrupt request present • If free-run timer count value TCDT0 matches the output compare register OCCP1, ICP1 becomes “1”. • Interrupt request is enabled when the interrupt permission bit (ICP1) is set to “1”. •...
Page 779 • bit0: Enable operation requests (output compare 0) CST0 Disable output compare 0 operation Enable output compare 0 operation • A bit that enables a comparison operation between the free-run timer count value and the output compare register (TCDT0 and OCCP0). •...
Page 780 Chapter 37 Output Compare 4.Registers 4.2 OCCP: Compare Register Register that sets the value to be compared to the 16 bit free-run timer count value. • OCCP0 (Compare 0): Address 0190h (Access: • OCCP1 (Compare 1): Address 0192h (Access: • OCCP2 (Compare 2): Address 0194h (Access: •...
Page 781: Operation
5. Operation 5.1 Output Compare Output (Independent Reversal) CMODE=“0” Peripheral clock (CLK) Free-run timer 2 Compare register value Compare-match signal OCU pin output BFFFh BFFFh Free-run timer 0 count 0000 h Free-run timer 2 clear Compare register value BFFFh OCU Output Interrupt request (1) Free-run timer clear/reset (2) Compare value setting...
Page 782 Chapter 37 Output Compare 5.Operation 5.2 Output Compare Output (Cooperative Reversal) CMODE=“1” BFFFh Free-run timer 0 count 4000h 0000h Free-run timer 2 clear Compare register 0 BFFFh Compare register 1 4000h CST 0 CST 1 OCU0 output CMOD=“0” OCU1 output OCU0 output CMOD=“1”...
Page 783: Settings
6. Settings Table 6-1 Settings Necessary for Using Output Compare Settings Free-run timer setting Compare value setting Compare mode setting Stop compare operation Set initial level of compare pin output Set OCU0-OCU7 pins to output Clear free-run timer Enable compare operation (activate) *: For the setting procedure, refer to the section indicated by the number.
Page 784 Chapter 37 Output Compare 7.Q & A 7. Q & A 7.1 How do I set the compare value? Write the compare value to compare registers OCCP0 - OCCP7. 7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output) This is done using compare mode bits (OCS01.CMOD), (OCS23.CMOD), (OCS45.CMOD), (OCS67.CMOD).
Page 785 To enable compare operation 7.4 How do I set the initial level of the compare pin output? Set it with compare pin output specification bit (OCS01.OTD[1:0]), (OCS23.OTD[1:0]), (OCS45.OTD[1:0]), (OCS67.OTD[1:0]). Operation To set compare 0 pin to “L” To set compare 0 pin to “H” To set compare 1 pin to “L”...
Page 786 Chapter 37 Output Compare 7.Q & A 7.5 How do I set the output for compare pins OCU0-OCU7? Set it with port function register (PFR15[7:0]). Operation To set compare 0 pin (OCU0) to output To set compare 1 pin (OCU1) to output To set compare 2 pin (OCU2) to output To set compare 3 pin (OCU3) to output To set compare 4 pin (OCU4) to output...
Page 787 Output Compare 2 Address: 0FFE64h Output Compare 3 Address: 0FFE60h Output Compare 4 Address: 0FFE5Ch Output Compare 5 Address: 0FFE58h Output Compare 6 Address: 0FFE54h Output Compare 7 Address: 0FFE50h Interrupt request flags (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45. ICP[1:0]), (OCS67. ICP[1:0]), are not automatically cleared, so write “0”...
Page 788 Chapter 37 Output Compare 7.Q & A 7.11 How do I enable interrupts? Enabling of interrupts is done with interrupt request permission bit (OCS01. ICE[1:0]), (OCS23. ICE[1:0]), (OCS45. ICE[1:0]), (OCS67. ICE[1:0]). Interrupt disabled Enable interrupts Interrupt requests are cleared with interrupt request bits (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45. ICP[1:0]), (OCS67.
Page 789: Caution
8. Caution • Compare stop space during compare operation As shown below, for one count directly after the compare value is written to the compare register, the compare operation cannot be used. Free-run timer count value Write to compare register Compare register value •...
Page 790 Chapter 37 Output Compare 8.Caution...
Page 791: Chapter 38 Reload Timer
Chapter 38 Reload Timer 1. Overview The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down. The count length is 16 bits. Soft trigger External event Internal clock External event 2.
Page 792: Configuration
Chapter 38 Reload Timer 3.Conﬁguration Reload timer 2 PPG4, PPG5 Reload timer 3 PPG6, PPG7 Reload timer 4 PPG8, PPG9 Reload timer 5 PPG10, PPG11 Reload timer 6 PPG12, PPG13 Reload timer 7 PPG14, PPG15 • A/D converter activation trigger source (Reload timer 7 3.
Page 793 Reload timer 0 (External event count) Trigger (reload + counter activation) TRG TMCSR:bit0 No effect Soft trigger CNTE TMCSR:bit1 TIN0 PFR14.0 GP Port Reload Timer Input To general-purpose From general-purpose port input port output TIN0/ICU0/P14.0 Event source Active edge MOD2-0 Note: For information about ICR registers and interrupt vectors, see No.311)”.
Page 794: Registers
Chapter 38 Reload Timer 4.Registers 4. Registers 4.1 TMCSR: Reload Timer Control Status Register The control status register controls the operation mode of the reload timer and interrupts. • TMCSR0 (Reload timer 0): Address: 001B6H (Access: • TMCSR1 (Reload timer 1): Address: 001BEH (Access: •...
Page 795 • bit9-7: Operation mode selection Reload trigger when internal clock is selected MOD2 MOD1 MOD0 When the selected reload trigger is input, the value of reload register TMRLR is loaded to the down counter and the count operation is started. Count trigger when external event is selected MOD2 MOD1...
Page 796 Chapter 38 Reload Timer 4.Registers interrupt request is enabled (INTE=“1”) an interrupt request is generated. • bit1: Enable timer count CNTE Stop count operation Enable count operation (waiting for activation trigger) If timer count is enabled, it waits for an activation trigger, and when an activation trigger is generated, the count operation starts.
Page 797 • bit0: Software trigger No effect. (The read value is “0”.) Start count operation after data load. If the count operation is enabled (CNTE=“1”) and the software trigger bit is set to “1”, the value of the reload register (TMRLR) is loaded to the down counter and the count operation starts. If the count operation is not enabled (CNTE=“0”), the software trigger has no effect.
Page 798: Operation
Chapter 38 Reload Timer 5.Operation RX/W RX/W RX/W (For information on attributes, see The reload value for the down counter is stored in reload register TMRLR. Please write using half-word access. 5. Operation 5.1 Internal Clock/Reload Mode In reload mode, a pulse with a 50% duty ratio is output. TMRLR Reload data Count clock...
Page 799 5.2 Internal Clock/One-shot Mode In one-shot mode, a one-shot pulse is output. Reload data TMRLR Count clock FFFF Counter CNTE bit Activation trigger (Soft or external event) Data load Underflow TOT output waveform OUTL=0 OUTL=1 When RELD=0 Set reload value to reload register Enable reload timer count operation TOT pin output Generate reload trigger (activation): soft trigger or external event trigger...
Page 800 Chapter 38 Reload Timer 5.Operation 5.3 External Event Clock Reload Mode External event reload mode counts external events and outputs a pulse with a 50% duty ratio. Reload data TMRLR External event (clock) Counter FFFF CNTE bit 0 (Min) Activation trigger (Soft only) Data load Underflow...
Page 801 5.4 External Event Clock/One-shot Mode In external event one-shot mode, external events are counted and a one-shot pulse is output. Reload data TMRLR External event clock Counter FFFF CNTE bit Activation trigger (Soft only) Data load Underflow TOT output waveform OUTL=0 OUTL=1 When RELD=0...
Page 802 Chapter 38 Reload Timer 5.Operation 5.8 Operation when Returning from Stop Mode When returning due to an external interrupt, the reload timer will continue operation from its stopped state. When returning from a reset (INITX), it will return to the initial state (down counter stopped, no TOT pin output).
Page 803: Setting
6. Setting Table 6-1 Settings Necessary for Moving the Reload Timer (Internal Clock Operation) Setting Reload value settings Count clock selection (internal clock selection) Enable reload timer count operation Mode selection (reload /one-shot) Output reversal speciﬁcation Reload trigger selection (activation selection) Soft trigger External trigger (Rising edge/falling edge/both edges)
Page 804 Chapter 38 Reload Timer 6.Setting Table 6-3 Items Necessary for Performing Reload Timer Interrupts Setting Reload timer interrupt vector Reload timer interrupt level setting Reload timer interrupt settings Interrupt request clear Enable interrupt requests *: For the setting procedure, refer to the section indicated by the number. Table 6-4 Settings Necessary for Stopping the Reload Timer Setting Reload timer stop bit setting...
Page 805 7. Q & A 7.1 What is the reload value setting (rewriting) procedure? The reload value is set by the 16 bit reload registers TMRLR0-TMRLR7. The equation for the values to be set is as follows. • Formula TMRLR register value = {reload interval/count clock}-1 •...
Page 806 Chapter 38 Reload Timer 7.Q & A Reload mode, Initial value “L” level output Reload mode, initial value “H” level output (reversed) One-shot mode, counting “H” level output One-shot mode, counting “L” level output (reversed) Set to “0” Set to “1” Set to “0”...
Page 807 7.6 What are the kinds of triggers, and how do I select them? • Selection is done via the trigger selection bit (TMCSR.MOD[2:0]). There are 4 types of reload triggers when an internal clock is selected. Trigger Software trigger (TRG bit set) External trigger from TINx pin (rising edge) External trigger from TINx pin (falling edge) External trigger from TINx pin (both edges)
Page 808 Chapter 38 Reload Timer 7.Q & A TIN6 pin TIN7 pin 7.10 How do I generate an activation trigger? • Generating a soft trigger The setting is done via the software trigger bit (TMCSR.TRG). When the software trigger bit (TGR) is set to“1”, a trigger is generated. To enable operation and activate at the same time, set the count permission bit (TMCSR.CNTE) and the soft trigger bit (TMCSR.TRG) simultaneously.
Page 809 Enabling of interrupts is done via the interrupt request permission bit (TMCSR0.INTE) ~ (TMCSR7.INTE). To disable interrupt requests To enable interrupt requests Clearing of interrupt requests is done via the interrupt request bit (TMCSR0.UF) ~ (TMCSR7.UF). To disable interrupt requests 7.13 How do I stop the reload timer? This setting is done via the reload timer stop bit.
Page 810: Caution
Chapter 38 Reload Timer 8.Caution 8. Caution • Count source select bit (TMCSR.CSL[2:0]) settings not in the table: “100”, “111” are disabled. If they are set, disable the reload timer operation before resetting the count source select bit. • Operation mode bit (TMCSR.MOD2) must be set to “0”. If it is set to “1”, disable the reload timer count operation before resetting it.
Page 811: Chapter 39 Programmable Pulse Generator
Chapter 39 Programmable Pulse Generator 1. Overview Programmable Pulse Generators (PPGs) are used to gain one-shot (rectangular wave) output or pulse width modulation (PWM) output. With their software-programmable cycle and duty capability, the PPGs comfortably fit into broad applications. Count clock 2.
Page 812 Chapter 39 Programmable Pulse Generator 2.Features • Interrupt: Choose from four choices: • Software trigger • Counter borrow (cycle match) • Duty match • Counter borrow (cycle match) or duty match • Activation trigger: • Software trigger • Internal triggers Reload timer output 0 (TOT0) available as trigger for PPG0-PPG3 Reload timer output 1 (TOT1) available as trigger for PPG0-PPG3 Reload timer output 2 (TOT2) available as trigger for PPG4-PPG7...
Page 813: Configuration
3. Configuration PPG (0-3) MDSE PCNH: bit13 Period value PWM operation One shot Count clock CKS1,0 PCNH: bit11,10 CLKP CLKP/4 CLKP/16 CLKP/64 Read-only down counter Peripheral clock Prescaler (CLKP) Enable operation/Stop CNTE PCNH: bit15 Stop Enable operation Trigger selection TSEL03-00 GCN10: bit3-0 GCN20 EN0 bit GCN20 EN1 bit...
Page 814 Chapter 39 Programmable Pulse Generator 3.Conﬁguration Note: For more information about the ICR register and interrupt vector, see “Chapter 24 Interrupt Control (Page No.311)”.
Page 815: Registers
4. Registers 4.1 PCSR: PPG Cycle Setting Register Controls the cycle of the PPG. • PCSR00 (PPG0): Address 0112h (Access: • PCSR01 (PPG1): Address 011Ah (Access: • PCSR02 (PPG2): Address 0122h (Access: • PCSR03 (PPG3): Address 012Ah (Access: • PCSR04 (PPG4): Address 0132h (Access: •...
Page 816 Chapter 39 Programmable Pulse Generator 4.Registers 4.2 PDUT: PPG Duty Setting Register Sets the duty of the PPG output waveform. • PDUT00 (PPG0): Address 0114h (Access: • PDUT01 (PPG1): Address 011Ch (Access: • PDUT02 (PPG2): Address 0124h (Access: • PDUT03 (PPG3): Address 012Ch (Access: •...
Page 817 4.3 PCN: PPG Control Status register Controls the operations and status of PPGs. • PCN00 (PPG0): Address 0116h (Access: Byte, • PCN01 (PPG1): Address 011Eh (Access: Byte, • PCN02 (PPG2): Address 0126h (Access: Byte, • PCN03 (PPG3): Address 012Eh (Access: Byte, •...
Page 818 Chapter 39 Programmable Pulse Generator 4.Registers • Bit 13: Mode selection MDSE PWM operation One-shot operation • When the Mode Selection bit is set to “0”, a PWM operation is enabled to generate pulses in sequence. • When the Mode Selection bit is set to “1”, pulse output takes place only once. •...
Page 819 Interrupt request If the Interrupt Request flag (IRQF) equals “1” and writing “0” to the flag take place at the same time, the setting of the Interrupt Request flag (IRQF=“1”) overrides. • Bit 3-2: Interrupt cause selection IRS1 IRS0 Software trigger, or, trigger input Counter borrow The counter matches the duty value.
Page 820 Chapter 39 Programmable Pulse Generator 4.Registers 4.4 GCN1: General Control register 1 Selects a trigger input to PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15. • GCN10 (PPG0-PPG3): Address 0100h (Access: • GCN11 (PPG4-PPG7): Address 0104h (Access: • GCN12 (PPG8-PPG11): Address 0108h (Access: •...
Page 821 TSEL None of the above • PPG0 to PPG15 as selected are activated when the edge specified by the Trigger Input Edge Selection bits (PCN.EGS[1:0]) are detected during the specified activation trigger. • For detailed setting of each channel see chapter they selected? (Page No.815) Activation trigger speciﬁcation EN0 bit (GCN2 register)
Page 822 Chapter 39 Programmable Pulse Generator 4.Registers 4.5 GCN2: General Control Register 2 Generates PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15 internal trigger levels using software. • GCN20 (PPG0-PPG3): Address 0103h (Access: • GCN21 (PPG4-PPG7): Address 0107h (Access: • GCN22 (PPG8-PPG11): Address 010Bh (Access: •...
Page 823 4.6 PTMR: PPG Timer Register Reads the counts of PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15. • PTMR00 (PPG0): Address 0110h (Access: • PTMR01 (PPG1): Address 0118h (Access: • PTMR02 (PPG2): Address 0120h (Access: • PTMR03 (PPG3): Address 0128h (Access: • PTMR04 (PPG4): Address 0130h (Access: •...
Page 824: Operation
Chapter 39 Programmable Pulse Generator 5.Operation 5. Operation The MB91460 series features a maximum of 16 programmable pulse generators (PPGs), which provide programmable pulse output independently or jointly. The individual modes of operation are described below. 5.1 PWM Operation In PWM operation, variable-duty pulses are generated from the PPG pin. Enable count CNTE Activation trigger...
Page 825 • Equation Period = {Period value (PCSR) + 1} x Count clock Duty = {Duty value (PDUT) + 1} x Count clock Width up to pulse output = {Period value (PCSR) – Duty value (PDUT)} x Count clock 5.2 One-Shot Operation In one-shot operation, one-shot pulses are generated from the PPG pin.
Page 826 Chapter 39 Programmable Pulse Generator 5.Operation 5.3 Restart Operation The restart operation is described below. • Restart available in PWM operation: Trigger N = duty, T = cycle • Restart available in one-shot operation: Rising edge detection Trigger If a restart is not available, the second and subsequent triggers have no effect in both PWM and one-shot operations.
Page 827: Setting
6. Setting Table 6-1 Settings Needed to Start the PPG Setting Period and duty value settings Enable PPG operation. Operation mode selection (PWM/one-shot) Enable restart. Count clock selection PPG output mask selection Trigger selection Software Internal trigger External trigger Output polarity speciﬁcation PPG pin output setting Trigger generation (software trigger) (Reload timer)
Page 828 Chapter 39 Programmable Pulse Generator 6.Setting Table 6-4 Settings Needed to Implement PPG Interrupts PPG interrupt cause selection (Generate an activation trigger, borrow, and duty match) PPG interrupt setting Clear interrupt requests. Enable interrupt requests. *:For the setting procedure, refer to the section indicated by the number. PPG control status (PCN00-PCN15) 7.13 7.14...
Page 829 7. Q & A 7.1 How do I set (rewrite) a cycle and a duty? Period and duty value settings • Set each cycle value in PPG Period Setting Register PCSR. • Set each duty value in PPG Duty Setting Register PDUT. •...
Page 830 Chapter 39 Programmable Pulse Generator 7.Q & A 7.5 What count clocks are available and how are they selected? Count clock selection The count clock is selectable out of the four choices listed below. Use the count clock selection bit (PCN.CKS[1:0]). Count Clock Selection Bit Count Clock...
Page 831 7.7 What activation triggers are available and how are they selected? • Trigger selection • Activation triggers are broadly grouped into software triggers, internal triggers and external triggers. • Software triggers work at all times. • Internal and external trigger availability depends on each device specification. trigger using (GCN1.TSEL2[3:0]), and (GCN1.TSEL3[3:0]).
Page 832 Chapter 39 Programmable Pulse Generator 7.Q & A Triggers are selectable for PPG8, PPG9, PPG10, and PPG11 independently. Internal Trigger To select the EN0 bit of the GCN22 register To select the EN1 bit of the GCN22 register To select the EN2 bit of the GCN22 register To select the EN3 bit of the GCN22 register To select reload timer 4 To select reload timer 5...
Page 833 7.8 How do I invert the output polarity? Output polarity specification The polarity in the normal state can be specified as follows: Use the PPG Output Polarity Specification bit (PCN.OSEL) to set. (“Normal state” means the state in which pulse output is not executed.) Output Level in Normal State To enable “L”...
Page 834 Chapter 39 Programmable Pulse Generator 7.Q & A 7.10 How do I generate an activation trigger? Generating a trigger Methods of generating an activation trigger are described below. • Activating a software trigger Use the Software Trigger bit (PCN.STGR) to set. Write “1”...
Page 835 #118 PPG6 Address: 0FFE24h #119 PPG7 Address: 0FFE20h #120 PPG8 Address: 0FFE1Ch #121 PPG9 Address: 0FFE18h #122 PPG10 Address: 0FFE14h #123 PPG11 Address: 0FFE10h #124 PPG12 Address: 0FFE0Ch #125 PPG13 Address: 0FFE08h #126 PPG14 Address: 0FFE04h #127 PPG15 Address: 0FFE00h The Interrupt Request flag (PCN.IRQF) does not clear itself automatically.
Page 836 Chapter 39 Programmable Pulse Generator 7.Q & A 7.13 What interrupts are available and how are they selected? Interrupt cause selection Four kinds of interrupts are selectable as follows: Use the Interrupt Cause Setting bit (PCN.IRS[1:0]) to set. Interrupt Cause Software trigger or Internal trigger generation (PPG0-PPG15) Down counter borrow (cycle match) Duty match...
Page 837: Caution
8. Caution • If the Interrupt Request flag (PCN.IRQF) equals “1” and the Interrupt Request flag is set to “0” at the same time, the setting of the Interrupt Request flag to “1” overrides the flag clear request. • The first load comes with a maximum delay of 2.5T after the activation trigger. (T: Count clock) If the down counter is loaded and counts at the same time, the load operation overrides.
Page 838 Chapter 39 Programmable Pulse Generator 8.Caution...
Page 839: Chapter 40 Pulse Frequency Modulator
Chapter 40 Pulse Frequency Modulator This chapter provides an overview of the 16-bit pulse frequency modulator, describes the regis- ter structure/functions, and describes the operation of the 16-bit pulse frequency modulator. 1. PFM Overview The 16-bit pulse frequency modulator consists of two 16-bit down-counters, two 16-bit reload registers, prescalers for generating the internal count clocks and control registers.
Page 840 Chapter 40 Pulse Frequency Modulator 1.PFM Overview ■ 16-bit Reload Counter 0 Register Configuration Register Control status register 16-bit counter register 16-bit reload register ■ 16-bit Reload Counter 1 Register Configuration Register Control status register 16-bit counter register 16-bit reload register Figure 1-1 16-bit Reload Counter Register Conﬁguration Name –...
Page 841 ■ Block Diagram of the 16-Bit Pulse Frequency Modulator Clock selector φ Internal clock Clock selector φ Internal clock Figure 1-2 Block Diagram of the 16-bit Pulse Frequency Modulator 16-bit reload register Reload 16-bit down-counter GATE CSL2 CSL1 CSL0 φ φ...
Page 842: Reload Counter Registers
Chapter 40 Pulse Frequency Modulator 2.Reload Counter Registers 2. Reload Counter Registers This section describes the 16-bit pulse frequency modulator registers listed below. Control status register (P0TMCSR, P1TMCSR) 16-bit counter register (P0TMR, P1TMR) 16-bit reload register (P0TMRLR, P1TMRLR) ■ Control Status Register (P0TMCSR, P1TMCSR) Controls the operation mode and interrupts for the 16-bit reload counter.
Page 843 Table 2-1 CSL Bit Clock Source Settings CSL2 CSL1 CSL0 [Bits 9] Reserved Always set to "0". [Bits 8] MOD1 Sets the Trigger level to Falling edge (MOD1=’1’ is necessary for PFM operation) [Bits 7 to 5] Reserved Always set to "010". [Bit 4] RELD This bit enables reload operations.
Page 844 Chapter 40 Pulse Frequency Modulator 2.Reload Counter Registers Writing "1" sets the counter to wait for a trigger. Writing "0" stops count operation. [Bit 0] TRG Software trigger bit. Writing "1" to TRG applies a software trigger, causing the counter to load the reload register contents to the counter and start counting.
Page 845 ● P0TMRLR, P1TMRLR structure Address 0000 0176 0000 017A Access × × Initial value Figure 2-3 Structure of the 16-bit Reload Register • • • × × × • • • Chapter 40 Pulse Frequency Modulator 2.Reload Counter Registers × ×...
Page 846: Reload Counter Operation
Chapter 40 Pulse Frequency Modulator 3.Reload Counter Operation 3. Reload Counter Operation This section describes the operations of the 16-bit reload counter: Internal clock operation and Underflow operation ■ Internal Clock Operation The machine clock divided by 2, 8, 32, 64 or 128 can be selected as the clock source when operating the counter from an internal clock.
Page 847 ● Underflow operation timing • When RELD = "1" Count clock Counter Data load Underﬂow set • When RELD = "0" Count clock Counter Underﬂow set ■ Counter Operation States The counter state is determined by the CNTE bit in the control register and the internal WAIT signal.
Page 848 Chapter 40 Pulse Frequency Modulator 3.Reload Counter Operation ● Counter state transitions Reset CNTE= "0" WAIT CNTE= "1", WAIT="1" Counter: Stores the value when counting stopped. Indeterminate after a reset until loaded. STOP CNTE= "0", WAIT= "1" Counter: Stores the value when counting stopped.
Page 849: Pfm Operation And Setting
4. PFM Operation and Setting This section describes the following operations of the 16-bit pulse frequency mod (combining the functionality of both reload counters). The underflow output of reload counter channel 0 is connected internally to the trigger input reload counter channel 1.
Page 850 Chapter 40 Pulse Frequency Modulator 4.PFM Operation and Setting...
Page 851: Chapter 41 Up/Down Counter
Chapter 41 Up/Down Counter 1. Overview Triggered by an input signal, 16-bit Up/Down Counter counts up or down within the range of 0 to 65535. Specifically, Up/Down Counter running in the phase difference count mode is suitable for counting the encoder pulse of motors and other equipment.
Page 852: Configuration
Chapter 41 Up/Down Counter 3.Conﬁguration 3. Configuration Up/Down Counter 0 (8 Bit Mode) 8 bit mode M16E UDCC0 : bit15 8 bit mode CMS1-0 UDCC0: bit11 -10 Timer mode (Countdown only) Up/down count mode Phase difference count mode (Multiply by 2) Phase difference count mode (Multiply by 4) Peripheral clock Prescaler...
Page 853 Up/Down Counter 1 (8 Bit Mode) 8 bit mode M16E UDCC0 : bit15 8 bit mode CMS1-0 UDCC1: bit11 -10 Timer mode (Countdown only) Up/down count mode Phase difference count mode (Multiply by 2) Phase difference count mode (Multiply by 4) Peripheral clock Prescaler CLKP...
Page 854 Chapter 41 Up/Down Counter 3.Conﬁguration Up/Down Counter (16 Bit Mode) 16 bit mode M16E UDCC0 : bit15 16 bit mode CMS1-0 UDCC0: bit11-10 Timer mode (Countdown only) Up/down count mode Phase difference count mode (Multiply by 2) Phase difference count mode (Multiply by 4) Peripheral clock Prescaler CLKP...
Page 855 Note: For ICR registers and interrupt vectors, refer to Note: For ICR registers and interrupt vectors, refer to Figure 3-5 Register List “Chapter 24 Interrupt Control (Page Figure 3-6 Register List “Chapter 24 Interrupt Control (Page Chapter 41 Up/Down Counter 3.Conﬁguration No.311)”.
Page 856: Register
Chapter 41 Up/Down Counter 4.Register 4. Register 4.1 UDCC: Counter Control Register This register is used to control behaviors of Up/Down Counter. • UDCC0 (Up/Down Counter 0): Address 0304 • UDCC1 (Up/Down Counter 1): Address 0308 • UDCC2 (Up/Down Counter 2): Address 0314 •...
Page 857 : Frequency of Peripheral clock (CLKP) CLKP This setting is enabled only in the timer mode, in which only countdown is performed. • bit11,10: Select count mode CMS1 CMS0 Timer mode (Countdown) Up/down count mode Phase difference count mode (Multiply by 2) Phase difference count mode (Multiply by 4) •...
Page 858 Chapter 41 Up/Down Counter 4.Register • bit1,0: Select counter clear/gate edge CGE1 CGE0 When the counter clear function is selected Disable edge detection. Detect a falling edge. Detect a rising edge. Disable setting. Edge detection/level selection When the gate function is selected (CGSC=“0”) Disable level detection.
Page 859 4.2 UDCS: Count Status Register This register is used to control Up/Down Counter and to indicate the status of the counter. • UDCS0 (Up/Down Counter 0): Address 0307 • UDCS1 (Up/Down Counter 1): Address 030B • UDCS2 (Up/Down Counter 2): Address 0317 •...
Page 860 Chapter 41 Up/Down Counter 4.Register To enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”). • bit1,0: Up/down flag UDF1 UDF0 No input Count down Count up Both of count up and count down Previous count operation...
Page 861 4.3 UDCR: Up/Down Counter Register This register is used to read the count value of Up/Down Counter. • UDCR10 (Up/Down Counter 0/1): Address 0302 • UDCR32 (Up/Down Counter 2/3): Address 0312 Depending on the setting of the 16-bit mode enable bit (CCR.M16E), this register behaves differently. ■...
Page 862 Chapter 41 Up/Down Counter 4.Register 4.4 UDRC: Up/Down Reload/Compare Register This register is used to reload a value to Up/Down Counter and for comparison. This register is also used to write to Up/Down Counter. • UDRC10 (Up/Down Counter 0/1): Address 0300 •...
Page 863 Chapter 41 Up/Down Counter 4.Register (1) Stop counting. (2) Write a value to the reload/compare register. (3) Write “1”to the counter write bit (CCR.CTUT).
Page 864: Operation
Chapter 41 Up/Down Counter 5.Operation 5. Operation This section describes each operation mode for Up/Down Counter. 5.1 Timer Mode CMS[1:0]=“00” divided by 2 CLKP divided by 8 CLKP Reload value CLKS, RLDE CGSC CSTR Underflow (Interrupt request) Interrupt request enabled An appropriate bit (Reload enable RLDE) is set.
Page 865 5.2 Up/Down Count Mode CMS[1:0]=“01” divided by 2 CLKP divided by 8 CLKP Reload value CLKS, RLDE CGSC CSTR Underflow (Interrupt request) Interrupt request enabled Up/Down Counter clear control using the ZIN pin Appropriate bits (Counting enable CSTR, Reload enable RLDE, Clear enable UCRE) are set. When pulse input to the AIN pin is detected, Up/Down Counter counts up.
Page 866 Chapter 41 Up/Down Counter 5.Operation 5.3 Up/Down Count Mode CMS[1:0]=“01” ZIN=Gate control CS TR, RLDE, UCRE UDCC CGE[1:0]=“10” ZIN (Gate) Countgate at the ZIN pin Appropriate bits (Counting enable CSTR, Reload enable RLDE and Clear enable UCRE) are set. Up/Down Counter is cleared. (“0” is written to CGSC). Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither counts up nor down.
Page 867 5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10” Frequency multiplied by 2 in phase difference count mode: On the rising and falling edges at the BIN count pin, Up/Down Counter counts up or down, depending on the voltage level at the AIN pin. Count value •...
Page 868 Chapter 41 Up/Down Counter 5.Operation 5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11” Frequency multiplied by 4 in phase difference count mode: On the rising and falling edges at the BIN pin, Up/Down Counter counts up or down, depending on the voltage level at the AIN pin, and on the rising and falling edges at the AIN pin, Up/Down Counter counts up or down, depending on the voltage level at the BIN pin.
Page 869 5.6 Clear Timing (1) When a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit UDCLR) is made, clear is performed next time when Up/Down Counter counts up. 0066 Compare value 0065 Count value Clear request Countup Clear timing (2) Even if a clear request (Compare-match, ZIN edge detection and writing “0”...
Page 870 Chapter 41 Up/Down Counter 5.Operation 5.7 Reload Timing The next time when Up/Down Counter counts down below “0000”, an underflow occurs (an interrupt request is made) and then reloading is performed. Compare value Count value Countdown Underflow Reload timing Note: If clear and reload operations occur at the same time, clear takes precedence. 5.8 Writing a Value to Counter Up/Down Counter CSTR...
Page 871: Setting
6. Setting Table 6-1 Required Settings to Run Up/Down Counter in Timer Mode Setting Set the reload value. (Optional) Set a value to Up/Down Counter Clear the count value of Up/Down Counter. Set a bit length. Set the count mode to timer mode. Select a count source.
Page 872 Chapter 41 Up/Down Counter 6.Setting Table 6-3 Required Settings to Run Up/Down Counter in Phase Difference Count Mode (Multiply by 2 or 4) Setting Set the reload value/compare value. (Optional) Set a value to Up/Down Counter Clear the count value of Up/Down Counter. Set a bit length.
Page 873 7. Q&A 7.1 How do I select a bit length (8 or 16) of Up/Down Counter? Use the 16 bit mode enable bit (UDCC.M16E). Up/Down Counter's bit length To set the bit length to 8 To set the bit length to 16 bit 7.2 What types of count modes are available and how are they set? There are four types of count modes: Timer, Up/down count, Phase difference count (Multiply by 2 or 4)
Page 874 Chapter 41 Up/Down Counter 7.Q&A 7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when Up/Down Counter is underﬂowed? Use the reload enable bit (UDCC.RLDE). When the count-up value agrees with the compare value: To disable reloading of the reload value (RCR) to Up/ Down Counter To enable reloading of the reload value (RCR) to Up/Down Counter...
Page 875 7.11 How do I enable/disable Up/Down Counter's count operation? Use the count activate bit (UDCS.CSTR). When the count-up value agrees with the compare value: To disable Up/Down Counter's count operation To enable Up/Down Counter's count operation (To activate count operation) •...
Page 876 Chapter 41 Up/Down Counter 7.Q&A 7.15 How do I know that an overﬂow or underﬂow has occurred? Use the overflow detection flag (UDCS.OVFF) and the underflow detection flag (UDCS.UDFF). OVFF =“1” indicates that Up/Down Counter has been overﬂowed. UDFF =“1” indicates that Up/Down Counter has been underﬂowed. 7.16 How do I set the reload/compare value? Set a value to the reload/compare registers (UDRC).
Page 877 7.19 How do I enable (select), disable or clear interrupts? Interrupt request enable and interrupt request flags To enable (select) interrupts, use the following interrupt request permission bits: • Count direction change interrupt request permission bits: UDCC.CFIE • Compare interrupt request permission bits •...
Page 878: Caution
Chapter 41 Up/Down Counter 8.Caution 8. Caution • The count direction is set to “countdown” immediately after resetting the counter. So, when the counter counts up immediately after resetting, the count direction change bit (UDCC.CDCF) is set to “1” to indicate a direction change has been made.
Page 879: Chapter 42 Sound Generator
Chapter 42 Sound Generator 1.Overview Chapter 42 Sound Generator 1. Overview This Chapter provides an overview of the Sound Generator, describes the register structure and functions, and describe the operation of the Sound Generator. The Sound Generator consists of the Sound Control register, Frequency Data register, Ampli- tude Data register, Decrement Grade register, Tone Count register, Sound Disable register, PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter.
Page 880: Block Diagram
Chapter 42 Sound Generator 2.Block Diagram 2. Block Diagram CLKP 8bit PWM pulse Prescaler S1 S0 Amplitude Data Grade register Tone Count Generator reload register Decrement Counter Decrement Tone Pulse Counter INTE INT register Frequency Toggle Counter flip-flop reload Frequency register TONE...
Page 881: Registers
3. Registers Sound Control register Address: 000198 Read/write Initial value Address: 000199 Read/write Initial value Frequency Data register Address: 00019A Read/write Initial value Amplitude Data register Address: 00019C Read/write Initial value Tone Count register Address: 00019E Read/write Initial value Decrement Grade register Address: 00019F Read/write...
Page 882 Chapter 42 Sound Generator 3.Registers 3.1 Register Details ■ Sound Control Register (SGCR) Sound Control register Address: 000198 Read/write Initial value Address: 000199 Read/write Initial value [bit 15] TST : Test bit This bit is prepared for the device test. In any user application it should be set to "0". [bits14 to12] S2 to S0 : Operation clock select bits These bits specify the clock input signal for the Sound Generator.
Page 883 [bit 2] INTE : Interrupt enable bit This bit enables the interrupt signal of the Sound Generator. When this bit is "1" and the INT bit is set to "1", the Sound Generator signals an interrupt. [bit 1] INT : Interrupt bit This bit is set to "1"...
Page 884 Chapter 42 Sound Generator 3.Registers value represents the amplitude of the sound. The register value is reloaded into the PWM pulse generator at the end of every tone cycle. When the DEC bit is "1" and the Decrement counter reaches its reload value, this register value is decremented by 1(one).
Page 885 reaches the reload value it sets the INT bit. They are intended to reduce the frequency of interrupts. The count input of the Tone Pulse counter is connected to the carry-out signal from the Decrement counter. And when the Tone count register is set to "00", the Tone Pulse counter sets the INT bit every carry-out from the Decrement counter.
Page 886 Chapter 42 Sound Generator 3.Registers...
Page 887: Chapter 43 Stepper Motor Controller
Chapter 43 Stepper Motor Controller 1. Overview The stepping motor controller consists of PWM pulse generators, motor drivers, selector logic circuits and A/D converter inputs. The four motor drivers have a high-output driving capability and two motor coils can be connect- ed directly to four pins.
Page 888: Registers
Chapter 43 Stepper Motor Controller 2.Registers Clock Prescaler PWM1 pulse generator Peripheral clock PWM1 compare register CLKP PWM2 pulse generator PWM2 compare register Remark: The SMC channels 4 and 5 are not shared with ADC inputs. 2. Registers There are seven types of registers for the stepping motor controller: PWM Control register PWM1 Compare register PWM2 Compare register...
Page 889 2.1 Registers for Stepping Motor Controller PWM Control register (PWC0, PWC1, PWC2, PWC3, PWC4, PWC5) Address 0x0C1, 0x0C3 0x0C5, 0x0C7 0x0C9, 0x0CB PWM1 Compare register (PWC10, PWC11, PWC12, PWC13, PWC14, PWC15) Address 0x092, 0x09A 0x0A2, 0x0AA 0x0B2, 0x0BA Address 0x093, 0x09B 0x0A3, 0x0AB 0x0B3, 0x0BB PWM2 Compare register (PWC20, PWC21, PWC22, PWC23...
Page 890 Chapter 43 Stepper Motor Controller 2.Registers 2.2 PWM Control Register The PWM control register starts/stops the stepping motor controller, performs interrupt control and performs setting of external output pins, etc., for the stepping motor controller. ■ PWM Control Register PWM Control register (PWC0, PWC1, PWC2, PWC3, PWC4, PWC5) Address 0x0C1, 0x0C3 0x0C5, 0x0C7...
Page 891 Chapter 43 Stepper Motor Controller 2.Registers PWM pulse generator operates at 8 bit. [bit 1 to 0] Reserved bits Always set the reserved bits to "00".
Page 892 Chapter 43 Stepper Motor Controller 2.Registers 2.3 PWM1&2 Compare Registers The value of the two 8(10) bits compare register of PWM1&2 determine the width of the PWM pulse. The stored "00 (000 ("3FF ") value indicates that the PWM duty is 99.6% (99.9%). ■...
Page 893 Chapter 43 Stepper Motor Controller 2.Registers Figure 2-1 Relationship between the Compare Register Setting Value and PWM Pulse Width Register value One PWM cycle 256 (1024) input cycles (200 128 (512) input cycle (3FF 255 (1023) input cycle...
Page 894 Chapter 43 Stepper Motor Controller 2.Registers 2.4 PWM1&2 Selection Registers The PWM1&2 selection registers determine whether to set the output of the external pin of the stepping motor controller to "0", "1", PWM pulse or high impedance. ■ PWM1&2 Selection Registers PWM2 Selection register (PWS20, PWS21, PWS22, PWS23, PWS24, PWS25) Address 0x096, 0x09E...
Page 895 Figure 2-2 load timing of PWM compare register value [Automatic clear of BS bit] PWM pulse PWM pulse generator 3FFh 000h counter value PWM compare 3FFh register value Load PWM pulse generator XXXh compare register value When set a BS bit in "1" with automatic clear simultaneously PWM pulse PWM pulse generator 3FFh...
Page 896 Chapter 43 Stepper Motor Controller 2.Registers [bit 13 to 11] P2 to P0: Output select bits These bits are used to select the output signal for SMC2P. [bit 10 to 8] M2 to M0: Output select bits These bits are used to select the output signal for SMC2M. [bit 7 to 6] Reserved bit Always set the reserved bit to "0".
Page 897: Operation
3. Operation The operation of the stepping motor controller is explained. ■ Setting Operation of Stepping Motor Controller Figure 3-1 Setting of Stepping Motor Controller ■ Operation of PWM-pulse generator When the counter is started (PWC: CE = 1), the counter starts incrementing from 00H on the selected count clock rising.
Page 898 Chapter 43 Stepper Motor Controller 3.Operation Figure 3-2 Examples of PWM1&2 Waveform Output When the value of compare register is "00 Value of counter: PWM waveform: When the value of compare register is "80 Value of counter: PWM waveform: When the value of compare register is "FF Value of counter: PWM waveform: ■...
Page 899: Caution
Chapter 43 Stepper Motor Controller 4.Caution 4. Caution The caution when using the stepping motor controller are described below. ■ Caution when Changing PWM Setting The PWM compare registers 1&2 (PWC1, PWC2) and the PWM selection registers 1&2 (PWS1, PWS2) can be accessed at any time.
Page 900 Chapter 43 Stepper Motor Controller 4.Caution...
Page 901: Chapter 44 A/D Converter
Chapter 44 A/D Converter This chapter provides an overview of the A/D converter, describes the register structure and functions, and describes the operation of the A/D converter. • 1. Overview of A/D Converter • 2. Block Diagram of A/D Converter •...
Page 902: Block Diagram Of A/D Converter
Chapter 44 A/D Converter 2.Block Diagram of A/D Converter 2. Block Diagram of A/D Converter Following figure shows block diagram of A/D converter. Block diagram of A/D converter MP X AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22...
Page 903: Registers Of A/D Converter
3. Registers of A/D Converter The A/D converter has the following registers. • • A/D enable register (ADER) • • A/D control status register (ADCS) • • Data register (ADCR) • • Sampling timer setting register (ADCT) • • Start channel setting register (ADSC) •...
Page 904 Chapter 44 A/D Converter 3.Registers of A/D Converter • ADCS0 (ADC0): Address 01A5h (Access: (See “Meaning of Bit Attribute Symbols (Page • ADCR1 (ADC0): Address 01A6h (Access: (See “Meaning of Bit Attribute Symbols (Page • ADCR0 (ADC0): Address 01A7h (Access: (See “Meaning of Bit Attribute Symbols (Page •...
Page 905 • ADECH (ADC0): Address 01ABh (Access: RX, W0 RX, W0 RX, W0 (See “Meaning of Bit Attribute Symbols (Page 3.1 A/D Enable Register (ADER) While a pin is used as analog input, corresponding bit in ADER register have to be set to 1. ■...
Page 906 Chapter 44 A/D Converter 3.Registers of A/D Converter 3.2 A/D Control Status Register (ADCS) A/D control status register controls and shows the status of A/D converter. Do not overwrite ADCS0 register during A/D converting. ■ A/D control status register 1 (ADCS1) •...
Page 907 Cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting condition of DMA transfer, this bit cannot be cleared. Regarding protect function of converted data, see Section [bit 3, 2] STS1, STS0 (Start source select) These bits initialized "00"...
Page 908 Chapter 44 A/D Converter 3.Registers of A/D Converter Continuous mode: Repeated A/D conversion cycles from selected channels ANS4 to ANS0 to selected channels ANE4 to ANE0. Stop mode: A/D conversion for each channel from selected ANS4 to ANS0 to selected channels ANE4 to ANE0, followed by a pause.
Page 909 2-bit. The register values are updated at the completion of each conversion. The registers normally store the results of the previous conversion. ■ Data register (ADCR1, ADCR0) • ADCR1 (ADC0): Address 01A6h (Access: RX, W0 RX, W0 RX, W0 (See “Meaning of Bit Attribute Symbols (Page •...
Page 910 Chapter 44 A/D Converter 3.Registers of A/D Converter Conversion time = CT value * CLKP cycle * 10 + (4 * CLKP) Remarks : Do not set conversion time over 500 us. [bit 9 to 0] ST9-0 (Analog input sampling time set) These bits specify sampling time of analog input.
Page 911 • ADECH (ADC0): Address 01ABh (Access: RX, W0 RX, W0 RX, W0 (See “Meaning of Bit Attribute Symbols (Page These bits set the start and end channel for A/D converter. Setting of ANE4 to ANE0 the same channel as in ANS4 to ANS0 speciﬁes conversion for that channel only.
Page 912: Operation Of A/D Converter
Chapter 44 A/D Converter 4.Operation of A/D Converter 4. Operation of A/D Converter The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. As only one 16-bit register is provided to store conversion results, the conversion data register (ADCR0 and ADCR1) is updated each time conversion completes.
Page 913 4.1 Single-shot conversion mode AN input Channel selection Activation (trigger) Internal level Conversion value Buffer (ADT) Conversion end (INT) BUSY Channel selection A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger) INT flag clear, BUSY flag set Sample hold Conversion (Conversion a + Conversion b + Conversion c) Conversion end, INT flag set, BUSY flag clear Buffers the conversion value.
Page 914 Chapter 44 A/D Converter 4.Operation of A/D Converter 4.2 Scan conversion mode AN input Scan start channel selection Sample hold Activation (trigger) a, b, c Buffers ADT0 ADT1 ADT2 ADT3 Conversion end (INT) BUSY Activation channel selection A/D activation (Trigger: Software trigger/Reload timer/External trigger) INT flag clear, BUSY flag set AN0 conversion a.
Page 915: Setting
5. Setting Table 5-1 Settings needed to use A/D - Single-Shot Conversion Mode Setting Mode selection (Single-shot conversion) Bit length selection Channel selection Conversion time setting To program the AN pin as an input A/D activation trigger selection A/D activation trigger generation Software trigger ->...
Page 916 Chapter 44 A/D Converter 5.Setting Table 5-3 Forcing A/D operations to Stop Setting Forced stop A/D control (ADCS) *: For the setting procedure, refer to the section indicated by the number. Table 5-4 Items needed to enable A/D Interrupts Setting A/D interrupt vector and A/D interrupt level settings A/D interrupt cause selection (A/D conversion end)
Page 917 6. Q & A 6.1 What conversion modes are available and how are they selected? Two modes of conversion are available: • Single-shot conversion mode, in which the conversion takes place only once. • Scan conversion mode, in which a specified sequence of channels are converted. Mode selection is made using the conversion mode selection bits (ADCS.MD[1:0]).
Page 918 Chapter 44 A/D Converter 6.Q & A 6.3 How do I set a conversion time? Use Conversion Time Setting registers ADCT to set. [bit 15 to 10] CT5-0 (A/D conversion time set) These bits specify clock division of conversion time. Setting "000001"...
Page 919 To program the AN18 pin as an input To program the AN19 pin as an input To program the AN20 pin as an input To program the AN21 pin as an input To program the AN22 pin as an input To program the AN23 pin as an input To program the AN24 pin as an input To program the AN25 pin as an input...
Page 920 Chapter 44 A/D Converter 6.Q & A To specify a software trigger To specify an external trigger/software trigger To specify a reload timer/software trigger To specify an external trigger/reload timer/software trigger The converter A/D is activated on the first instance of any one of these causes selected. 6.7 To activate the A/D converter •...
Page 921 6.11 What interrupt registers are used? A/D interrupt vector, A/D interrupt level setting The table below summarizes the relationships among the machine cycle, A/D number, interrupt level, and interrupt vector. For more information about the interrupt level and interrupt vector, see No.311).”...
Page 922: Caution
Chapter 44 A/D Converter 7.Caution 7. Caution Tips on using the A/D converter are summarized as follows: • Power-on sequence Be sure to turn on the MCU power (Vdd*) before turning on the power to the A/D converter (AVcc, AVRH) and applying a voltage to the analog input.
Page 923 ■ Definitions of A/D Converter Terms • Resolution Analog change identifiable to an A/D converter. • Linearity error Deviation between the straight line connecting zero transition point (00 0000 0000 <- -> 00 0000 0001) and full-scale transition point (11 1111 1110 <- -> 11 1111 1111) from actual conversion characteristics •...
Page 924 Chapter 44 A/D Converter 7.Caution • Overall error Difference between an actual vale and a theoretical value, containing a zero transition error/full transition error/linearity error AVRH - AV 1LSB’(Ideal value) = ’ (Ideal value) ’ (Ideal value) = AVRH - 1.5LSB’ Overall error of digital output N = : Voltage at which digital output transit from (N+1) to N 1024...
Page 925: Chapter 45 D/A Converter
Chapter 45 D/A Converter 1. Overview The D/A converter converts digital values to analog output values on an R-2R type conversion basis. Digital value 2. Features Method : R-2R type conversion Quantity : 2 (Output: DA0 pin and DA1 pin) Conversion time : 0.45us (Typ) (Load capacitance = 20pF) 2.0us (Typ) (Load capacitance = 100pF)
Page 926: Configuration
Chapter 45 D/A Converter 3.Conﬁguration 3. Configuration D/A converter (0-1) DADR0/ DADR1 AVcc AVss For a detailed description of the D/A pin circuit, see the chapter entitled “Basic Information”. Figure 3-1 Conﬁguration Diagram Register number (:bit) DACR: bit 0 DACR: bit 1 D/A output disable (0 V output) D/A output enable From Port...
Page 927: Registers
4. Registers 4.1 DADR: D/A Data Register The D/A Data Register sets the output voltage of the D/A converter. • DADR0(ch0): Address 0364 • DADR1(ch1): Address 0366 RX/W0 RX/W0 RX/W0 (For the attributes, refer to the • The D/A Data Register is not initialized on a reset. •...
Page 928 Chapter 45 D/A Converter 4.Registers • bit2: D/A 8-/10-bit mode control MD08 • In case MD08=’1’ the 8-bit value of DA7-DA0 (DADR[7:0]) is output. Operation D/A resolution is 10 bits D/A resolution is 8 bits...
Page 929: Operation
5. Operation The operations of the D/A converter are described below. DADR0/- 0A0h DADR1 DA0/DA1 output level (1) Digital value setting (software-programmable) (2) D/A conversion in progress (3) Output enabled (software-programmable) (4) Analog value output (5) Digital value rewrite (software-programmable) (6) D/A conversion in progress (7) Output level finalized (8) Output disabled (software-programmable)
Page 930: Setting
Chapter 45 D/A Converter 6.Setting 6. Setting Table 6-1 Settings Needed to Use D/A Setting Digital value settings Pin settings Output enabled *:For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings Needed to Stop D/A Output Setting Output halted *:For the setting procedure, refer to the section indicated by the number.
Page 931 7. Q & A 7.1 Where should I set digital values? Write digital values to the D/A Data Registers (DADR[7:0] for 8-bit mode, DADR[9:0] for 10-bit mode). Access in a byte or halfword format. D/A conversion begins immediately on writing. 7.2 How do I program the D/A pins for D/A output? DA Pin output setting Setting is accomplished by writing “1”...
Page 932: Caution
Chapter 45 D/A Converter 8.Caution 8. Caution • The table below lists the output voltages of the D/A converter (in 10-bit resolution mode). DADR Settings D/A Converter Output Voltage Value When stopped • The table below lists the output voltages of the D/A converte (in 8-bit resolution mode)r. DADR Settings D/A Converter Output Voltage Value When stopped...
Page 933: Chapter 46 Alarm Comparator
Chapter 46 Alarm Comparator 1. Overview This chapter provides an overview of the Alarm Comparator (also called Under/Overvoltage De- tection), describes the register structure and functions, and describes the operation of the Alarm Comparator. 2. Block Diagram Alarm comparator - analog part AVDD 0.8 AVDD ALARM...
Page 934: Alarm Comparator Control/Status Register (Acsr)
Chapter 46 Alarm Comparator 3.Alarm Comparator Control/Status Register (ACSR) 3. Alarm Comparator Control/Status Register (ACSR) • ACSR0 (ch0): Address 01AD • ACSR1 (ch1): Address 01AF Address ACSR0 0000 01AD ACSR1 0000 01AF Figure 3-1 Structure of Alarm comparator control/status register Bit 7: MD Mode select Bit 6: OV_EN Overvoltage Enable Bit 5: UV_EN Undervoltage Enable...
Page 935: Operation Modes
Bit 1: IEN Interrupt enable bit. Bit 0: PD Power down bit. 4. Operation Modes The alarm comparator circuit can operate in interrupt or polling mode. The internal interrupt logic will detect each interrupt event independent from setting of the IEN bit. 4.1 Interrupt Mode (IEN=1) The following truth table describes the valid interrupt events Table 4-1 Valid interrupt events...
Page 936 Chapter 46 Alarm Comparator 4.Operation Modes 4.4 Power Down Modes of the Alarm Comparator The alarm comparator circuit has the following power down modes: Table 4-2 Alarm Comparator power down modes STOP Precaution: The outputs of the alarm comparator (analog parts) will remain undefined for at least 3 us after power on and also after reentering the runmode.
Page 937: Chapter 47 Lcd Controller
Chapter 47 LCD Controller 1. Overview LCD allows display of up to 160 cells and selection of a duty cycle from 1/2, 1/3 and 1/4. LCD has many applications. Internal Divided Resistors External Divided Resistors Peripheral clock Sub-clock 2. Features •...
Page 938: Configuration
Chapter 47 LCD Controller 3.Conﬁguration 3. Configuration LCD Controller FP1,0 FP1,0 LCR0: bit1,0 Main clock CLKP CLKP CLKP CLKP Peripheral clock clock Internal Divided Resistors VSEL LCR0: bit5 Disconnect internal divided resistors. Connect internal divided resistors. LCEN LCR0: bit6 Disable display in watch mode. Enable display in watch mode.
Page 939 Chapter 47 LCD Controller 3.Conﬁguration Figure 3-2 Register List...
Page 940: Registers
Chapter 47 LCD Controller 4.Registers 4. Registers 4.1 LCR0: LCDC Control Register 0 This register is used to select a frame period and its clock and the display mode, to enable/disable LCD display and the operation in the watch mode, and to control the drive power source. •...
Page 941 • bit1-0: Frame period When peripheral clock is selected: CLKP CLKP CLKP CLKP Peripheral clock (CLKP) frequency CLKP Subclock frequency CL-SUB Time division number (Selected with the display mode select bits, MS1 and MS0.) Select an appropriate value in accordance with the frame frequency of your LCD panel. Frame period ×...
Page 942 Chapter 47 LCD Controller 4.Registers 4.2 VRAM: Data Memory for Display Memory area (VRAM) for setting display data • VRAM0 (SEG0, SEG1): Address 0EC • VRAM1 (SEG2, SEG3): Address 0ED • VRAM2 (SEG4, SEG5): Address 0EE • VRAM3 (SEG6, SEG7): Address 0EF •...
Page 943 Chapter 47 LCD Controller 4.Registers • Correspondence between VRAM and Common/Segment Pins...
Page 944 Chapter 47 LCD Controller 4.Registers 4.3 LCR1: LCDC Control Register 1 • LCR1H: Address 0EA (Access: Byte, Half-word, Word) (For attributes, refer to “Meaning of Bit Attribute Symbols (Page • bit15-10: Undefined (Read: Indeterminate, Write: “0” is always written.) • bit9-8: Segment driver enable. Always set to “11 ”...
Page 945: Operation
5. Operation This section describes operation. 5.1 LCD Controller/Driver (LCDC) Operation (1) Set values to the display data memory (VRAM) in advance. (2) Make necessary settings to each register. (3) When the frame period generation clock oscillates, LCD drive waveform is output through common/ segment output pins (COM0 - COM3, SEG0 - SEG39).
Page 946 Chapter 47 LCD Controller 5.Operation LCD cell corresponding to SEG 2n+1, COM0 output COM0 output COM1 output COM2 output COM3 output SEG 2n output SEG 2n+1 output LCD cell corresponding to SEG 2n, COM0 output LCD cell corresponding to SEG 2n, COM1 output LCD cell corresponding to SEG 2n+1, COM1 output...
Page 947 5.3 1/3 Duty Cycle Output Waveform In the 1/3 duty cycle output mode, COM0, COM1 and COM2 outputs are used for LCD display. COM3 output is not used. • Example of 1/3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment outputs are lit. Table 5-2 Example of Data Memory Contents for Display Segment SEG 2n output...
Page 948 Chapter 47 LCD Controller 5.Operation COM0 output COM1 output COM2 output COM3 output SEG 2n output SEG 2n+1 output LCD cell corresponding to SEG 2n, COM0 output LCD cell corresponding to SEG 2n, COM1 output LCD cell corresponding to SEG 2n, COM2 output LCD cell corresponding to SEG 2n+1, COM0 output LCD cell corresponding to SEG 2n+1, COM1 output LCD cell corresponding to SEG 2n+1, COM2 output...
Page 949 5.4 1/4 Duty Cycle Output Waveform In the 1/4 duty cycle output mode, COM0, COM1, COM2, and COM3 outputs are all used for LCD display. • Example of 1/3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment output are lit. Table 5-3 Example of Data Memory Contents for Display Segment SEG 2n...
Page 950: Setting
Chapter 47 LCD Controller 6.Setting 6. Setting Table 6-1 Required Setting to Use LCD Setting Presetting Set divided resistors. Set ports Set display data. Select the frame period generation clock. Set a frame period. Select a duty cycle. (Activation) Enable LCD display. * :For the setting procedure, refer to the section indicated by the number.
Page 951 7. Q&A 7.1 How do I specify pins as COM or SEG output pins? Use COM and SEG output settings. Software can switch ports to COM or SEG output ports. To do so, write “1” to the output designation bit (COM[3:0], SEG[39:0]). COM0 COM1 Port function register PFR30[3:0]...
Page 952 Chapter 47 LCD Controller 7.Q&A SEG32 SEG33 SEG34 SEG35 Port function register PFR31[7:0] SEG36 SEG37 SEG38 SEG39 (SEG32) (SEG33) (SEG34) (SEG35) (SEG36) (SEG37) (SEG38) (SEG39)
Page 953 7.2 How do I set VRM? The following tables show the relationship between pins and the bit positions of VRAM(n). (n=0 to 19) Table 7-1 1/2 duty cycle COM1 COM0 SEG 2n bit 1 bit 0 SEG 2n+1 Bit 5 Bit 4 Table 7-2 1/3 duty cycle COM2...
Page 954 Chapter 47 LCD Controller 7.Q&A 7.4 How do I set a duty cycle? Use the display mode select bit (LCR0.MS[1:0]). Controlled operation To deactivate LCD (Pin output: “L”) To set the 1/2 duty cycle output mode To set the 1/3 duty cycle output mode To set the 1/4 duty cycle output mode The display mode select bit also serves as an operation start/stop control bit.
Page 955 7.9 How do I select internal or external divided resistors? • When using internal divided resistors: LCDC operation enabled • When using external divided resistors: The LCD driving voltage can be generated by connecting external divided resistors to the LCD drive power supply pins (V0 to V3).
Page 956: Caution
Chapter 47 LCD Controller 8.Caution 8. Caution • To access VRAM, be sure to use byte-by-byte access. • Switching the frame period generation clocks: Frame period generation clocks (LCR0:CSS) can be switched even during LCD display. However, switching may cause some screen flicker. To avoid such flicker, be sure to set the blanking select bit (LCR0:BK) to “1” (blank display) before switching.
Page 957: Chapter 48 Clock Monitor
Chapter 48 Clock Monitor 1. Overview The Clock Monitor is a macro that outputs internal clock signals to a terminal to externally monitor them. The Clock Monitor provides a function to divide the frequency of a clock signal before it outputs to the terminal, thus allowing the clock signal to be used as an event at which external circuits act in synchronization with a MCU function.
Page 958: Configuration
Chapter 48 Clock Monitor 3.Conﬁguration 3. Configuration Clock Monitor Internal clocks Selector CMCFG CMSEL3:0 0000 Disable clock monitor output 0001 Main oscillation before CSV 0010 Sub oscillation before CSV 0011 RC oscillation 0100 Sub clock (after SCKS) 0101 Main oscillation after CSV 0110 Sub oscillation after CSV 0111...
Page 959: Register
4. Register 4.1 Clock Monitor Conﬁguration Register A register for output settings of an internal clock signal • CMCFG: Address 04AF (Access: Byte) CMPRE3 CMPRE2 CMPRE1 (For attributes, refer to “Meaning of Bit Attribute Symbols (Page • bit7-4: Select an output frequency prescaler CMPRE3 CMPRE2 CMPRE1...
Page 960 Chapter 48 Clock Monitor 4.Register • CSCFG: Address 04AEh (Access: Byte) EDSUEN PLLLOCK RCSEL (See “Meaning of Bit Attribute Symbols (Page • bit4: Clock Monitor MONCLK inverter MONCKI MONCLK mark level is low [Initial value] MONCLK mark level is high •...
Page 961: Operation
Chapter 48 Clock Monitor 5.Operation 5. Operation The following diagram shows the output waveforms of the Clock Monitor. (1) The MONCLK pin is in high impedance state. (2) CMSEL is set from “0000” (no clock selected) to the selected (and prescaled) clock. (3) The MONCLK pin changes to output “L”...
Page 962: Settings
Chapter 48 Clock Monitor 6.Settings 6. Settings Table 6-1 Settings for Using Clock Monitor Settings Set a prescaler value Set a source clock Change the mark level Enable clock monitor output.(MONCLK) *:For each setting procedure, refer to an appropriate section. 7.
Page 963: Caution
Chapter 48 Clock Monitor 8.Caution 8. Caution Due to the glitch free switching mechanism it is necessary to follow these rules when switching the clock source (CMCFG3:0) or the prescaler ratio (CMPRE3:0): - The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are currently 0x0. - The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are written to 0x0 within the same write access.
Page 964 Chapter 48 Clock Monitor 8.Caution...
Page 965: Chapter 49 Real-Time Clock
Chapter 49 Real-Time Clock 1. Overview Real-time Clock (RTC) continues to count elapsed time even in the STOP mode to provide the current real time (HH/MM/SS) based on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (~100kHz). This allows precise time counting without a return from an interrupt during stand by periods. Oscillation clock 2.
Page 966: Configuration
Chapter 49 Real-Time Clock 3.Conﬁguration 3. Configuration Real-Time Clock RUN WT CR: bit 3 RUN WT CR: bit 3 RUN WT CR: bit 3 Read Read only Read RT C RT C RTC inactive RTC active RT C RT C Prescaler: 1/2 Oscillation WT CR: bit 0...
Page 967: Registers
4. Registers 4.1 WTCR: RTC Control Register This register is used to control behavior of the Real-time Clock module. • WTCR: Address 04A2 (Access: Byte, Half-word) INTE3 INT3 INTE2 R(R1),W Reserved Reserved Reserved R/W0 R/W0 R/W0 (For attributes, refer to “Meaning of Bit Attribute Symbols (Page •...
Page 968 Chapter 49 Real-Time Clock 4.Registers When the minute counter overflows, this flag is set to “1”. • bit10: 1-minute interrupt request flag INT1 No interrupt requests Generate interrupt requests at 1-minute intervals. • bit9: Enable interrupt requests at 1-second intervals INTE0 No interrupt requests Generate interrupt requests at 1-second intervals.
Page 969 recommended that the Sub-Second register is updated while the ST bit is "0". However, if this update is done immediately after an RTC second interrupt there should be enough time to securely modify the registers until the next reload operation (next second interrupt) even if ST is not set to "0"...
Page 970 Chapter 49 Real-Time Clock 4.Registers 4.2 WTBR: Sub-Second Registers These registers are used to hold values to be reloaded to the 21 bit down counter. • WTBR0: Address 04A5 (Access: Byte, Half-word, Word) • WTBR1: Address 04A6 (Access: Byte, Half-word, Word) •...
Page 971 4.3 WTHR/WTMR/WTSR: Hour/Minute/Second Registers These registers hold time information (HH/MM/SS) for Real-time Clock. • WTHR (Hour register): Address 04A8 • WTMR (Minute register): Address 04A9 • WTSR (Second register): Address 04AA WTHR – – – – – – – – –...
Page 972: Operation
Chapter 49 Real-Time Clock 5.Operation 5. Operation This section describes Real-time Clock operation. 21 bit down counter Clear Half Second Second Clear Hour/ Minute/ Second counters Minute Clear Hour Clear WTSR WTMR WTHR WTBR(0 -2) STOP The start bit (ST) is set to “1” and then “0”. (Register initialization operation) This (ST=“0”) resets to 0 and stops the 21 bit down counter and the hour/minute/second timers.
Page 973 (10) When the second counter counts up to “59”, the counter is cleared next time when the counter counts up, at which the minute counter counts up, generating a 1-minute interrupt request. (11) When the minute counter counts up to “59”, the counter is cleared next time when the counter counts up, at which the hour counter counts up, generating a 1-hour interrupt request.
Page 974: Setting
Chapter 49 Real-Time Clock 6.Setting 6. Setting Table 6-1 Required Settings to Run Real-time Clock Setting Set a reload value to the sub-second registers. Initialize Real-time Clock. Set time (hour/minute/second). Activate Real-time Clock. *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Required Settings to Know Time Setting Read time.
Page 975 7. Q&A 7.1 How do I set the count period of 1 second? Stop Real-time Clock and then set the sub-second register WTBR. The reload value corresponds to the time needed for half a second, i.e. • At 32 kHz RTC operation set WTBR to “001FFF •...
Page 976 Chapter 49 Real-Time Clock 7.Q&A 7.8 What are interrupt-related registers? RTC interrupt vector and level settings. The following table shows the relationship between interrupt levels and vectors. For details on interrupt levels and vectors, refer to Interrupt vectors (Default) #132 (0FFDECh) The interrupt request flags (INT0,INT1,INT2,INT3 and INT4) are not automatically cleared, so the software must clear them by writing 0”...
Page 977: Caution
8. Caution • Setting the interrupt request flags (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT4 and WTCER.INT4) to “1” due to overflow, and writing “0” to that bit have occurred at the same time, the flag is set to “1”. (Flag setting takes precedence.) •...
Page 978 Chapter 49 Real-Time Clock 8.Caution lower than that of the peripheral clock (CLKP). If not, correct values cannot be read from WTHR/WTMR/ WTSR. • Note that only byte-access is allowed to these register. So, when these registers are read at the very timing of changing over the hour or minute boundary as shown below, there is a possibility of misjudging the time.
Page 979: Chapter 50 Subclock Calibration Unit
Chapter 50 Subclock Calibration Unit 1. Overview The Clock Calibration Module provides possibilities to calibrate the 32kHz oscillation clock or 100kHz RC oscillation clock with respect to the 4MHz oscillation clock. This chapter gives an overview of the calibration unit, describes the registers and provides some application notes. 1.1 Description This hardware allows the software to measure time generated by the 32kHz clock (or 100kHz RC clock) with the 4MHz clock.
Page 980: Block Diagram
Chapter 50 Subclock Calibration Unit 2.Block Diagram 2. Block Diagram UC18CLK OSC4 gate STRT READY RUNS OSC32 gate STRT CLKP gate RSLEEPB gate RSLEEPB STRT CLKPG2 = CLKP | (~STRT & RSLEEPB); async STRT RSLEEP UC18BUS *_RD *_WR UC18IO Figure 2-1 Block Diagram of the calibration unit CLK4G = OSC4 | ~STRT | (READY &...
Page 981: Timing
3. Timing 32 kHz STRT (CLKP) STRTS (32 kHz) (32 kHz) RUNS (4 MHz) 32 kHz counter (16 bit) 4 MHz counter (24 bit) old CUTR READY (32 kHz) READYPULSE (CLKP) INT (CLKP) Figure 3-1 Timing of the measurement process CUTD CUTD-1 Chapter 50 Subclock Calibration Unit...
Page 982: Clocks
Chapter 50 Subclock Calibration Unit 4.Clocks 4. Clocks The module operates with 3 different clocks: The 4 MHz clock OSC4, the 32 kHz clock OSC32 (ot the 100kHz clock OSC100) and the peripheral clock CLKP. Synchronization circuits adapt the different domains. The clock frequencies have to fulfill the following requirements: ●...
Page 983: Register Description
5. Register Description This section lists the registers of the calibration unit and describes the function of each register in detail. ■ Calibration Unit Control Register (CUCR) Control Register low byte Address : Read/write ⇒ Default value⇒ ■ 32kHz/100kHz Timer Data Register (CUTD) 32/100kHz Timer Register high byte Address : 0004B2H...
Page 984 Chapter 50 Subclock Calibration Unit 5.Register Description ■ 4MHz Timer Data Register (CUTR1/CUTR2) 4MHz Timer Register1 high byte Address : 0004B4H Read/write ⇒ Default value⇒ 4MHz Timer Register1 low byte Address : 0004B5 Read/write ⇒ Default value⇒ 4MHz Timer Register2 high byte Address : 0004B6 Read/write ⇒...
Page 985 BIT[0]: INTEN - Interrupt enable interrupt disabled (default) interrupt enabled This is the interrupt enable bit corresponding to the INT bit. When this bit is set to 1 and the INT bit is set by the hardware, the calibration module signals an interrupt to the CPU. The INT-bit itself is not affected by the INTEN bit and is set by hardware even if interrupts are disabled (INTEN=0).
Page 986 Chapter 50 Subclock Calibration Unit 5.Register Description 5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD) The 32kHz/100kHz Timer Data Register (CUTD) holds the value which determines the duration of calibration (32kHz/100kHz reload value) 32/100kHz Timer Register high byte Address : 0004B2 Read/write ⇒...
Page 987 Table 5-1 32kHz : Ideal measurement results depending on measurement duration The duration of the whole process from writing a 1 into the STRT bit until STRT is reset by hardware is longer than the actual calibration measurement time, due to synchronization between the different clock domains.
Page 988 Chapter 50 Subclock Calibration Unit 5.Register Description 5.3 4 MHz Timer Data Register (24 bits) (CUTR) The Timer Data Register (CUTR) holds the value of the calibration result (4MHz counter) Precaution: Reading this register during calibration, results in random values. The end of calibration is indicated by the INT-bit and the STRT-bit in the CUCR-register.
Page 989: Application Note
6. Application Note This section lists application notes concerning accuracy of the calibration, power dissipation and measurement duration. ● 32kHz The setting of the 32KHz Timer Data Register can be calculated in the following way. If the duration of 1 second is desired for the calibration, 8000Hex = 32768Dec should be set in the 32kHz Timer Data Register and it represents 32,768 pulses of the 32.768kHz oscillation clock.
Page 990: Power Dissipation
Chapter 50 Subclock Calibration Unit 6.Application Note ■ Accuracy: The accuracy of the calibration is dependent on the clock frequency used by the 4MHz Timer and duration of the calibration. The maximum error of the 4MHz timer is +/- 1 digit. If the clock frequency is 4MHz and duration of the calibration is 1 second, the achieved accuracy is calculated in the following way: 0.25us (Clock cycle time) / 1 second (duration)=0.25 ppm.
Page 991: Chapter 51 Low Voltage Reset/Interrupt
Chapter 51 Low Voltage Reset/Interrupt 1. Overview • Module for generating a low voltage reset or interrupt depending on the supply state of either the internal or external supply voltage. 2. Features • Generates a low voltage reset or a low voltage interrupt •...
Page 992: Registers
Chapter 51 Low Voltage Reset/Interrupt 3.Registers 3. Registers 3.1 LV Detection Control Registers Controls the low voltage detection function. • LVDET: Address 04C5h (Access: Byte, Halfword, Word) LVSEL LVEPD R0/W0 (See “Meaning of Bit Attribute Symbols (Page • Bit7: Reserved bit. The read value is always ‘0’. •...
Page 993 • LVSEL: Address 04C4h (Access: Byte, Halfword, Word) LVESEL3 LVESEL2 LVESEL1 (See “Meaning of Bit Attribute Symbols (Page • Bit7-4: External LV detection voltage level LVESEL3-LVESEL0 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 • Bit3-0: Internal LV detection voltage level LVISEL3-LVISEL0 0111 0110...
Page 994 Chapter 51 Low Voltage Reset/Interrupt 3.Registers...
Page 995: Chapter 52 Regulator Control
Chapter 52 Regulator Control 1. Overview • Module for controlling the behaviour of the MAIN-Regulator and SUB-Regulator in the device modes. 2. Features • Main Regulator enable and disable independently for Sub-run and STOP/RTC • Main regulator standby flag output •...
Page 996: Registers
Chapter 52 Regulator Control 3.Registers 3. Registers 3.1 Regulator Control Registers Controls the regulator function. • REGCTR: Address 04CFh (Access: Byte, Halfword, Word) R0/WX R0/WX R0/WX (See “Meaning of Bit Attribute Symbols (Page • Bit7-5: Reserved bit. The read value is always “0”. •...
Page 997 • REGSEL: Address 04CEh (Access: Byte, Halfword, Word) FLASHSEL MAINSEL R0/WX R0/WX (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bit. The read value is always “0”. • Bit5: Flash memory supply mode. FLASHSEL Flash memory operation mode is 1.8V [Initial value] Flash memory operation mode is 1.9V Note: Please check with the related device datasheet if this setting is supported.
Page 998 Chapter 52 Regulator Control 3.Registers...
Page 999: Chapter 53 Fixed Mode-Reset Vector / Boot-Rom
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 1. Overview The Boot ROM is a ﬁxed start-up routine, which is located at memory addresses 0xB000 to 0xBFFF. The entry point 0xBFF8 is determined by the Fixed Reset Vector if the device is conﬁgured with the mode pins set to MD[2:0]=”000”...
Page 1000 Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.Check for Boot Conditions *1) Boot-Security-Vector points to address in valid address range (0x04:000 – 0x13:FFFF)? *2) Start user application at address given by Boot Security Vector *3) Start user application at default user program entry address *4) Timeout about 100 ms Flow Chart of checking boot conditions on MB91V460...
Page 1001 2.2 Flash devices of MB91460 series (MB91F46x) After the chip initialization and saving the RSRR (Reset Cause Register) to CPU register R4, there is a check for boot conditions. All Flash devices have two Boot Security Vectors (BSV1: 0x14:8004, BSV2: 0x14:800C). These vectors are located in parallel sector to the Flash Security Vectors (FSV1, FSV2): The Flash Security Vectors are used for conﬁguring the protection mode of the ﬂash memory sectors and do no inﬂuence startup of Boot ROM.
Page 1002 Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.Check for Boot Conditions the internal bootloader is entered. Otherwise Boot ROM is left and application is also started at default user program entry address 0x0F:4000. *1) Boot Security Vector points to address in Flash-ROM *2) Magic Number = 0x0A897A? *3) Start user application at address given by Boot Security Vector 1/2 *4) Start user application at default user program entry address...

This manual is also suitable for:

Fr60 Mb91460 series

Fujitsu MB91460 SERIES FR60 User Manual

Chapter 1 Introduction

Chapter 2 MB91460 Rev.a/Rev.b Overview

Chapter 3 MB91460 Series Basic Information

Chapter 4 CPU Architecture

Chapter 5 CPU Registers

Chapter 6 EIT: Exceptions, Interrupts and Traps

Chapter 7 Branch Instruction

Chapter 8 Device State Transition

Chapter 9 Reset

Chapter 10 Standby

Chapter 11 Memory Controller

Chapter 12 Instruction Cache

Chapter 13 Clock Control

Chapter 14 PLL Interface

Chapter 15 CAN Clock Prescaler

Chapter 16 Clock Supervisor

Chapter 17 Clock Modulator

Chapter 18 Timebase Counter

Chapter 19 Timebase Timer

Chapter 20 Software Watchdog Timer

Chapter 21 Hardware Watchdog Timer

Chapter 22 Main Oscillation Stabilisation Timer

Chapter 23 Sub Oscillation Stabilisation Timer

Chapter 24 Interrupt Control

Chapter 25 External Interrupt

Chapter 26 DMA Controller

Chapter 27 Delayed Interrupt

Chapter 28 Bit Search

Chapter 29 MPU / EDSU

Chapter 30 I/O Ports

Chapter 31 External Bus

Chapter 32 USART (LIN / FIFO)

Chapter 33 I2C Controller

Chapter 34 CAN Controller

Chapter 35 Free-Run Timer

Chapter 36 Input Capture

Chapter 37 Output Compare

Chapter 38 Reload Timer

Chapter 39 Programmable Pulse Generator

Chapter 40 Pulse Frequency Modulator

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Summary of Contents for Fujitsu MB91460 SERIES FR60