Table of Contents
Chapter 32 USART (LIN / FIFO)
5.USART Interrupts
Transmission
Reception IRQ
5.1 Reception Interrupt Generation and Flag Set Timing
The following are the reception interrupt causes: Completion of reception (SSR04: RDRF) and occurrence of a
reception error (SSR04: PE, ORE, or FRE).
■ Reception Interrupt Generation and Flag Set Timing
Generally a reception interrupt is generated, if the received data is complete (RDRF = 1) and the Reception
Interrupt Enable (RIE) flag bit of the Serial Status Register (SSR04) was set to "1". This interrupt is generated
if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM =
0).
(Note)
If a reception error has occurred, the Reception Data Register (RDR04) contains invalid data in each
mode.
Receive data
(mode 0/3)
Receive data
(mode 1)
Receive data
(mode 2)
PE*, FRE
RDRF
ORE**
(if RDRF = "1")
* The PE flag will always remain "0" in mode 1 or 3
ST: Start Bit
(Note)
The example in figure
640
Figure 5-1 Bus idle interrupt generation
data
Reception
data
TBI
RBI
: Start bit
: Stop bit
Figure 5-2 Reception operation and flag set timing
ST
D0
ST
D0
D0
SP: Stop Bit
5-2
does not show all possible reception options for mode 0 and 3. Here it is:
: Data bit
D1
D2
....
D5
D1
D2
....
D6
D1
D2
....
D4
A/D: Mode 1 (multi processor) address/data selection bit
D6
D7/P
SP
ST
D7
A/D
SP
ST
D5
D6
D7
D0
reception interrupt occurs
Table of Contents
