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Chapter 20 Software Watchdog Timer
3.Configuration
3. Configuration
Timebase counter
(26-bit counter)
0
1
2
3
Base clock
1
2
3
4
2
2
2
2
2
(φ)
Timer clear
CT BR
CT BR
Clears the counter
after writing "A5h"
and then "5Ah".
274
Figure 3-1 Configuration Diagram
13 14 15 16 17 18 19 20 21 22 23 24 25
14
15
16
17
18
19
20
21
22
23
24
2
2
2
2
2
2
2
2
2
2
Watchdog timer
WT1-WT0
RSRR:bit2-1
φ
0
0
0
0
φ
0
0
1
1
φ
1
1
0
0
φ
1
1
1
1
Figure 3-2 List of Registers
-Sleep
-Stop
-Oscillation stability
wait RUN
Temporary stop
25
26
2
2
For watchdog detection
1-bit
counter
x
2
20
x
22
2
WPR
WPR
x
24
2
Clears the counter
x
2
26
after writing "A5h"
and then "5Ah".
Watchdog reset
WIF
WIF
OSCR:bit 7
To the reset
0
0
Without interrupt request
circuit
1
With interrupt request
WRITE; 0: Flag clear
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