Table of Contents
Chapter 16 Clock Supervisor
4.Operation Modes
■ Re-enabling the RC-oscillator and the clock supervisors
The initial point of this scenario is that the RC-oscillator and both main clock and sub-clock supervisor are
disabled.
•
The RC-oscillator can be enabled by setting RCE (bit 4 of CSVCR) to '1'.
•
The main clock supervisor is enabled by setting MSVE (bit 3 of CSVCR) to '1'. Enabling of the main clock
supervisor must only take place 100 s after the RC-oscillator is enabled. The software has to take care that
this time constraint is met.
•
The sub- clock supervisor is enabled by setting SSVE (bit 2 of CSVCR) to '1'. Enabling of the sub-clock
supervisor must only take place 100 s after the RC-oscillator is enabled. The software has to take care that
this time constraint is met.
Figure 4-7 Timing Diagram: Re-enabling the RC-oscillator and the clock supervisors
PONR
MCLK
SCLK
RC_CLK
OSC_STAB
TO_MCLK
TO_SCLK
MSVE
MSEN
SSVE
SSEN
MCLK_STBY
SCLK_STBY
SRST
EXT_RST
EXT_RST_OUT
MCLK_OUT
SCLK_OUT
MCLK_MISSING
SCLK_MISSING
232
µ
µ
RCE
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