Table of Contents
Chapter 32 USART (LIN / FIFO)
2.USART Configuration
2. USART Configuration
■ USART consists of the following blocks:
• Reload Counter
• Reception Control Circuit
• Reception Shift Register
• Reception Data Register
• Transmission Control Circuit
• Transmission Shift Register
• Transmission Data Register
• Error Detection Circuit
• Oversampling Unit
• Interrupt Generation Circuit
• LIN Break Generation
• LIN Break and Synch Field Detection
• Bus Idle Detection Circuit
• Serial Mode Register (SMR04)
• Serial Control Register (SCR04)
• Serial Status Register (SSR04)
• Extended Com. Contr. Reg. (ECCR04)
• Extended Status/Contr. Reg. (ESCR04)
• FIFO Control Register (FCR04)
• FIFO Status Register (FSR04)
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