Figure 5-20 SM-I/O PELV digital input logic diagram
T7 digital
input 5 state
X.05
T7 digital input 5
NOTE
The performance of the freeze input is highly dependant upon the quality of the signal driving it. If negative edge triggering is used then care should
be taken to ensure that the input is actively pulled low via low impedance. If positive edge triggering is used then care should be taken to ensure that
the input is actively pulled high, or pulled high via a suitably low pull-up resistance.
Figure 5-21 SM-I/O PELV relay logic diagram
Relay 1
Relay 2
Input
terminals
Output
terminals
The parameters are all shown at their default setting
Figure 5-22 SM-I/O PELV analog input logic diagram (current mode)