Sm-I/O Pelv Digital Input Logic Diagram; Sm-I/O Pelv Relay Logic Diagram; Sm-I/O Pelv Analog Input Logic Diagram (Current Mode) - Emerson unidrive sp User Manual

Universal variable speed ac drive for induction and servo motors
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Parameter
Keypad and
Parameter
structure
display
x.00
Figure 5-20 SM-I/O PELV digital input logic diagram
T7 digital
input 5 state
X.05
T7 digital input 5
NOTE
The performance of the freeze input is highly dependant upon the quality of the signal driving it. If negative edge triggering is used then care should
be taken to ensure that the input is actively pulled low via low impedance. If positive edge triggering is used then care should be taken to ensure that
the input is actively pulled high, or pulled high via a suitably low pull-up resistance.
Figure 5-21 SM-I/O PELV relay logic diagram
Relay 1
Relay 2
Input
terminals
Output
terminals
The parameters are all shown at their default setting
Figure 5-22 SM-I/O PELV analog input logic diagram (current mode)
Analog input 1
8
+
_
9
mode selector
Unidrive SP Advanced User Guide
Issue Number: 10
Parameter
Advanced parameter
description format
descriptions
T7 digital
input 5 invert
X.15
x(-1)
X.17
Key
Read-write (RW)
0.XX
parameter
Read-only (RO)
0.XX
parameter
Analog input
1 level
X.40
X.38
X.41
Analog
Analog
input 1
input 1
x(-1)
scaling
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Serial comms
Macros
protocol
T7 digital input 5
destination
X.25
Any
unprotected
bit
parameter
??.??
??.??
Analog
input 1
destination
Any
unprotected
X.43
variable
parameter
??.??
??.??
X.42
Analog input 1
invert
Electronic
Performance RFC mode
nameplate
Menus 15 to 17
SM-I/O PELV
305

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