Table of Contents
19.2
Registers and Sector/Bank Configuration of Flash Memory
This section explains the registers and the sector/bank configuration of flash memory.
I List of Registers and Reset Values of Flash Memory
Figure 19.2-1 List of Registers and Reset Values of Flash Memory
Flash memory control status
register (FMCS)
Flash memory write control
register (FWR0)
Flash memory write control
register (FWR1)
´: Undefined
I Sector and Bank Configuration of 512 Kbit Flash Memory
Figure 19.2-2 "Sector Configuration of 512 Kbit Flash Memory"" shows the sector configuration of
512 Kbit flash memory. The upper and lower addresses of each sector are given in the figure.
G
Sector configuration
For access from the CPU, the FF bank register has SA0 to SA9.
G
Bank configuration
The flash memory consists of two banks: upper one ranging from SA4 and SA9 and lower one
from SA0 and SA3.
CHAPTER 19 512 KBIT FLASH MEMORY
bit
7
6
5
0
0
0
bit
7
6
5
0
0
0
bit
7
6
5
0
0
0
4
3
2
1
0
´
0
0
0
0
4
3
2
1
0
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
577
Table of Contents
