Table of Contents
CHAPTER 5 Timebase timer
5.3
Configuration of Timebase Timer
This section explains the registers and interrupt factors of the timebase timer.
I List of Registers and Reset Values of Timebase Timer
Figure 5.3-1 List of Registers and Reset Values of Timebase Timer
Timebase timer control register
(TBTC)
×
: Undefined
I Generation of Interrupt Request from Timebase Timer
When the selected timebase timer counter bit reaches the interval time, the overflow interrupt request flag
bit in the timebase timer control register (TBTC: TBOF) is set to "1".If the overflow interrupt request flag
bit is set (TBTC: TBOF = 1) when the interrupt is enabled (TBTC: TBIE = 1), the timebase timer generates
an interrupt request.
196
bit
15
14
13
12
×
×
1
0
11
10
9
8
0
1
0
0
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