Page 1 FUJITSU SEMICONDUCTOR CM44-10127-1E CONTROLLER MANUAL ® -16LX 16 bit Microcontroller MB90895 series Hardware Manual...
Page 3 ® -16LX 16 bit Microcontroller MB90895 series Hardware Manual FUJITSU LIMITED...
Page 5 ASICs (application specific ICs) and were developed as general-purpose products in the MC-16LX series. This manual describes the functions and operation of the MB90895 series and is intended for engineers who intend to use MB90895 series microcontrollers to develop actual products. Please read through this manual.
Page 6 I Organization of this document This manual contains the following 21 chapters and an appendix. CHAPTER 1 Overview This chapter describes the features and basic specifications of MB90895 series. CHAPTER 2 Handling Devices This chapter describes points to note when using the MB90895 series.
Page 7 module CHAPTER 19 512 KBIT FLASH MEMORY This section describes the functions and operations of the 512 Kbit flash memory. CHAPTER 20 Dual Operation Flash This section describes the functions and operations of the dual operation flash. CHAPTER 21 FLASH SERIAL PROGRAMMING CONNECTION EXAMPLE This section describes the functions and operations of the flash serial programming connection example.
Page 9 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW....................1 Features of the MB90895 series......................2 Product Lineup for MB90895 Series....................4 Block Diagram of MB90895 Series...................... 7 Pin Assignment............................ 8 Package Dimensions ........................... 9 Pin Description........................... 10 I/O Circuit............................13 CHAPTER 2 HANDLING DEVICES ................. 15 Precautions when Handling Devices ....................
Page 12 3.5.9 Software interrupt ......................... 77 3.5.10 Interrupts by extended intelligent I/O service (EI OS) ..............78 3.5.11 OS descriptor (ISD) ......................... 80 3.5.12 Each Register of EI OS Descriptor (ISD) ..................82 3.5.13 Operation of EI OS........................85 3.5.14 Procedure for Use of EI OS ......................
Page 13 4.4.1 Registers for Port 2 (PDR2, DDR2) .................... 170 4.4.2 Operation of Port 2 ........................171 Port 3 ............................... 173 4.5.1 Registers for Port 3 (PDR3, DDR3) .................... 175 4.5.2 Operation of Port 3 ........................176 Port 4 ............................... 178 4.6.1 Registers for Port 4 (PDR4, DDR4) ....................
Page 14 CHAPTER 8 16-bit reload timer..................245 Overview of 16-bit Reload Timer ..................... 246 Block Diagram of 16-bit Reload Timer..................... 249 Configuration of 16-bit Reload Timer....................252 8.3.1 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)..........255 8.3.2 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)..........257 8.3.3 16-bit Timer Registers (TMR0, TMR1) ..................
Page 15 11.5 Precautions when Using Delayed Interrupt Generation Module............327 11.6 Program Example of Delayed Interrupt Generation Module............328 CHAPTER 12 DTP/external interrupt ................329 12.1 Overview of DTP/External Interrupt ....................330 12.2 Block Diagram of DTP/External Interrupt..................331 12.3 Configuration of DTP/External Interrupt................... 333 12.3.1 DTP/external interrupt factor register (EIRR) ................
Page 16 14.4.2 Generation of Transmit Interrupt and Timing of Flag Set ............403 14.5 UART0 baud rate..........................405 14.5.1 Baud rate by dedicated baud rate generator ................407 14.5.2 Baud Rate by Internal Timer (16-bit Reload Timer)..............410 14.5.3 Baud rate by external clock ......................412 14.6 Explanation of Operation of UART0 ....................
Page 17 16.3.8 Transmit request register (TREQR) .................... 503 16.3.9 Transmit RTR register (TRTRR) ....................505 16.3.10 Remote frame receive waiting register (RFWTR) ............... 507 16.3.11 Transmission cancel register (TCANR) ..................509 16.3.12 Transmit complete register (TCR) ....................511 16.3.13 Transmit complete interrupt enable register (TIER) ..............513 16.3.14 Receive complete register (RCR) ....................
Page 18 19.7.1 Data Polling Flag (DQ7) ......................592 19.7.2 Toggle Bit Flag (DQ6) ........................ 594 19.7.3 Timing Limit Over Flag (DQ5) ....................595 19.7.4 Sector Erase Timer Flag (DQ3) ....................596 19.7.5 Toggle Bit 2 Flag (DQ2) ......................597 19.8 Details of Programming/Erasing Flash Memory ................599 19.8.1 Read/Reset State in Flash Memory ...................
Page 19: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter describes the features and basic specifications of MB90895 series. 1.1 Features of the MB90895 series 1.2 Product Lineup for MB90895 Series 1.3 Block Diagram of MB90895 Series 1.4 Pin Assignment 1.5 Package Dimensions 1.6 Pin Description...
Page 20: Features Of The Mb90895 Series
CHAPTER 1 OVERVIEW Features of the MB90895 series MB90895 series devices are 16-bit micro general-purpose controllers designed for applications which need high-speed real-time processing. The devices of this series are high-performance 16-bit CPU micro controllers em-ploying of the dual operation flash memory and CAN controller on LQFP-48 small package.
Page 21 CHAPTER 1 OVERVIEW Low-power consumption (standby) mode • Sleep mode (stops CPU clock) • Timebase timer mode (operates only oscillation clock and sub clock, timebase timer and watch timer) • Watch mode (operates only sub clock and watch timer) • Stop mode (stops oscillation clock and sub clock) •...
Page 22: Product Lineup For Mb90895 Series
CHAPTER 1 OVERVIEW Product Lineup for MB90895 Series MB90895 series is available in two types. This section provides the product lineup, CPU, and peripherals. I Product Lineup for MB90895 Series Table 1.2-1 Product Lineup for MB90895 Series MB90V495G MB90F897/S Classification...
Page 23 CHAPTER 1 OVERVIEW I CPU and peripheral functions of MB90895 series Table 1.2-2 CPU and peripheral functions of MB90895 series (1/2) MB90V495G MB90F897/S CPU function Number of basic instructions: 351 instructions Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum instruction execution time: 62.5 ns (at a machine clock frequency of 16 MHz)
Page 24 CHAPTER 1 OVERVIEW Table 1.2-2 CPU and peripheral functions of MB90895 series (2/2) MB90V495G MB90F897/S 8/10-bit A/D converter Channel count: 8 Resolution: 10 or 8 bits Conversion time: 6.125 µs (including sampling time at 16-MHz machine clock frequency) Two or more continuous channels can be converted sequentially (up to 8 channels)
Page 25: Block Diagram Of Mb90895 Series
CHAPTER 1 OVERVIEW Block Diagram of MB90895 Series Block diagram of MB90895 series is shown in the figure below. I Block Diagram of MB90895 Series Figure 1.3-1 Block Diagram of MB90895 Series X0,X1 Clock controller MC-16LX core X0A,X1A Watch timer...
Page 26: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment Pin assignment of MB90895 series is shown in the figure below. I Pin Assignment (FPT-48P-M26) Figure 1.4-1 Pin Assignment (FPT-48P-M26) P17/ PPG3 P16/ PPG2 P50/ AN0 P15/ PPG1 P51/ AN1 P14/ PPG0 P52/ AN2 P13/ IN3...
Page 27: Package Dimensions
CHAPTER 1 OVERVIEW Package Dimensions MB90895 series is available in one type of package. The package dimensions below are for reference only. Contact Fujitsu for the correct package dimensions. I Package Dimension of FPT-48P-M26 48-pin plastic LQFP Lead pitch 0.50 mm Package width ×...
Page 28: Pin Description
CHAPTER 1 OVERVIEW Pin Description This section describes the I/O pins and their functions of MB90895 series. I Pin Description Table 1.6-1 Pin Description (1/3) Number Circuit Pin Name Functional description Type − power input pin for A/D converter Power (Vref+) input pin for A/D converter. The power supply should not be input V −...
Page 29 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (2/3) Number Circuit Pin Name Functional description Type − Power (0 V) input pin Capacity pin for stabilizing power supply. This pin should be connected to a ceramic − capacitor of approx.0.1µF. High-speed oscillation pin High-speed oscillation pin P10 to P13 General-purpose I/O port...
Page 30 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (3/3) Number Circuit Pin Name Functional description Type X1A* Low-speed oscillation pin. P36* General-purpose I/O port − power input pin for A/D converter *: MB90F897:X1A,X0A MB90F897S:P36,P35...
Page 31: I/O Circuit
CHAPTER 1 OVERVIEW I/O Circuit I/O circuit of MB90895 series is shown in the figure below. I I/O Circuit Table 1.7-1 I/O Circuit (1/2) Classifi Circuit Remarks cation • Approximately 1MΩ high speed oscillation feedback resistor. • Oscillation feedback resistor for low speed approximately Clock input 10MΩ...
Page 32 CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit (2/2) Classifi Circuit Remarks cation • CMOS hysteresis input V cc • CMOS-level output • Also used as analog input pin • Standby control provided Digital output • Automotive Input Digital output V ss Hysteresis input Standby control automotive input...
Page 33: Chapter 2 Handling Devices
CHAPTER 2 HANDLING DEVICES This chapter describes the precautions when handling the general-purpose one chip micro-controller. 2.1 Precautions when Handling Devices...
Page 34: Precautions When Handling Devices
Using External Clock" shows an use example of external clock. Figure 2.1-1 Example of Using External Clock Open MB90895 Series Precautions when not using sub clock If an oscillator is not connected to the X0A and X1A pins, connect the X0A pin to Pull-down resistor and leave the X1A pin open.
Page 35 Crystal oscillator circuit • Noise near the X0 and X1 pins may cause MB90895 series to malfunction. When designing a PC board using the device, place the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent the wiring patterns for the X0 and X1 pins from crossing.
Page 36 CHAPTER 2 HANDLING DEVICES...
Page 37: Chapter 3 Cpu
CHAPTER 3 This chapter explains the CPU functions of the MB90895 series. 3.1 Memory Space 3.2 Dedicated Registers 3.3 General-purpose Register 3.4 Prefix Code 3.5 Interrupt 3.6 Reset 3.7 Clock 3.8 Low-power Consumption Mode 3.9 CPU Mode...
Page 38: Memory Space
CHAPTER 3 CPU Memory Space The memory space of the F MC-16LX is 16 MB and is allocated to I/O, programs, and data. Part of the memory space is used for specific uses such as the expansion intelligent I/O service (EI OS) descriptors, the general-purpose registers, and the vector tables.
Page 39 CHAPTER 3 CPU I ROM Area Vector table area (address: FFFC00 to FFFFFF • The vector table is provided for reset and interrupts. • This area is allocated at the top of the ROM area. And The starting address of the corresponding processing routine is set to the address of each vector table as data.
Page 40: Mapping Of And Access To Memory Space
I Memory Map for MB90895 Series In MB90895 series, the internal address bus is output up to a width of 24 bits and the external address bus is output up to a width of 24 bits; the external access memory can access up to the 16-MB memory space.
Page 41 CHAPTER 3 CPU I Image Access to Internal ROM In the F MC-16LX family, with the internal ROM in operation, ROM data in the FF bank can be seen as an image in the top 00 bank. This function is called ROM mirroring and enables effective use of a small C compiler.
Page 42: Memory Map
3.1.2 Memory Map MB90895 series memory map is shown for each device. I Memory Map Figure 3.1-3 "Memory Map of MB90895 Series" shows the memory map for MB90895 series. Figure 3.1-3 Memory Map of MB90895 Series MB90F897/S MB90V495G Internal ROM...
Page 43: Addressing
CHAPTER 3 CPU 3.1.3 Addressing Linear and bank types are available for addressing. The F MC-16LX family basically uses bank addressing. • Linear type: direct-addressing all 24 bits by instruction • Bank type: addressing higher 8 bits by bank registers suitable for the use, and lower 16 bits by instruction I Linear Addressing and Bank Addressing The linear addressing is to access the 16-MB memory space by direct-addressing.
Page 44: Linear Addressing
CHAPTER 3 CPU 3.1.4 Linear Addressing The linear addressing has the following two types: • Direct-addressing 24 bits by instruction • Using lower 24 bits of 32-bit general-purpose register for address I Linear Addressing by Specifying 24-bit Operand Figure 3.1-5 Example of 24-bit Physical Direct Addressing in Linear Type JMPP 123456 Old program bank 452D...
Page 45: Bank Addressing
CHAPTER 3 CPU 3.1.5 Bank Addressing The bank addressing is a type of addressing each of 254 64-KB banks into which the 16- MB memory space is divided, using the bank register, and the lower 16 bits by an instruction. The following five types of bank registers are available for different purposes.
Page 46 CHAPTER 3 CPU Figure 3.1-7 "Example of Bank Addressing" shows the relationships between the memory space divided into banks and each register. Figure 3.1-7 Example of Bank Addressing 0 0 0 0 0 0 0 7 0 0 0 0 System stack space SSB (System stack bank register) 07FFFF...
Page 47: Allocation Of Multi-Byte Data In Memory
CHAPTER 3 CPU 3.1.6 Allocation of Multi-byte Data in Memory Multi-byte data is written to memory in sequence starting from the low addresses. For 32- bit length data, the lower 16 bits are written first, and then the higher 16 bits are written.
Page 48 CHAPTER 3 CPU I Storage of Multi-byte Data in Stack Figure 3.1-10 "Storage of Multi-byte Data in Stack" shows the order in which multi-byte data is stored in the stack. Figure 3.1-10 Storage of Multi-byte Data in Stack PUSHW RW1,RW3 Lower address PUSHW RW1, 35A4...
Page 49: Dedicated Registers
CHAPTER 3 CPU Dedicated Registers The CPU has the following dedicated registers. • Accumulator • User stack pointer • System stack pointer • Processor status • Program counter • Direct page register • Bank registers (program bank register, data bank register, user stack bank register, system stack bank register, additional data bank register) I Configuration of Dedicated Registers Figure 3.2-1 Configuration of Dedicated Registers...
Page 50 CHAPTER 3 CPU Table 3.2-1 Reset Values of Dedicated Registers Dedicated Registers Reset Value Accumulator (A) Undefined User stack pointer (USP) Undefined System stack pointer (SSP) Undefined Processor status (PS) bit15 bit13 bit12 bit8 bit7 bit0 0 0 0 0 0 0 0 0 0 1 x x x x x Value of reset vector (data at FFFFDC and FFFFD...
Page 51: Dedicated Registers And General-Purpose Register
CHAPTER 3 CPU 3.2.1 Dedicated Registers and General-purpose Register The F MC-16LX family has two types of registers: dedicated registers in the CPU and general-purpose register in the internal RAM. I Dedicated Registers and General-purpose Register The dedicated registers are limited to the use in the hardware architecture of the CPU. The general-purpose registers are in the internal RAM in the CPU address space.
Page 52: Accumulator (A)
CHAPTER 3 CPU 3.2.2 Accumulator (A) The accumulator (A) consists of two 16-bit length operation registers (AH and AL) used for temporary storage of the operation result or data. The accumulator can be used as a 32-, 16-, or 8-bit register to perform various operations between the AH and AL registers and memory or other registers.
Page 53 CHAPTER 3 CPU Byte processing arithmetic operation of accumulator When the arithmetic operation instruction for byte processing is executed for the AL register, the higher 8 bits of the AL register in pre-operation are ignored, and the higher 8 bits of the operation result become all "0".
Page 54 CHAPTER 3 CPU Figure 3.2-6 Example of 16-bit Data Transfer to Accumulator (A) (Data Saving) (Instruction of following execution; MOVW A,@RW1+6 - Reading by the result(RW1 contents + 8-bit length offset) as address - Storing the data contents in register A Memory space Before XXXX...
Page 55: Stack Pointer (Usp, Ssp)
CHAPTER 3 CPU 3.2.3 Stack Pointer (USP, SSP) The stack pointers include a user stack pointer (USP) and a system stack pointer (SSP). Both these pointers indicate the address where saved data and return data are stored when the PUSH instruction, the POP instruction, and the subroutine are executed. •...
Page 56 CHAPTER 3 CPU Figure 3.2-8 "Stack Operation Instructions and Stack Pointers" shows an example of the stack operation using the system stack. Figure 3.2-8 Stack Operation Instructions and Stack Pointers PUSHW A when S flag is "0" A624 F328 C6F327 C6F326 Before execution...
Page 57 CHAPTER 3 CPU I Stack Area Securing stack area The stack area is used to save and return the program counter (PC) at execution of the interrupt processing, subroutine call instruction (CALL) and vector call instruction (CALLV). It is also used to save and return temporary registers using the PUSHW and POP The stack area is secured with the data area in RAM.
Page 58: Processor Status (Ps)
CHAPTER 3 CPU 3.2.4 Processor status (PS) The processor status (PS) consists of the bits controlling CPU and various bits indicating the CPU status. The processor status (PS) consists of the following three registers. • Interrupt level mask register (ILM) •...
Page 59 CHAPTER 3 CPU 3.2.4.1 Condition Code Register (PS: CCR) The condition code register (CCR) is an 8-bit register consisting of bits indicating the result of instruction execution, and the bits enabling or disabling the interrupt request. I Configuration of Condition Code Register (CCR) Figure 3.2-11 "Configuration of Condition Code Register (CCR)"...
Page 60 CHAPTER 3 CPU Zero flag (Z) If all the bits of the operation result are "0", this flag is set to "1". If any 1 bit is "1", the flag is cleared to "0". Overflow flag (V) If an overflow occurs as a signed numeric value at the execution of operation, this flag is set to "1". If no overflow occurs, the flag is cleared to "0".
Page 61 CHAPTER 3 CPU 3.2.4.2 Register Bank Pointer (PS: RP) The register bank pointer (RP) is a 5-bit register that indicates the starting address of the currently used general-purpose register bank. I Register bank pointer (RP) Figure 3.2-12 "Configuration of Register Bank Pointer (RP)" shows the configuration of the register bank pointer (RP).
Page 62 CHAPTER 3 CPU 3.2.4.3 Interrupt Level Mask Register (PS: ILM) The interrupt level mask register (ILM) is a 3-bit register indicating the interrupt level accepted by the CPU. I Interrupt level mask register (ILM) Figure 3.2-14 shows the configuration of the interrupt level mask register (ILM). Figure 3.2-14 Configuration of Interrupt Level Mask Register (ILM) bit15 13 12 11 10...
Page 63: Program Counter (Pc)
CHAPTER 3 CPU 3.2.5 Program counter (PC) The program counter (PC) is a 16-bit counter indicating the lower 16 bits of the address for the next instruction code to be executed by the CPU. I Program counter (PC) The program bank register (PCB) indicates the higher 8 bits of addresses where the next instruction code to be executed by the CPU is stored;...
Page 64: Direct Page Register (Dpr)
CHAPTER 3 CPU 3.2.6 Direct page register (DPR) The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the low address directly specified using the operand when executing the instruction by the abbreviated direct addressing.
Page 65: Bank Register (Pcb, Dtb, Usb, Ssb, And Adb)
CHAPTER 3 CPU 3.2.7 Bank Register (PCB, DTB, USB, SSB, and ADB) The bank register sets the MSB 8 bit of the 24-bit address using bank addressing The following five registers are included. • Program bank register (PCB) • Data bank register (DTB) •...
Page 66: General-Purpose Register
CHAPTER 3 CPU General-purpose Register The general-purpose register is a memory block allocated to addresses "000180 " to "00037F " in the internal RAM in 1 bank units of 16 bits x 8. • General-purpose 8-bit register (byte registers R0 to R7) •...
Page 67 CHAPTER 3 CPU I Register Bank The register bank can be used as a general-purpose register (byte registers R0 to R7, word registers RW0 to RW7, and long-word registers RL0 to RL3) to perform various operations or to serve as a pointer. The long- word register can also be used as a linear addressing to directly access the entire memory space.
Page 68: Prefix Code
CHAPTER 3 CPU Prefix Code When prefix code is inserted by an instruction, the operation of the instruction can be changed partially. The prefix code has the following three types: • Bank select prefix (PCB, DTB, ADB, and SPB) • Common register bank prefix (CMR) •...
Page 69: Bank Select Prefix (Pcb, Dtb, Adb, And Spb)
CHAPTER 3 CPU 3.4.1 Bank select prefix (PCB, DTB, ADB, and SPB) When the bank select prefix codes precede an instruction, any memory space accessed by the instruction can be set, regardless of the addressing modes. I Bank select prefix (PCB, DTB, ADB, and SPB) Memory space used at data access is predetermined for each addressing mode.
Page 70 CHAPTER 3 CPU Table 3.4-3 Instructions Requiring Precaution When Using Bank Select Prefix Instruction Types Instruction Description Flag change instruction AND CCR,#imm8 The bank select prefix code affects up to the next instruction. OR CCR,#imm8 ILM setting instruction MOV ILM,#imm8 The bank select prefix code affects up to the next instruction.
Page 71: Common Register Bank Prefix (Cmr)
CHAPTER 3 CPU 3.4.2 Common register bank prefix (CMR) When the common register bank prefix (CMR) code precedes an instruction for accessing a general-purpose register, the general-purpose register to be accessed by the instruction can be changed to a common bank (register bank selected when the register bank pointer (RP) is 0) at 000180 to 00018F , regardless of the current value of...
Page 72: Flag Change Inhibit Prefix (Ncc)
CHAPTER 3 CPU 3.4.3 Flag change inhibit prefix (NCC) When the flag change inhibit prefix (NCC) code precedes an instruction for changing various flags of the condition code register (CCR), a flag change caused by instruction execution can be inhibited. I Flag change inhibit prefix (NCC) The flag change inhibit prefix (NCC) code is used to inhibit an unnecessary flag change.
Page 73: Restrictions On Prefix Code
CHAPTER 3 CPU 3.4.4 Restrictions on Prefix Code The use of the prefix codes is restricted as follows: • No interrupt request is accepted during execution of a prefix code and interrupt inhibit instruction. • When a prefix code precedes an interrupt inhibit instruction, The effect of the prefix code is delayed.
Page 74 CHAPTER 3 CPU Delay of the effect of the prefix code When a prefix code precedes an interrupt inhibit instruction, it affects the next instruction after the interrupt inhibit instruction. Figure 3.4-2 Interrupt Inhibit Instruction and Prefix Code Interrupt inhibit instruction MOV A,FF MOV ILM,#imm8 ADD A,01...
Page 75: Interrupt
CHAPTER 3 CPU Interrupt The F MC-16LX family has four interrupt functions for suspending the current processing to pass control to a separately defined program when a specific event occurs. • Hardware Interrupt • Software interrupt • Interrupts by extended intelligent I/O service (EI •...
Page 76 CHAPTER 3 CPU I Interrupt Operation Figure 3.5-1 shows interrupt start and return processing. Figure 3.5-1 General Flow of Interrupt Operation START Main program Valid interrupt ? Interrupt start/return processing During execution of string instruction* Starting the EI OS ? Fetch of next instruction and decode OS processing...
Page 77: Interrupt Factor And Interrupt Vector
CHAPTER 3 CPU 3.5.1 Interrupt Factor and Interrupt Vector The F MC-16LX family has vector tables corresponding to 256 types of interrupt factor. I Interrupt Vector The interrupt vector tables referenced at interrupt processing are allocated to the most significant addresses ("FFFC00 "...
Page 78 CHAPTER 3 CPU I Interrupt Factor, Interrupt Vector, and Interrupt Control Register Table 3.5-2 shows the relationships between the interrupt factor except software interrupt, and interrupt vector and interrupt control register. Table 3.5-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register Interrupt Vector Interrupt Control Register Priority...
Page 79 CHAPTER 3 CPU :Available :Not available :Interrupt factor corresponds to EI OS and has EI OS stop function : Interrupt factor can be used when not using interrupt sources sharing ICR register • The interrupt level for resources sharing an ICR register become the same. •...
Page 80: Interrupt Control Registers And Peripherals
CHAPTER 3 CPU 3.5.2 Interrupt Control Registers and Peripherals The interrupt control registers (ICR00 to ICR15) are allocated in he interrupt controller, and correspond to all peripherals with interrupt functions. The registers control the interrupt and extended intelligent I/O service (EI OS).
Page 81 CHAPTER 3 CPU Each interrupt control register (ICR) has the following four functions. Some functions of the interrupt control register (ICR) are different at write and read. • Setting of interrupt level of corresponding peripheral • Selection of whether to perform normal interrupt or EI OS for corresponding peripheral •...
Page 82: Interrupt Control Register (Icr00 To Icr15)
CHAPTER 3 CPU 3.5.3 Interrupt Control Register (ICR00 to ICR15) The functions of the interrupt control registers are shown below. I Interrupt Control Register (ICR00 to ICR15) Some functions differ depending on whether data is written to or read from the interrupt control registers. Figure 3.5-2 Interrupt Control Register (ICR00 to ICR15) at Write At writing Reset value...
Page 83 CHAPTER 3 CPU Figure 3.5-3 Interrupt Control Register (ICR00 to ICR15) at Read At read Reset value X X 0 0 0 1 1 1 bit0 bit2 bit1 Interupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (without interruption) bit3 OS enable bit When an interrupt occurs, start normal interrupt process...
Page 84: Function Of Interrupt Control Register
CHAPTER 3 CPU 3.5.4 Function of Interrupt Control Register The interrupt control registers (ICR00 to ICR15) consist of the following bits with four functions. • Interrupt level setting bits (IL2 to IL0) • EI OS enable bit (ISE) • EI OS channel select bits (ICS3 to ICS0) •...
Page 85 CHAPTER 3 CPU I Function of Interrupt Control Register Interrupt level setting bits (IL2 to IL0) Sets corresponding peripheral Functions of Interrupt Control Register. At reset, the bits are set to level 7 (IL2 to IL0 = "111 ": no interrupt). Table 3.5-4 shows the relationship between the interrupt level setting bits and interrupt levels.
Page 86 CHAPTER 3 CPU Table 3.5-5 Correspondence between EI OS Channel Select Bits and Descriptor Addresses (2/2) ICS3 ICS2 ICS1 ICS0 Channel to be Selected Descriptor Address 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 OS status bits (S1 and S0) When the S1 and S0 bits are read at the termination of the EI OS, the operating and end states can be checked.
Page 87: Hardware Interrupt
CHAPTER 3 CPU 3.5.5 Hardware Interrupt The hardware interrupt responds to the interrupt request from a resource, suspends the current-executing program and transfers control to the interrupt processing program defined by user. The hardware interrupt corresponds to the EI I Hardware Interrupt Function of hardware interrupt When a hardware interrupt occurs, the interrupt level (IR: IL) of the interrupt request from a peripheral resource is compared with the interrupt level mask register (PS: ILM) and the state of the interrupt enable...
Page 88 CHAPTER 3 CPU I Mechanism of Hardware Interrupt The mechanism related to hardware interrupts consists of the four sections. When starting the hardware interrupt, these four sections must be set by the program. Table 3.5-7 Mechanism Related to Hardware Interrupt Mechanism Related to Hardware Function Interrupt...
Page 89 CHAPTER 3 CPU Hardware interrupt inhibition by interrupt inhibit instruction Table 3.5-8 shows the hardware interrupt inhibit instructions. If a hardware interrupt occurs during execution of a hardware interrupt inhibit instruction, the interrupt is processed after execution of the hardware interrupt inhibit instruction and other instructions. Table 3.5-8 Hardware Interrupt Inhibit Instructions Prefix Code Interrupt Inhibit Instruction...
Page 90: Operation Of Hardware Interrupt
CHAPTER 3 CPU 3.5.6 Operation of Hardware Interrupt The operation from the generation of hardware interrupt request to the completion of interrupt processing is explained below. I Start of Hardware Interrupt Operation of peripheral (generation of interrupt request) The peripherals with a hardware interrupt request function have an interrupt request flag indicating the generation of an interrupt request, as well as an interrupt enable flag selecting between enabling and disabling an interrupt request.
Page 91 CHAPTER 3 CPU I Operation of Hardware Interrupt Figure 3.5-6 shows the operation from the generation of hardware interrupt to the completion of interrupt processing. Figure 3.5-6 Operation of Hardware Interrupt Internal bus PS,PC Micro code Check Comparator F MC-16LXCPU Other peripheral function Peripheral function of interrupt request generate...
Page 92: Procedure For Use Of Hardware Interrupt
CHAPTER 3 CPU 3.5.7 Procedure for Use of Hardware Interrupt The settings of the system stack area, resources, interrupt control registers (ICR) are required for using the hardware interrupt. I Procedure for Use of Hardware Interrupt Figure 3.5-7 shows an example of the procedure for use of the hardware interrupt. Figure 3.5-7 Procedure for Use of Hardware Interrupt Start Setting the system stack area...
Page 93: Multiple Interrupts
CHAPTER 3 CPU 3.5.8 Multiple interrupts Multiple hardware interrupts can be generated by setting different interrupt levels in the interrupt level setting bits of the interrupt control register (ICR: ILO to IL2) in response to multiple interrupt requests from the resource. However, multiple EI OS cannot be started.
Page 94 CHAPTER 3 CPU Example of multiple interrupts As an example of multiple interrupt processing, assuming that a timer interrupt is preferred to an A/D converter interrupt, set the interrupt level of the A/D converter to 2 and the interrupt level of the timer to 1. Figure 3.5-8 shows the processing of the timer interrupt generated during processing of the A/D converter interrupt.
Page 95: Software Interrupt
CHAPTER 3 CPU 3.5.9 Software interrupt The software interrupt is a function for transiting control from the current-executing program to the interrupt processing program defined by user by execution of a software interrupt instruction (INT instruction). The software interrupt is held during execution of a software interrupt.
Page 96: Interrupts By Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 CPU 3.5.10 Interrupts by extended intelligent I/O service (EI OS is a function to automatically transfer data between the peripherals (I/O) and memory. It generates the hardware interrupt at termination of data transfer. I EI The EI OS provides automatic data transfer between the I/O area and memory. When data transfer is terminated, the termination factor (end condition) is set, branching automatically to the interrupt processing routine.
Page 97 CHAPTER 3 CPU I Operation of EI Figure 3.5-9 shows the operation of the EI Figure 3.5-9 Operation of EI Memory space By IOA I/O area 00 Bank area Interrupt request By ICS Interrupt control register (ICR) Interrupt controller By BAP Buffer Count by DCT ISD :EI...
Page 98: Ei Os Descriptor (Isd)
CHAPTER 3 CPU 3.5.11 OS descriptor (ISD) The EI OS descriptor (ISD) is allocated to the addresses "000100 " to "00017F " in the internal RAM, and consists of 8 bytes x 16 channels. I Configuration of EI OS Descriptor (ISD) ISD consists of 8 bytes x 16 channels, and each ISD is composed as shown in Figure 3.5-10.
Page 99 CHAPTER 3 CPU Table 3.5-9 EI OS Descriptor (ISD) Area (2/2) Channel Descriptor header Address (ICR: ICS3 to ICS0) 000140 000148 000150 000158 000160 000168 000170 000178...
Page 100: Each Register Of Ei 2 Os Descriptor (Isd)
CHAPTER 3 CPU 3.5.12 Each Register of EI OS Descriptor (ISD) The EI OS descriptor (ISD) consists of the following registers. • Data counter (DCT) • I/O address pointer (IOA) • EI OS status register (ISCS) • Buffer address pointer (BAP) The reset value of each register is undefined and a reset should be performed carefully.
Page 101 CHAPTER 3 CPU I EI OS Status Register (ISCS) The EI OS status register (ISCS) is an 8-bit register that sets the method to update the buffer address pointer and I/O address pointer, transfer data format (byte/word), and transfer direction. Figure 3.5-13 shows the bit configuration of the EI OS status register (ISCS).
Page 102 CHAPTER 3 CPU I Buffer address pointer (BAP) The buffer address pointer (BAP) is a 24-bit register and sets the 16-MB addresses where data is transferred to or from I/O area. When the BAP updating/fixing select bit of the EI OS status register (ISCS: BF) is set to updated (ISCS: BF=0), the buffer address pointer (BAP) changes only in the lower 16 bits (BAPH, BAPL) and does not change in the higher 8 bits (BAPH).
Page 103: Operation Of Ei 2 Os
CHAPTER 3 CPU 3.5.13 Operation of EI The flowchart of operation of the EI OS using the microcode in the CPU is shown below: I Operation of EI Figure 3.5-15 Flowchart of Operation of EI Interrupt request generate : EI OS descriptor from peripheral resource ISCS...
Page 104: Procedure For Use Of Ei 2 Os
CHAPTER 3 CPU 3.5.14 Procedure for Use of EI The procedure for using the EI OS is shown below: I Procedure for Use of EI Figure 3.5-16 Procedure for Use of EI Processing by software Processing by hardware Start Setting of system stack area Setting of EI OS Descriptor Setting of peripheral resource interruption...
Page 105: Ei 2 Os Processing Time
CHAPTER 3 CPU 3.5.15 OS Processing Time The time required for EI OS processing depends on the following factors: • Setting of EI OS status register (ISCS) • Data length of transfer data Some interrupt handling time is required at the transition to hardware interrupt processing after completion of data transfer.
Page 106 CHAPTER 3 CPU At end of data counter (DCT) (DCT ≠ 0, ISCS: SE=0) At completion of data transfer by the EI OS, since the hardware interrupt is started, the interrupt handling time is added. The EI OS processing time at the end of counting is calculated by the following expression. OS Processing Time after count finish OS Processing Time at continuing data transfer + (21 + 6 ×...
Page 107: Exception Processing Interrupt
CHAPTER 3 CPU 3.5.16 Exception Processing Interrupt The F MC-16LX family performs exception processing when an undefined instruction is executed. Exception is basically the same as interrupt. When an exception is detected between instructions, normal processing is suspended to perform exception processing. Exception processing is performed when an unexpected operation is performed, and should be used only for starting recovery software at debugging or in an emergency.
Page 108: Time Required To Start Interrupt Processing
CHAPTER 3 CPU 3.5.17 Time Required to Start Interrupt Processing The time for terminating the currently executing instruction plus the interrupt handling time is required from generation of the hardware interrupt request to execution of the interrupt-processing. I Time Required to Start Interrupt Processing The interrupt request sampling wait time and the interrupt handling time (time required for preparation for interrupt processing) are required from generation of the interrupt request and acceptance of interrupt, to execution of the interrupt processing.
Page 109 CHAPTER 3 CPU Table 3.5-13 Compensation Value (Z) of Interrupt Handling Time Address Set by Stack Pointer Compensation Value (Z) For internal area (even address) For internal area (odd address) Reference: One machine cycle is equal to one clock cycle of the machine clock (φ).
Page 110: Stack Operation For Interrupt Processing
CHAPTER 3 CPU 3.5.18 Stack Operation for Interrupt Processing When an interrupt request is accepted, the values of dedicated registers are automatically saved to the system stack before transition to interrupt processing. At completion of interrupt processing, the values of the dedicated registers are automatically returned from the system stack.
Page 111: Program Example Of Interrupt Processing
CHAPTER 3 CPU 3.5.19 Program Example of Interrupt Processing This section gives a program example of interrupt processing. I Program Example of Interrupt Processing Processing specification This is an example of interrupt program using external interrupt 4 (INT4). Coding example DDR2 000012H ;Port 2 direction register...
Page 112 CHAPTER 3 CPU ;----------Interupt program------------------------------------- ED_INT1: I:EIRR,#00H ;Prohibition of new INT4 reception RETI ;Recover from interrupt CODE ENDS ;----------Vector setting---------------------------------------- VECT CSEG ABS=0FFH 0FFD0H ;Setting vector to interrupt #11(0BH) ED_INT1 0FFDCH ;Setteing of reset vector START ;Setting to single chip mode VECT ENDS START...
Page 113 CHAPTER 3 CPU ;----------Main program----------------------------------- CODE CSEG START: CCR,#0BFH ;I flag of CCR in PS cleared to interrupt disabled RP,#00 ;Setting register bank pointer A,#!STACK_T ;Setting system stack SSB,A MOVW A,#STACK_T ;Setting system stack pointer MOVW SP,A ;in this case,S flag=1,so set to SSP I:DDR2,#00000000B ;Setting P24/INT4 pin to input BAPL,#00H...
Page 114: Reset
CHAPTER 3 CPU Reset When a reset trigger even occurs, the CPU immediately suspends the current process and starts the reset operation. The reset factors are as follows: • Power on reset • Watchdog timer overflow • Generation of software reset request •...
Page 115 CHAPTER 3 CPU inputting Low level from the RST pin requires at least 16 machine cycles (main clock). • An external reset does not require the oscillation stabilization wait time. • If an external reset request is generated from the RST pin during writing by a transfer Notes: instruction (such as MOV), the reset cancel wait state is set after completion of the transfer instruction, so writing is terminated normally.
Page 116: Reset Factors And Oscillation Stabilization Wait Times
Software reset None External reset None HCLK: Oscillation clock frequency *: MB90V495G requires 2 /HCLK. Figure 3.6-1 MB90895 series oscillation stabilization wait time at generating power-on reset CPU operation /HCLK Oscillation time of oscillator /HCLK Wait time for stabilizing oscillation...
Page 117 CHAPTER 3 CPU Table 3.6-3 Oscillation stabilization wait time setting by clock select register (CKSCR) Clock select bit Oscillation Stabilization Wait Time Parenthesized values are examples calculated at an oscillation clock frequency of 4 MHz. /HCLK (256µs) /HCLK (approx.2.048ms) /HCLK (approx.4.1ms) *1,*2 /HCLK (approx.8.19ms) HCLK: Oscillation clock frequency...
Page 118: External Reset Pin
External Reset Pin The external reset pin (RST pin) is a reset input pin. Input of an external Low level generates a reset factor. MB90895 series starts the reset operation in synchronization between the CPU and clock. I Block Diagram of External Reset Pin Figure 3.6-2 Block Diagram of External Reset Pin...
Page 119: Reset Operation
CHAPTER 3 CPU 3.6.3 Reset Operation During reset operation, the mode for reading mode data and reset vectors is set according to the settings of the mode pins (MD0 to MD2) and a mode fetch is executed. When the oscillation clock is returned from stop states (power on, stop mode) by a reset, a mode fetch is executed after the elapse of the main clock oscillation stabilization wait time.
Page 120 CHAPTER 3 CPU I Mode Fetch At transition to the reset operation, the CPU automatically transfers mode data and reset vectors by hardware to the appropriate register in the CPU core. The mode data and reset vector are allocated to four bytes of addresses "FFFFDC "...
Page 121: Reset Factor Bit
CHAPTER 3 CPU 3.6.4 Reset Factor Bit To check reset factors, read the value of the watchdog timer control register (WDTC). I Reset Factor Bit Each reset factor provides a flip-flop circuit corresponding to each factor. The state of the flip-flop circuit can be checked by reading the value of the watchdog timer control register (WDTC).
Page 122 CHAPTER 3 CPU I Correspondence of Reset Factor Bit and Reset Factor Figure 3.6-6 shows the configuration of the reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST). Figure 3.6-6 Configuration of Reset Factor Bit bit7 bit6 bit5...
Page 123 CHAPTER 3 CPU I Notes on Reset Factor Bit Power on reset When a power on reset is executed, the PONR bit is set to "1" after completion of the reset operation. Any reset factor bit other than the PONR bit is undefined. When the PONR bit is "1" after completion of the reset operation, ignore the value of any bit other than the PONR bit.
Page 124: State Of Each Pin At Reset
CHAPTER 3 CPU 3.6.5 State of Each Pin at Reset This section explains the state of each pin at reset. I State of Pins at Reset The state of the pins during reset operation is determined by the settings of the mode pins (MD2 to MD0). When internal vector mode set: •...
Page 125: Clock
CHAPTER 3 CPU Clock The clock generation section controls the internal clock that is an operating clock for the CPU or resources. The clock generated by the clock generation section is called a machine clock and one cycle of the machine clock is a machine cycle. The clock to be supplied from a high-speed oscillator is called an oscillation clock and the 2- frequency division of the oscillation clock is called a main clock.
Page 126 CHAPTER 3 CPU Machine clock This clock is an operating clock for the CPU and the resources. One cycle of the machine clock is a machine cycle (1/φ). One clock can be selected from the main clock sub clock, and four types of PLL clock.
Page 127 CHAPTER 3 CPU I Clock Supply Map Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and peripherals. The operation of the CPU and peripheral peripherals is affected by switching between the main clock and subclock or PLL clock (clock mode) or by switching the PLL clock multiplier.
Page 128: Block Diagram Of Clock Generation Section
CHAPTER 3 CPU 3.7.1 Block Diagram of Clock Generation Section The clock generation section consists of the following five blocks: • Oscillation clock generator/sub clock generator • PLL multiplying circuit • Clock selector • Clock select register (CKSCR) • Oscillation stabilization wait time selector I Block Diagram of Clock Generation Section Figure 3.7-2 shows the block diagram of the clock generation section.
Page 129 CHAPTER 3 CPU Oscillation clock generator This generator generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external clock to the high-speed oscillation pins. Sub clock generator This generator generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to the low-speed oscillation pins (X0A, X1A).
Page 130: Register In Clock Generation Section
CHAPTER 3 CPU 3.7.2 Register in Clock Generation Section This section explains the register in the clock generation section. I Register in Clock Generation Section and List of Reset Values Figure 3.7-3 Clock Select Register and List of Reset Values Clock select register (CKSCR)
Page 131: Clock Select Register (Ckscr)
CHAPTER 3 CPU 3.7.3 Clock select register (CKSCR) The clock select register (CKSCR) is used to switch the clock mode between main clock, subclock, and PLL clock and to select the oscillation stabilization wait time and the PLL clock multiplier. I Clock select register (CKSCR) Figure 3.7-4 Clock select register (CKSCR) Reset value...
Page 132 CHAPTER 3 CPU Table 3.7-1 Functions of clock select register (CKSCR) (1/2) bit name Function bit9 CS1, CS0: The PLL clock multiplier is selected from among seven options depending on the combination of bit8 the multiplication rate PSCCR: CS2 and CKSCR: CS1/CS0. select bits Any reset causes the bit to return to the reset value.
Page 133 CHAPTER 3 CPU Table 3.7-1 Functions of clock select register (CKSCR) (2/2) bit name Function bit13 WS1, WS0: These bits are used to select an oscillation stabilization wait time required for the oscillation clock bit12 oscillation stabilization when the stop mode is canceled, when transition occurs from subclock mode to main clock mode, wait time select bit or when transition occurs from subclock mode to PLL clock •...
Page 134: Pll/Subclock Control Register (Psccr)
CHAPTER 3 CPU 3.7.4 PLL/subclock control register (PSCCR) The PLL/subclock control register (PSCCR) is used to switch the subclock frequency divide ratio (selecting division by 2 or 4) and to set the PLL clock multiplier (division by 1, 2, 3 or 4). I PLL/subclock control register (PSCCR) Figure 3.7-5 PLL/subclock control register (PSCCR) Address:003F...
Page 135 CHAPTER 3 CPU Table 3.7-3 PLL multipliler setting in PSCCR:CS2 and CKSCR:CS1/CS0 (Calculated assuming a frequency of 4 MHz) Function × HCLK (4 MHz) × HCLK (8 MHz) × HCLK (12 MHz) × HCLK (16 MHz) × HCLK(8 MHz) × HCLK(16 MHz) Unavailable Unavailable...
Page 136: Clock Mode
CHAPTER 3 CPU 3.7.5 Clock Mode Clock modes have a main clock mode, sub clock mode, and PLL clock mode. I Clock Mode Main clock mode In the main clock mode, a clock with 2-frequency division of the clock generated by connecting an oscillator or inputting an external clock to the high-speed oscillation pins (X0, X1) is used as the operating clock for the CPU or peripherals.
Page 137 CHAPTER 3 CPU Transition from sub clock mode to main clock mode When the sub clock select bit (CKSCR: SCS) is rewritten from "0" to "1", the sub clock switches to the main clock after the main clock oscillation stabilization wait time has elapsed. Notes: •...
Page 138 CHAPTER 3 CPU Figure 3.7-6 shows the transition of a clock mode. Figure 3.7-6 Clock Mode Transition → Main MCS=1 MCM=1 Main SCS=0 (10) MCS=1 MCS=1 SCM=1 MCM=1 MCM=1 CS1,CS0=xx (16) SCS=1 SCS=0 (10) SCM=1 SCM=0 (11) → Main CS1,CS0=xx CS1,CS0=xx MCS=1 MCM=1...
Page 139 CHAPTER 3 CPU (1) MCS bit "0" write (2) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=00 (3) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=01 (4) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=10 (5) Termination of PLL clock oscillation stabilization wait time &...
Page 140: Oscillation Stabilization Wait Time
CHAPTER 3 CPU 3.7.6 Oscillation Stabilization Wait Time At power on or return from the stop mode when the oscillation clock is stopped, a time until the oscillation clock stabilizes (oscillation stabilization wait time) is required after starting an oscillation.The oscillation stabilization wait time is also required for switching the clock mode from main clock mode to PLL clock or subclock mode and from subclock mode to main clock or PLL clock mode.
Page 141: Connection Of Oscillator And External Clock
3.7.7 Connection of Oscillator and External Clock MB90895 series has a system clock generator and generates an internal clock by connecting an oscillator to the oscillation pins. External clocks that are input to the oscillation pins can be used as oscillation clocks.
Page 142: Low-Power Consumption Mode
CHAPTER 3 CPU Low-power Consumption Mode The CPU operation modes are classified as follows according to the selection of the operation clock and the oscillation control of a clock. All the operation modes except the PLL clock mode are low-power consumption modes. •...
Page 143 CHAPTER 3 CPU I Clock Mode PLL clock mode In PLL clock mode, the CPU and peripherals operate on a PLL multiplying clock of oscillation clock (HCLK). Main clock mode In main clock mode, the CPU and peripherals operate on a clock with 2-frequency division of oscillation clock (HCLK).
Page 144 CHAPTER 3 CPU Timebase timer mode The timebase timer mode operates only the oscillation clock (HCLK), sub clock (SCLK), timebase timer, and watch timer.Resources other than the timebase timer and watch timer stop. Stop mode The stop mode stops the oscillation clock (HCLK) and sub clock (SCLK) during operation in each clock mode.It enables data to be retained with the least power consumption.
Page 145: Block Diagram Of Low-Power Consumption Circuit
CHAPTER 3 CPU 3.8.1 Block Diagram of Low-power Consumption Circuit This section shows block diagram of low-power consumption circuit. I Block Diagram of Low-power Consumption Circuit Figure 3.8-2 Block Diagram of Low-power Consumption Circuit Low power consumption mode control register (LPMCR) CG1 CG0 Reserved Pin High-Z...
Page 146 CHAPTER 3 CPU CPU intermittent operation selector This selector selects the halt cycle count of the CPU clock in the CPU intermittent operation mode. Standby controller The CPU clock controller and resource clock controller switch between the CPU operating clock and resource operating clock to enter and cancel the standby mode.
Page 147: Registers For Setting Low-Power Consumption Modes
CHAPTER 3 CPU 3.8.2 Registers for Setting Low-power Consumption Modes This section explains the registers to be used to set lower-power consumption modes. I Low-power Consumption Mode Control Register and Reset Values Figure 3.8-3 Low-power Consumption Mode Control Register and Reset Values Low power consumption control register (LPMCR)
Page 148: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 3 CPU 3.8.3 Low-power consumption mode control register (LPMCR) The low-power consumption mode control register (LPMCR) transits an operation mode to, and cancels the low-power consumption modes, generates an internal reset signal, and sets the halt cycle count in the CPU intermittent operation mode. I Low-power consumption mode control register (LPMCR) Figure 3.8-4 Low-power consumption mode control register (LPMCR) Reset value...
Page 149 CHAPTER 3 CPU Table 3.8-1 Functions of low-power consumption mode control register (LPMCR) bit name Function bit0 Reserved: reserved bit Always set this bit to "0". bit1 CG1, CG0: These bits are used to set the halt cycle count of the CPU clock in the CPU intermittent operation bit2 CPU halt cycle count mode.
Page 150 CHAPTER 3 CPU • To access the low-power consumption mode control register (LPMCR) with C language, refer to "I Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby Mode" in the section 3.8.8 "Precautions when Using Low-Power Consumption Mode". •...
Page 151: Cpu Intermittent Operation Mode
CHAPTER 3 CPU 3.8.4 CPU Intermittent operation mode The CPU intermittent operation mode causes the CPU to operate intermittently with an operating clock supplied to the CPU or resources to reduce power consumption. I Operation in CPU Intermittent Operation Mode CPU The CPU intermittent operation mode halts the clock supplied to the CPU at every instruction execution when the CPU accesses registers, internal memory, I/O, or resources delaying to start the internal bus.Decreasing the CPU processing speed while supplying a high-speed clock to resources reduces the...
Page 152: Standby Mode
CHAPTER 3 CPU 3.8.5 Standby Mode The standby mode causes the standby control circuit to either stop supplying an operation clock to the CPU and resources, or to stop the oscillation clock (HCLK) to reduce power consumption. I the operating state in each standby mode Table 3.8-3 shows the operating state in each standby mode.
Page 153 CHAPTER 3 CPU : operation, : stop, : held in the state before transiting, Hi-Z: High impedance *1: The timebase timer and watch timer operate.- *2: The watch timer operates. *3: The DTP/external interrupt input pin operates. *4: Watch timer, timebase timer, and external interrupts *5: Watch timer and external interrupts *6: External interrupt INT6/INT7 MCS: PLL clock select bit in clock select register (CKSCR)
Page 154 CHAPTER 3 CPU 3.8.5.1 Sleep Mode The sleep mode stops the operating clock to the CPU during an operation in each clock mode.The CPU stops and the resources continue to operate. I Transition to Sleep Mode When the mode transits to the sleep mode by setting the low-power consumption mode control register (LPMCR: SLP = 1, STP = 0), the mode transits to the sleep mode according to the settings of the MCS and SCS bits in the clock select register (CKSCR).
Page 155 CHAPTER 3 CPU I Return from Sleep Mode The sleep mode is cancelled by a reset factor or when an interrupt is generated. Return by reset factor When the sleep mode is cancelled by a reset factor, the mode transits to the main clock mode after the sleep mode is cancelled, transiting to the reset sequence.
Page 156 CHAPTER 3 CPU 3.8.5.2 Watch Mode The watch mode operates only the sub clock (SCLK) and the watch timer.-The main clock and PLL clock stop. I Transition to Watch Mode In the sub clock mode, when 0 is written to the TMD bit in the LPMCR register according to the settings of the low-power consumption mode control register (LPMCR), the mode transits to the watch mode.
Page 157 CHAPTER 3 CPU I Return from Watch Mode The watch mode is cancelled by a reset factor or when an interrupt is generated. Return by reset factor When the watch mode is cancelled by a reset factor, the mode transits to the main clock mode after the watch mode is cancelled, transiting to the reset sequence.
Page 158 CHAPTER 3 CPU 3.8.5.3 Timebase Timer Mode The timebase timer mode operates only the oscillation clock (HCLK), sub clock (SCLK), timebase timer, and watch timer. Peripherals other than the timebase timer and watch timer stop. I Timebase Timer Mode The mode transits to the timebase timer mode when 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) during operation in the PLL clock mode or the main clock mode (CKSCR: SCM = 1).
Page 159 CHAPTER 3 CPU I Return from Timebase Timer Mode The timebase timer mode is cancelled by a reset factor or when an interrupt is generated. Return by reset factor When the timebase timer mode is cancelled by a reset factor, the mode transits to the main clock mode after the timebase timer mode is cancelled, transiting to the reset sequence.
Page 160 CHAPTER 3 CPU 3.8.5.4 Stop Mode The stop mode stops the oscillation clock (HCLK) and sub clock (SCLK) during operation in each clock mode.It enables data to be retained with the least power consumption. I Stop Mode When 1 is written to the STP bit of the low-power consumption mode control register (LPMCR) during operation in the PLL clock mode, the mode transits to the stop mode according to the settings of the MCS bit and SCS bit in the clock select register (CKSCR).
Page 161 CHAPTER 3 CPU Note: To set that pin to high impedance which serves either as a peripheral resource or as a port in stop mode, disable the output of the peripheral resource, then set the STP bit of to "1".Listed below are applicable ports.
Page 162 CHAPTER 3 CPU Return by interrupt When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the stop mode, the stop mode is cancelled.In the stop mode, the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled.
Page 163: State Transition In Standby Mode
3.8.6 State Transition in Standby Mode The operating state and state transition in the clock mode and standby mode in MB90895 series are shown in the diagram. I State Transition Diagram Figure 3.8-8 State Transition Diagram External reset, Watchdog timer reset, Software reset...
Page 164: Pin State In Standby Mode, At Reset
CHAPTER 3 CPU 3.8.7 Pin State in Standby Mode, at Reset The state of input/output pins in the standby mode and at reset is shown in each access mode. I State of Input/Output Pins (Single-chip Mode) Table 3.8-6 State of Input/Output Pins (Single-chip Mode) At stop/clock/timebase timer Pin Name At sleep...
Page 165: Precautions When Using Low-Power Consumption Mode
CHAPTER 3 CPU 3.8.8 Precautions when Using Low-power Consumption Mode This section explains the precautions when using the low-power consumption modes. I Transition to Standby Mode When an interrupt request is generated from the resource to the CPU, the mode does not transit to each standby mode even after setting the STP and SLP bits in the low-power consumption mode control register (LPMCR) to 1 and the TMD bit to 0 (and also even after interrupt processing).
Page 166 CHAPTER 3 CPU Oscillation stabilization wait time of sub clock In the sub-stop mode, the oscillation of the sub clock stops and the oscillation stabilization wait time of the sub clock is required.The oscillation stabilization wait time of the sub clock is fixed at 2 /SCLK (SCLK: sub clock).
Page 167 CHAPTER 3 CPU Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby Mode To access the low-power consumption mode control register (LPMCR) with assembler language • To set the low power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 3.8-2.
Page 168 CHAPTER 3 CPU (3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #progrma asm MOVI;_IO_LPMCR,#H’58); /* Set LPMCR SLP bit to 1 */ JMP $+3"...
Page 169: Cpu Mode
For details on the low power consumption modes, see 3.8 "Low-power Consumption Mode". Flash serial programming mode and flash memory mode Some products in MB90895 series have user-programmable flash memory. The flash serial programming mode is that for serially programming data to flash memory.
Page 170: Mode Pins (Md2 To Md0)
CHAPTER 3 CPU 3.9.1 Mode Pins (MD2 to MD0) The mode pins are three external pins of MD2 to MD0, and enable a combination of these pins to set, the following: • Operation modes (RUN mode, flash serial programming mode, flash memory mode) •...
Page 171 CHAPTER 3 CPU Figure 3.9-1 Flow of Mode Pin Setting Setting the pin mode Flash memory programing Flash programing Internal vector mode mode "1" "1" "1" "0" "1" "1" MD2 to MD0: Set to 0=V ss , 1=V cc . And also, do not set to other than above description.
Page 172: Mode Data
CHAPTER 3 CPU 3.9.2 Mode Data Mode data is used to set the memory access mode.It is automatically read to the CPU by mode fetch. I Mode Data The values of the mode register can be changed only in the reset sequence.The changed mode register values are enabled after the reset sequence.
Page 173 CHAPTER 3 CPU I Setting Mode Data Set the mode data as shown in Figure 3.9-3. Figure 3.9-3 Flow of Mode Data Setting Setting of mode data Single chip mode Single chip mode Mode data 00 Do not set mode data other than above value.
Page 174: Memory Access Mode
CHAPTER 3 CPU 3.9.3 Memory Access Mode There are two modes in the memory access mode: bus mode and external access mode. • Bus mode: Sets access area (internal) I Bus Modes Figure 3.9-4 shows the memory map in the mode. Figure 3.9-4 Memory map in the mode When ROM mirror is enabled 000000...
Page 175: Operations For Selecting Memory Access Mode
CHAPTER 3 CPU 3.9.4 Operations for Selecting Memory Access Mode This section explains selection of the memory access mode in the reset sequence. I Operations for Selecting Memory Access Mode After reset is cancelled, the CPU selects the memory access mode according to the procedure shown in Figure 3.9-5 by referencing the settings of the mode pins and mode data.
Page 176 CHAPTER 3 CPU...
Page 177: Chapter 4 I/O Port
CHAPTER 4 I/O PORT This chapter describes the function and operation of the I/O port. 4.1 Overview of I/O Ports 4.2 Registers of I/O Port and Assignment of Pins Serving as External 4.3 Port 1 4.4 Port2 4.5 Port 3 4.6 Port 4 4.7 Port 5 4.8 Port input level select register...
Page 178: Overview Of I/O Ports
CHAPTER 4 I/O PORT Overview of I/O Ports I/O ports can be used as general-purpose I/O ports (parallel I/O ports). In MB90895 series, there are five ports (34 pins). Each port pin also serves as a peripheral I/O pins. I I/O Port Function The I/O ports enable the port data register (PDR) to output data to the I/O pins from the CPU and fetch signals input to the I/O pins.These also enable the port direction register (DDR) to set a direction for the I/ O pins by bit.
Page 179: Registers Of I/O Port And Assignment Of Pins Serving As External Bus
CHAPTER 4 I/O PORT Registers of I/O Port and Assignment of Pins Serving as External Bus The registers related to I/O port setting are listed as follows. I Registers of I/O Ports Table 4.2-1 shows the register list of each port. Table 4.2-1 Registers of Each Port Register Name Read/Write...
Page 180: Port 1
CHAPTER 4 I/O PORT Port 1 Port 1 is a general-purpose I/O port that also serves as a peripheral resource I/O pin. When the single-chip mode is set, use port 1 by switching between the resource pin and the general-purpose I/O port. The configuration, pin assignment, block diagram of the pins, and registers for port 1 are shown below.
Page 181 CHAPTER 4 I/O PORT I Block Diagram of Port-1 Pins (in Single Chip Mode) Figure 4.3-1 Block Diagram of Pins of Port 1 Resource output Resource input Port data register (PDR) Resource output acceptance PDR read Output latch PDR write Port direction register (DDR) Direction latch DDR write...
Page 182: Registers For Port 1 (Pdr1, Ddr1)
CHAPTER 4 I/O PORT 4.3.1 Registers for Port 1 (PDR1, DDR1) The registers for port 1 are explained. I Function of Registers for Port 1 (in Single Chip Mode) Port 1 data register (PDR1) • Port 1 data register indicates the state of the pins. Port 1 direction register (DDR1) •...
Page 183: Operation Of Port 1
CHAPTER 4 I/O PORT 4.3.2 Operation of Port 1 The operation of port 1 is explained. I Operation of Port 1 (in Single Chip Mode) Operation of output port • When the bit in the port 1 direction register (DDR1) corresponding to the output pin is set to "1", port 0 functions as an output port.
Page 184 CHAPTER 4 I/O PORT Operation in stop mode, timebase timer mode or watch mode • When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the high- impedance state.
Page 185: Port2
CHAPTER 4 I/O PORT Port2 Port 2 is a general-purpose I/O port that also serves as a peripheral resource I/O pin. Use port 2 by switching between the resource pin and the general-purpose I/O port. The configuration, pin assignment, block diagram of the pins, and registers for port 2 are shown below.
Page 186 CHAPTER 4 I/O PORT Table 4.4-1 shows pin assignment of port 2. Table 4.4-1 Pin Assignment of Port 2 I/O Type Circu Port Port Function Resource Name Name Outpu Input Type P20/ 16-bit reload TIN0 TIN0 timer 0 input 16-pit reload P21/ TOT0 timer 0...
Page 187 CHAPTER 4 I/O PORT I Block Diagram of Pins of Port 2 (General-purpose I/O Port) Figure 4.4-1 Block Diagram of Pins of Port 2 Resource output Resource input Port data register (PDR) Resource output acceptance PDR read Output latch PDR write Port direction register (DDR) Direction latch DDR write...
Page 188: Registers For Port 2 (Pdr2, Ddr2)
CHAPTER 4 I/O PORT 4.4.1 Registers for Port 2 (PDR2, DDR2) The registers for port 2 are explained. I Function of Registers for Port 2 Port 2 data register (PDR2) Port 2 data register indicates the input/output state of the pins. Port 2 direction register (DDR2) •...
Page 189: Operation Of Port 2
CHAPTER 4 I/O PORT 4.4.2 Operation of Port 2 The operation of port 2 is explained. I Operation of Port 2 (General-purpose I/O Port) Operation of output port • When the bit in the port 2 direction register (DDR2) corresponding to the output pin is set to "1", port 2 functions as an output port.
Page 190 CHAPTER 4 I/O PORT Operation at reset • When the CPU is reset, the value of the DDR2 is initialized to "0".Consequently, all output buffers are set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state. •...
Page 191: Port 3
CHAPTER 4 I/O PORT Port 3 Port 3 is a general-purpose I/O port that serves as the resource I/O pin. Use port 3 by switching between the resource pin and the general-purpose I/O port. The configuration, pin assignment, block diagram of the pins, and registers for port 3 are shown below.
Page 192 CHAPTER 4 I/O PORT I Block Diagram of Pins of Port 3 (General-purpose I/O Port) Figure 4.5-1 Block Diagram of Pins of Port 3 Resource output Resource input Port data register (PDR) Resource output acceptance PDR read Output latch PDR write Port direction register (DDR) Direction latch DDR write...
Page 193: Registers For Port 3 (Pdr3, Ddr3)
CHAPTER 4 I/O PORT 4.5.1 Registers for Port 3 (PDR3, DDR3) The registers for port 3 are explained. I Function of Registers for Port 3 Port 3 data register (PDR3) • Port 3 data register indicates the state of the pins. Port 3 direction register (DDR3) •...
Page 194: Operation Of Port 3
CHAPTER 4 I/O PORT 4.5.2 Operation of Port 3 The operation of port 3 is explained. I Operation of Port 3 (General-purpose I/O Port) Operation of output port • When the bit in the port 3 direction register (DDR3) corresponding to the output pin is set to "1", port 3 functions as an output port.
Page 195 CHAPTER 4 I/O PORT Table 4.5-4 shows the state of the port 3 pins. Table 4.5-4 The state of the port 3 pins Stop Mode, Timebase Timer Mode or Watch Mode Normal Pin Name Sleep mode Operation SPL=0 SPL=1 P30 to P33, General- General- General-purpose I/O...
Page 196: Port 4
CHAPTER 4 I/O PORT Port 4 Port 4 is a general-purpose I/O port that also serves as a peripheral resource I/O pin. Use port 4 by switching between the resource pin and the general-purpose I/O port. The configuration, pin assignment, block diagram of the pins, and registers for port 4 are shown below.
Page 197 CHAPTER 4 I/O PORT I Block Diagram of Pins of Port 4 Figure 4.6-1 Block Diagram of Pins of Port 4 Resource input Resource output Port data register (PDR) Resource output acceptance PDR read Output latch PDR write Port direction register (DDR) Direction latch DDR write Standby control (SPL=1)
Page 198: Registers For Port 4 (Pdr4, Ddr4)
CHAPTER 4 I/O PORT 4.6.1 Registers for Port 4 (PDR4, DDR4) The registers for port 4 are explained. I Function of Registers for Port 4 Port 4 data register (PDR4) • Port 4 data register indicates the state of the pins. Port 4 direction register (DDR4) •...
Page 199: Operation Of Port 4
CHAPTER 4 I/O PORT 4.6.2 Operation of Port 4 The operation of port 4 is explained. I Operation of Port 4 Operation of output port • When the bit in the port 4 direction register (DDR4) corresponding to the output pin is set to "1", port 4 functions as an output port.
Page 200 CHAPTER 4 I/O PORT output. Operation in stop mode, timebase timer mode or watch mode If the pin state specify bit (SPL) of the low-power consumption mode control register (LPMCR) is set to "1" when the CPU operation mode switches to stop mode, timebase timer mode or watch mode, the pin enters the high-impedance state.In this case, the output buffer is forcibly set to off regardless of the values of the Port 4 direction register (DDR4).
Page 201: Port 5
CHAPTER 4 I/O PORT Port 5 Port 5 is a general-purpose I/O port that also serves as an analog input pin. Use port 5 by switching between the analog input pin and the general-purpose I/O port. The configuration, pin assignment, block diagram of the pins, and registers for port 5 are shown below.
Page 202 CHAPTER 4 I/O PORT Table 4.7-1 shows pins assignment of port 5. Table 4.7-1 Pins Assignment of Port 5 I/O Type Circu Port Name Port Function Resource Name Type Input Output Analog input P50/AN0 channel 0 Analog input P51/AN1 channel 1 Analog input P52/AN2 channel 2...
Page 203 CHAPTER 4 I/O PORT I Block Diagram of Pins of Port 5 Figure 4.7-1 Block Diagram of Pins of Port 5 Analog input ADER PDR (Port data register) PDR read Output latch PDR write DDR (Port direction register) Direction latch DDR write Standby control (SPL=1) DDR read...
Page 204: Registers For Port 5 (Pdr5, Ddr5, Ader)
CHAPTER 4 I/O PORT 4.7.1 Registers for Port 5 (PDR5, DDR5, ADER) The registers for port 5 are explained. I Function of Registers for Port 5 Port 5 data register (PDR5) • Port 5 data register indicates the state of the pins. Port 5 direction register (DDR5) •...
Page 205 CHAPTER 4 I/O PORT Table 4.7-3 Functions of the Registers for Port 5 Register Read/ Register Data At Read At Write Reset Value Name Write Address "0" is set for the output The pin state is latch, and when the pin is Low level.
Page 206: Operation Of Port 5
CHAPTER 4 I/O PORT 4.7.2 Operation of Port 5 The operation of port 5 is explained. I Operation of Port 5 Operation of output port • When the bit in the port 5 direction register (DDR5) corresponding to the output pin is set to 1, port 5 functions as an output port.
Page 207 CHAPTER 4 I/O PORT Operation at reset • When the CPU is reset, the value of the DDR5 is initialized to "0".Consequently, all output buffers are set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state. •...
Page 208: Port Input Level Select Register
CHAPTER 4 I/O PORT Port input level select register The port input level select register is used to set the input signal to CMOS hysteresis input, Automotive input, or to CMOS input. I Port input level select register (PILR) PILR:00A2 ILS1 ILS0 Read/Write...
Page 209: Chapter 5 Timebase Timer
CHAPTER 5 Timebase timer This chapter describes the function and operation of the timebase timer. 5.1 Overview of Timebase Timer 5.2 Block Diagram of Timebase Timer 5.3 Configuration of Timebase Timer 5.4 Interrupt of Timebase Timer 5.5 Explanation of Operations of Timebase Timer Functions 5.6 Precautions when Using Timebase Timer 5.7 Program Example of Timebase Timer...
Page 210: Overview Of Timebase Timer
CHAPTER 5 Timebase timer Overview of Timebase Timer The timebase timer is an 18-bit free-run counter (timebase timer counter) that increments in synchronization with the main clock (half frequency of main oscillation clock). • Four interval times can be selected and an interrupt request can be generated for each interval time.
Page 211 CHAPTER 5 Timebase timer I Clock Supply • The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait time timer, PPG timer, and watchdog timer. Table 5.1-2 shows the clock cycles supplied from the timebase timer.
Page 212: Block Diagram Of Timebase Timer
CHAPTER 5 Timebase timer Block Diagram of Timebase Timer The timebase timer consists of the following blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) I Block Diagram of Timebase Timer Figure 5.2-1 Block Diagram of Timebase Timer To watchdog To PPG timer...
Page 213 CHAPTER 5 Timebase timer Timebase timer counter The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation clock (HCLK) as a count clock. Counter clear circuit The counter clear circuit clears the value of the timebase timer counter by the following factors: •...
Page 214: Configuration Of Timebase Timer
CHAPTER 5 Timebase timer Configuration of Timebase Timer This section explains the registers and interrupt factors of the timebase timer. I List of Registers and Reset Values of Timebase Timer Figure 5.3-1 List of Registers and Reset Values of Timebase Timer Timebase timer control register ×...
Page 215: Timebase Timer Control Register (Tbtc)
CHAPTER 5 Timebase timer 5.3.1 Timebase timer control register (TBTC) The timebase timer control register (TBTC) provides the following settings: • Selecting the interval time of the timebase timer • Clearing the count value of the timebase timer • Enabling or disabling the interrupt request when an overflow occurs •...
Page 216 CHAPTER 5 Timebase timer Table 5.3-1 Functions of Timebase Timer Control Register (TBTC) bit name Function bit8 TBC1, TBC0: These bits set the cycle of the interval timer in the timebase bit9 Interval time select bits timer counter. • The interval time of the timebase timer is set according to the setting of the TBC1 and TBC0 bits.
Page 217: Interrupt Of Timebase Timer
CHAPTER 5 Timebase timer Interrupt of Timebase Timer The timebase timer generates an interrupt request (interval timer function) when the interval time bit in the timebase timer counter corresponding to the interval time set by the timebase timer control register carries (overflows). I Interrupt of Timebase Timer •...
Page 218: Explanation Of Operations Of Timebase Timer Functions
CHAPTER 5 Timebase timer Explanation of Operations of Timebase Timer Functions The timebase timer operates as an interval timer or an oscillation stabilization wait time timer. It also supplies a clock to peripherals. I Interval Timer Function Interrupt generation at every interval time enables the timebase timer to be used as an interval timer. Operating the timebase timer as an interval timer requires the settings shown in Figure 5.5-1.
Page 219 CHAPTER 5 Timebase timer Example of operation of timebase timer Figure 5.5-2 gives an example of the operation that the timebase timer performs under the following conditions: • A power-on reset occurs. • The mode transits to the sleep mode during the operation of the interval timer. •...
Page 220 CHAPTER 5 Timebase timer I Operation as Oscillation Stabilization Wait Time Timer The timebase timer can be used as the oscillation stabilization wait timer for the main clock and PLL clock. • The oscillation stabilization wait time is the time elapsed from when the timebase timer counter increments from "0"...
Page 221 CHAPTER 5 Timebase timer Table 5.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer (2/2) Counter TBOF Oscillation Stabilization Wait Operation Clear Clear Time Cancellation of PLL stop mode Transition to PLL clock mode after oscillation stabilization wait time of main clock completed Cancellation of timer mode ×...
Page 222: Precautions When Using Timebase Timer
CHAPTER 5 Timebase timer Precautions when Using Timebase Timer Precautions when using the timebase timer are shown below. I Precautions when Using Timebase Timer Clearing interrupt request To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF = 0), disable interrupts (TBTC: TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask register in the processor status.
Page 223: Program Example Of Timebase Timer
CHAPTER 5 Timebase timer Program Example of Timebase Timer Programming examples for the timebase timer are shown below. Program Example of Timebase Timer Processing specification The 2 /HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly.In this case, the interval time is approximately 1.0 ms (at 4-MHz operation).
Page 224 CHAPTER 5 Timebase timer...
Page 225: Chapter 6 Watchdog Timer
CHAPTER 6 Watchdog timer This chapter describes the function and operation of the watchdog timer. 6.1 Overview of Watchdog Timer 6.2 Configuration of Watchdog Timer 6.3 Watchdog Timer Registers 6.4 Explanation of Operations of Watchdog Timer Functions 6.5 Precautions when Using Watchdog Timer 6.6 Program Examples of Watchdog Timer...
Page 226: Overview Of Watchdog Timer
CHAPTER 6 Watchdog timer Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a count clock.If the counter is not cleared within a set interval time, the CPU is reset. I Functions of Watchdog Timer •...
Page 227: Configuration Of Watchdog Timer
CHAPTER 6 Watchdog timer Configuration of Watchdog Timer The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer counter (2-bit counter) • Watchdog reset generator • Counter clear control circuit • Watchdog timer control register (WDTC) I Block Diagram of Watchdog Timer Figure 6.2-1 Block Diagram of Watchdog Timer Watchdog timer control register (WDTC)
Page 228 CHAPTER 6 Watchdog timer Count clock selector The count clock selector selects the timebase timer output or watch timer output as a count clock input to the watchdog timer.Each timer output has four time intervals that can be set. Watchdog timer counter (2-bit counter) The watchdog timer counter is a 2-bit counter that uses the timebase timer output or watch timer output as a count clock.The clock source output destination is set by the watchdog clock select bit in the watch timer control register (WTC: WDCS).
Page 229: Watchdog Timer Registers
CHAPTER 6 Watchdog timer Watchdog Timer Registers This section explains the registers used for setting the watchdog timer. I List of Registers and Reset Values of Watchdog Timer Figure 6.3-1 List of Registers and Reset Values of Watchdog Timer Watchdog timer control register (WDTC) Undefined...
Page 230: Watchdog Timer Control Register (Wdtc)
CHAPTER 6 Watchdog timer 6.3.1 Watchdog timer control register (WDTC) The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds reset factors. I Watchdog timer control register (WDTC) Figure 6.3-2 Watchdog timer control register (WDTC) Reset value XXXXX111 bit1...
Page 231 CHAPTER 6 Watchdog timer Table 6.3-1 Functions of the Watching Timer Control Register (WDTC) bit name Function bit0 WT1, WT0: These bits set the interval time of the watchdog timer. bit1 Interval time select bits 'The time interval when the watch timer is used as the clock source to the watchdog timer (watchdog clock select bit WDCS = 0) is different from when the main clock mode or the PLL clock mode is selected as the clock mode and the WDCS bit in...
Page 232: Explanation Of Operations Of Watchdog Timer Functions
CHAPTER 6 Watchdog timer Explanation of Operations of Watchdog Timer Functions After starting, when the watchdog timer reaches the set interval time without the counter being cleared, a watchdog reset occurs. I Operations of Watchdog Timer The operation of the watchdog timer requires the settings shown in Figure 6.4-1. Figure 6.4-1 Setting of Watchdog Time bit7 bit0...
Page 233 CHAPTER 6 Watchdog timer Clearing watchdog timer • When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not cleared within the interval time, it overflows and the CPU is reset.
Page 234 CHAPTER 6 Watchdog timer Checking reset factors • The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be read after a reset to check the reset factors. Note: For details on the reset source bit, see Section 3.6 Reset. Figure 6.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer [Watchdog timer block diagram] 2-bit counter...
Page 235: Precautions When Using Watchdog Timer
CHAPTER 6 Watchdog timer Precautions when Using Watchdog Timer Take the following precautions when using the watchdog timer. I Precautions when Using Watchdog Timer Stopping watchdog timer • The watchdog timer is stopped by all the reset sources. Interval time •...
Page 236: Program Examples Of Watchdog Timer
CHAPTER 6 Watchdog timer Program Examples of Watchdog Timer Program example of watchdog timer is given below: I Program Examples of Watchdog Timer Processing specification • The watchdog timer is cleared each time in the loop of the main program. •...
Page 237: 16-Bit I/O Timer
CHAPTER 7 16-bit I/O timer This chapter explains the function and operation of the 16- bit input/output timer. 7.1 Overview of 16-bit Input/Output Timer 7.2 Block Diagram of 16-bit Input/Output Timer 7.3 Configuration of 16-bit Input/Output Timer 7.4 Interrupts of 16-bit Input/Output Timer 7.5 Explanation of Operation of 16-bit Free-run Timer 7.6 Explanation of Operation of Input Capture 7.7 Precautions when Using 16-bit Input/Output Timer...
Page 238: Overview Of 16-Bit Input/Output Timer
CHAPTER 7 16-bit I/O timer Overview of 16-bit Input/Output Timer The 16-bit input/output timer is a combined module that consists of a 16-bit free-run timer (x 1 unit) and an input capture (x 2 units/4 input pins).The clock cycle of an input signal and a pulse width can be measured based on the 16-bit input/output timer.
Page 239: Block Diagram Of 16-Bit Input/Output Timer
CHAPTER 7 16-bit I/O timer Block Diagram of 16-bit Input/Output Timer The 16-bit input/output timer consists of the following modules: • 16-bit free-run timer • Input capture I Block Diagram of 16-bit Input/Output Timer Figure 7.2-1 Block Diagram of 16-bit Input/Output Timer Internal data bus 16-bit Input...
Page 240: Block Diagram Of 16-Bit Free-Run Timer
CHAPTER 7 16-bit I/O timer 7.2.1 Block Diagram of 16-bit Free-run Timer The 16-bit free-run timer consists of the following blocks: • Prescaler • Timer counter data register (TCDT) • Timer counter control status register (TCCS) I Block Diagram of 16-bit Free-run Timer Figure 7.2-2 Block Diagram of 16-bit Free-run Timer Output count value Timer counter data register...
Page 241 CHAPTER 7 16-bit I/O timer Timer counter control status register (TCCS) The timer counter control status register (TCCS) selects the division ratio of the machine clock, clears the count value by software, enables or disables the count operation, checks and clears the overflow generation flag, and enables or disables interrupt.
Page 242: Block Diagram Of Input Capture
CHAPTER 7 16-bit I/O timer 7.2.2 Block Diagram of Input Capture The input capture consist of the following blocks: • Input capture data registers (IPCP0 to IPCP3) • Input capture control status registers (ICS01, ICS23) • Edge detection circuit I Block Diagram of Input Capture Figure 7.2-3 Block Diagram of Input Capture 16-bit free-run timer Edge detection circuit...
Page 243 CHAPTER 7 16-bit I/O timer I Details of Pins in Block Diagram The 16-bit input/output timer has four input capture input pins. The actual pin names and interrupt request numbers used in the input capture unit are shown in Table 7.2-1. Table 7.2-1 Pins and Interrupt Request Numbers of 16-bit Input/Output Timer Input Pin Actual Pin Name...
Page 244: Configuration Of 16-Bit Input/Output Timer
CHAPTER 7 16-bit I/O timer Configuration of 16-bit Input/Output Timer This section explains the pins, registers, and interrupt factors of the 16-bit input/output timer. I Pins of 16-bit Input/Output Timer The pins of the 16-bit input/output timer serve as general-purpose I/O ports. Table 7.3-1 shows the pin functions and the pin settings required to use the 16-bit input/output timer.
Page 245 CHAPTER 7 16-bit I/O timer I List of Registers and Reset Values of 16-bit Input/Output Timer Figure 7.3-1 List of Registers and Reset Values of 16-bit Input/Output Timer Timer counter control status register (TCCS) Timer counter data register upper (TCDT: H) Timer counter data register lower (TCDT: L) Input capture control status...
Page 246 CHAPTER 7 16-bit I/O timer I Generation of Interrupt Request from 16-bit Input/Output Timer The 16-bit input/output timer can generate an interrupt request as a result of the following factors: Overflow in 16-bit free-run timer In the 16-bit input/output timer, when the 16-bit free-run timer overflows, the overflow generation flag bit in the timer counter control status register (TCCS: IVF) is set to "1".When an overflow interrupt is enabled (TCCS: IVFE = 1), an interrupt request is generated.
Page 247: Timer Counter Control Status Register (Tccs)
CHAPTER 7 16-bit I/O timer 7.3.1 Timer counter control status register (TCCS) The timer counter control status register (TCCS) selects the count clock and conditions for clearing the counter, clears the counter, enables or disables the count operation or interrupt, and checks the interrupt request flag. I Timer counter control status register (TCCS) Figure 7.3-2 Timer counter control status register (TCCS) Reset value...
Page 248 CHAPTER 7 16-bit I/O timer Table 7.3-2 Functions of Timer Counter Control Status Register (TCCS) bit name Function] bit0 CLK2, CLK1, CLK0: These bits set the count clock to the 16-bit free-run time. bit1 Count clock selection Note: bit2 bits 1)Set the count clock after stopping the count operation (STOP = 1).
Page 249: Timer Counter Data Register (Tcdt)
CHAPTER 7 16-bit I/O timer 7.3.2 Timer counter data register (TCDT) The timer counter data register (TCDT) is a 16-bit up counter.At read the register value being counted is read.At write while the counter is stopped, any count value can be set. I Timer counter data register (TCDT) Figure 7.3-3 Timer counter data register (TCDT) bit15 bit14 bit13 bit12 bit11 bit10 bit9...
Page 250 CHAPTER 7 16-bit I/O timer Factors clearing timer counter data register (TCDT) The timer counter data register (TCDT) is cleared to 0000 H by the following factors: Of the following events, the overflow clears the register in synchronization with the count clock and each of the other events clears the register on occurrence of that event.
Page 251: Input Capture Control Status Registers (Ics01, Ics23)
CHAPTER 7 16-bit I/O timer 7.3.3 Input capture control status registers (ICS01, ICS23) The input capture control status registers sets the operation of input captures.The ICS01 register sets the operation of input captures 0 and 1 and the ICS23 sets the operation of input captures 2 and 3.The input capture control status registers provides the following settings: •...
Page 252 CHAPTER 7 16-bit I/O timer Table 7.3-3 Functions of Input Capture Control Status Register (ICS01) bit name Function bit0 EG01, EG00: These bits enable or disable the operation of input capture 0.The bit1 Input capture 0 edge edge detected by input capture 0 is selected when the operation select bits of input capture 0 is enabled.
Page 253: Input Capture Data Registers (Ipcp0 To Ipcp3)
CHAPTER 7 16-bit I/O timer 7.3.4 Input capture data registers (IPCP0 to IPCP3) The input capture data registers 0 to 3 (IPCP0 to IPCP3) store the counter value of the 16-bit free-run timer read in the timing with the edge detection by the input capture.The counter value of the 16-bit free-run timer is stored in the input capture data registers (IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3) to which an external signal is input.
Page 254: Interrupts Of 16-Bit Input/Output Timer
CHAPTER 7 16-bit I/O timer Interrupts of 16-bit Input/Output Timer The interrupt factors of the 16-bit input/output timer include an overflow in the 16-bit free-run timer and edge detection by the input capture.Interrupt generation starts EI I Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer Table 7.4-1 shows interrupt control bits and interrupt factors of 16-bit input/output timer.
Page 255: Explanation Of Operation Of 16-Bit Free-Run Timer
CHAPTER 7 16-bit I/O timer Explanation of Operation of 16-bit Free-run Timer After a reset, the 16-bit free-run timer starts incrementing from "0000 ".When the counter value is incremented from "FFFF " to "0000 ", an overflow occurs. I Setting of 16-bit Free-run Timer Operation of the 16-bit free-run timer requires the setting shown in Figure 7.5-1 Figure 7.5-1 Setting of 16-bit Free-run Timer bit15 14...
Page 256 CHAPTER 7 16-bit I/O timer I Operation Timing of 16-bit Free-run Timer Figure 7.5-2 shows counter clearing at an overflow. Figure 7.5-2 Counter Clearing at an Overflow Counter value Over flow F F F F BFFF 7 F F F 3 F F F 0 0 0 0 Time...
Page 257: Explanation Of Operation Of Input Capture
CHAPTER 7 16-bit I/O timer Explanation of Operation of Input Capture When the input capture detects the edge of the external signal input to the input pins, it stores the count value of the 16-bit free-run timer in the input capture data registers. I Setting of Input Capture Operation of the input capture requires the setting shown in Figure 7.6-1 Figure 7.6-1 Setting of Input Capture...
Page 258 CHAPTER 7 16-bit I/O timer I Operation of Input Capture • When the valid edges of the external signals input to the input pins (IN0 to IN3) are detected, the input capture valid edge detection flag bit (ICS: ICP) corresponding to the input pin is set to 1.At the same time, the count value of the 16-bit free-run timer is stored in the input capture data registers (IPCP) corresponding to the input pins (IN0 to IN3).
Page 259 CHAPTER 7 16-bit I/O timer I Operation Timing of Input Capture Figure 7.6-2 shows the timing of reading the counter value of the 16-bit free-run timer. Figure 7.6-2 Timing of Reading Counter Value of Input Capture φ Counter value Input capture input Available edge Capture signal...
Page 260: Precautions When Using 16-Bit Input/Output Timer
CHAPTER 7 16-bit I/O timer Precautions when Using 16-bit Input/Output Timer This section explains the precautions when using the 16-bit input/output timer. I Precautions when Using 16-bit Input/Output Timer Precautions when setting 16-bit free-run timer • Do not change the count clock select bits (TCCS: CLK2, CLK1, CLK0) during the count operation (TCCS: STOP = 0).
Page 261: Program Example Of 16-Bit Input/Output Timer
CHAPTER 7 16-bit I/O timer Program Example of 16-bit Input/Output Timer This section gives a program example of the 16-bit input/output timer. I Processing of Program for Measuring Cycle Using Input Capture • The cycle of a signal input to the IN0 pin is measured. •...
Page 262 CHAPTER 7 16-bit I/O timer CCR,#0BFH ;Interrupt disable I:ICR04,#00H ;Interrupt level 0 (strongest) I:ICR06,#00H ;Interrupt level 0 (strongest) I:DDR1,#00000000B ;Setting pin to input I:TCCS,#00110100B ;Count enable,counter clear, ;Over flow,interrupt enable, φ ;Count clock /4 selection I:ICS01,#00010001B ;IN0 pin selection, ;IPCP0 rising edge ;Without IPCP1 edge detection, ;Clear each interrupt request flag ;Input capture interrupt request enable...
Page 263: 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer This chapter explains the functions and the operations of 16-bit reload timer. 8.1 Overview of 16-bit Reload Timer 8.2 Block Diagram of 16-bit Reload Timer 8.3 Configuration of 16-bit Reload Timer 8.4 Interrupts of 16-bit Reload Timer 8.5 Explanation of Operation of 16-bit Reload Timer 8.6 Precautions when Using 16-bit Reload Timer 8.7 Program Example of 16-bit Reload Timer...
Page 264: Overview Of 16-Bit Reload Timer
(TMRLR) to the TMR to continue the TMR count operation can be selected. • The hardware interrupt corresponds to the EI • MB90895 series has two channels of 16-bit reload timers. I Operation Modes of 16-bit Reload Timer Table 8.1-1 indicates the operation modes of the 16-bit reload timer.
Page 265 CHAPTER 8 16-bit reload timer I Event count mode • When the count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) are set to "11 ", the 16-bit reload timer is set to the event count mode. •...
Page 266 CHAPTER 8 16-bit reload timer I Operation at Underflow When the start trigger is input, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register, starting decrementing in synchronization with the count clock.When the 16-bit timer register (TMR) is decremented from "0000 "...
Page 267: Block Diagram Of 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer Block Diagram of 16-bit Reload Timer The 16-bit reload timers 0 and 1 composed of the following seven blocks: • Count clock generator • Reload controller • Output controller • Operation controller • 16-bit timer register (TMR) •...
Page 268 CHAPTER 8 16-bit reload timer Details of Pins in Block Diagram There are two channels for 16-bit reload timer. The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows: 16-bit reload timer 0: TIN pin: P20/TIN0 TOT pin: P21/TOT0 Interrupt request number: #17 (11...
Page 269 CHAPTER 8 16-bit reload timer Timer control status register (TMCSR) The timer control status register (TMCSR) selects the operation mode, sets the operation conditions, selects the start trigger, performs a start using the software trigger, selects the reload operation mode, enables or disables an interrupt request, sets TOT pin output level, and sets TOT output pin.
Page 270: Configuration Of 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer Configuration of 16-bit Reload Timer This section explains the pins, registers, and interrupt factors of the 16-bit reload timer. I Pins of 16-bit Reload Timer The pins of the 16-bit reload timer serve as general-purpose I/O ports.Table 8.3-1 shows the pin functions and the pin settings required to use the 16-bit reload timer.
Page 271 CHAPTER 8 16-bit reload timer I List of Registers and Reset Values of 16-bit Reload Timer Registers of 16-bit reload timer 0 Figure 8.3-1 List of Registers and Reset Values of 16-bit Reload Timer 0 Timer control status register upper (TMCSR0) Timer control status register lower (TMCSR0) 16-bit timer register upper...
Page 272 CHAPTER 8 16-bit reload timer I Generation of Interrupt Request from 16-bit Reload Timer When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from "0000 " to "FFFF ", an underflow occurs.When an underflow occurs, the UF bit in the timer control status register is set to "1"...
Page 273: Timer Control Status Registers (High) (Tmcsr0: H, Tmcsr1: H)
CHAPTER 8 16-bit reload timer 8.3.1 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H) The timer control status registers (High) (TMCSR0: H, TMCSR1: H) set the operation mode and count clock. This section also explains the bit 7 in the timer control status registers (Low) (TMCSR0: L, TMCSR1: L).
Page 274 CHAPTER 8 16-bit reload timer Table 8.3-2 Functions of Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H) bit name Function bit7 MOD2, MOD1, MOD0: These bits set the operation conditions of the 16-bit reload timer. Operation mode select (Internal clock mode) bit9 bits The MOD2 bit is used to select the function of the input pin.
Page 275: Timer Control Status Registers (High) (Tmcsr0: H, Tmcsr1: H)
CHAPTER 8 16-bit reload timer 8.3.2 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L) The timer control status registers (Low) (TMCSR0: L, TMCSR1: L) enables or disables the timer operation, checks the generation of a software trigger or an underflow, enables or disables an underflow interrupt, selects the reload mode, and sets the output of the TOT pin.
Page 276 CHAPTER 8 16-bit reload timer Table 8.3-3 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L) bit name Function bit0 TRG: This bit starts the 16-bit reload timer by software. Software trigger bit The software trigger function works only when the timer operation is enabled (CNTE = 1).
Page 277: 16-Bit Timer Registers (Tmr0, Tmr1)
CHAPTER 8 16-bit reload timer 8.3.3 16-bit Timer Registers (TMR0, TMR1) The 16-bit timer registers (TMR0, TMR1) are 16-bit down counters.At read, the value being counted is read. I 16-bit Timer Registers (TMR0, TMR1) Figure 8.3-5 16-bit Timer Registers (TMR0, TMR1) Reset value TMR0 XXXXXXXX...
Page 278: 16-Bit Reload Registers (Tmrlr0, Tmrlr1)
CHAPTER 8 16-bit reload timer 8.3.4 16-bit Reload Registers (TMRLR0, TMRLR1) The 16-bit reload registers (TMRLR0, TMRLR1) set the value to be reloaded to the 16-bit timer register (TMR).When the start trigger is input, the value set in the 16-bit reload registers (TMRLR0, TMRLR1) is reloaded to the TMR, starting the TMR count operation.
Page 279: Interrupts Of 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer Interrupts of 16-bit Reload Timer The 16-bit reload timer generates an interrupt request when the 16-bit timer register (TMR) underflows. I Interrupts of 16-bit Reload Timer When the value of the TMR is decremented from "0000 "...
Page 280: Explanation Of Operation Of 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer Explanation of Operation of 16-bit Reload Timer This section explains the setting of the 16-bit reload timer and the operation state of the counter. I Setting of 16-bit Reload Timer Setting of internal clock mode Counting the internal clock requires the setting shown in Figure 8.5-1.
Page 281 CHAPTER 8 16-bit reload timer I Operating State of 16-bit Timer Register The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer control status register (TMCSR: CNTE) and the WAIT signal.The operating states include the stop state, start trigger input wait state (WAIT state), and RUN state.
Page 282: Operation In Internal Clock Mode
CHAPTER 8 16-bit reload timer 8.5.1 Operation in Internal Clock Mode In the internal clock mode, three operation modes can be selected by setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to MOD0).When the operation mode and reload mode are set, a rectangular wave or a toggle wave is output from the TOT pin.
Page 283 CHAPTER 8 16-bit reload timer I Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000 " to "FFFF " during the TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generation flag bit in the timer control status register (TMCSR: UF) is set to 1.
Page 284 CHAPTER 8 16-bit reload timer Figure 8.5-4 Count Operation in Software Trigger Mode (One-shot Mode) Count clock Reload Reload 0000 FFFF 0000 FFFF Counter data data Data load signal UF bit CNTE bit TRG bit TOT pin Activating trigger input waite T : Machine cycle : It takes 1T time from trigger input to loading data of reload register.
Page 285 CHAPTER 8 16-bit reload timer [External trigger mode (MOD2 to MOD0 = "001 ", "010 ", "011 ")] When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge to the TIN pin.When the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR, starting the TMR count operation.
Page 286 CHAPTER 8 16-bit reload timer [External gate input mode (MOD2 to MOD0 = "1x0 ", "1x1 ")] When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in the timer control status register (TMCSR: TRG) to "1".When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR).
Page 287: Operation In Event Count Mode
CHAPTER 8 16-bit reload timer 8.5.2 Operation in Event Count Mode In the event count mode, after the 16-bit reload timer is started, the edge of the signal input to the TIN pin is detected to perform the count operation of the 16-bit timer register (TMR).When the operation mode and reload mode are set, a rectangular wave or a toggle wave is output from the TOT pin.
Page 288 CHAPTER 8 16-bit reload timer I Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000 " to "FFFF " during the TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generation flag bit in the timer control status register (TMCSR: UF) is set to "1".
Page 289 CHAPTER 8 16-bit reload timer I Operation in Event Count Mode The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer control status register (TMCSR: CNTE) to "1".When the software trigger bit in the timer control status register (TMCSR: TRG) is set to 1, the 16-bit reload timer is started.When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count operation.After the 16-bit reload timer is started, the edge of the external event clock input...
Page 290: Precautions When Using 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer Precautions when Using 16-bit Reload Timer This section explains the precautions when using the 16-bit reload timer. I Precautions when Using 16-bit Reload Timer Precautions when using programs to set timebase timer • Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR: CNTE = 0) •...
Page 291: Program Example Of 16-Bit Reload Timer
CHAPTER 8 16-bit reload timer Program Example of 16-bit Reload Timer This section gives a program example of the 16-bit reload timer operated in the internal clock mode and the event count mode are given below: I Program Example in Internal Clock Mode Processing specification •...
Page 292 CHAPTER 8 16-bit reload timer ;---------Interrupt program--------------------------------- WARI: I:UF0 ;Clear interrupt request flag User processing RETI ;Recovery from interrupt CODE ENDS ;---------Vector setting------------------------------------ VECT CSEG ABS=0FFH 00FFB8H ;Setting vector to interrupt #17 WARI 00FFDCH ;Reset vector setting START ;Setting to single chip mode VECT ENDS START...
Page 293 CHAPTER 8 16-bit reload timer I:DDR2,00H ;Setting P20/TIN0 pin to input CLRB I:CNTE0 ;Temporary stop of counter MOVW I:TMRLR0,#2710H;Reload value set to 10000 times MOVW I:TMCSR0,#0000110000001011B ;Counter operating, external trig ;edge, external output disabled ;One-shot mode selection, interru ;Clear interrupt flag, count star ILM,#07H ;Setting ILM in PS to level 7 CCR,#40H...
Page 294 CHAPTER 8 16-bit reload timer...
Page 295: Chapter 9 Watch Timer
CHAPTER 9 Watch timer This section describes the functions and operations of the watch timer. 9.1 Overview of Watch Timer 9.2 Block Diagram of Watch Timer 9.3 Configuration of Watch Timer 9.4 Watch Timer Interrupt 9.5 Explanation of Operation of Watch Timer 9.6 Program Example of Watch Timer...
Page 296: Overview Of Watch Timer
CHAPTER 9 Watch timer Overview of Watch Timer The watch timer is a 15-bit free-run counter that increments in synchronization with the sub clock. • Seven interval times can be selected and an interrupt request can be generated for each interval time. •...
Page 297 CHAPTER 9 Watch timer I Cycle of Clock Supply The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the sub clock and the watchdog timer.Table 9.1-2 shows the cycles of clocks supplied from the watch timer. Table 9.1-2 Cycle of Clock Supply from Watch Timer Receiver of clock supply Clock Cycle...
Page 298: Block Diagram Of Watch Timer
CHAPTER 9 Watch timer Block Diagram of Watch Timer The watch timer consists of the following blocks: • Watch timer counter • Counter clear circuit • Interval timer selector • Watch timer control register (WTC) I Block Diagram of Watch Timer Figure 9.2-1 Block Diagram of Watch Timer To watchdog timer Watch timer counter...
Page 299 CHAPTER 9 Watch timer Interval timer selector The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time set in the watch timer control register (WTC). Watch timer control register (WTC) The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or disables an interrupt, checks the overflow state, and clears the overflow flag bit.
Page 300: Configuration Of Watch Timer
CHAPTER 9 Watch timer Configuration of Watch Timer This section explains the registers and interrupt factors of the watch timer. I List of Registers and Reset Values of Watch Timer Figure 9.3-1 List of Registers and Reset Values of Watch Timer Watch timer control register (WTC) : Undefined I Generation of Interrupt Request from Watch Timer...
Page 301: Watch Timer Control Register (Wtc)
CHAPTER 9 Watch timer 9.3.1 Watch timer control register (WTC) This section explains the functions of the watch timer control register (WTC). I Watch timer control register (WTC) Figure 9.3-2 Watch timer control register (WTC) Reset value 1X001000 bit2 bit1 bit0 WTC2 WTC1...
Page 302 CHAPTER 9 Watch timer Table 9.3-1 Functions of Watch Timer Control Register (WTC) bit name Function bit2 WTC2, WTC1, WTC0: These bits set the interval time of the watch timer. Interval time select bits • When the interval time set by the WTC2 to WTC0 bits is bit0 reached, the corresponding bit of the watch timer counter overflows (carries) and the overflow flag bit is set (WTC:...
Page 303: Watch Timer Interrupt
CHAPTER 9 Watch timer Watch Timer Interrupt When the interval time is reached with the watch timer interrupt enabled, the overflow flag bit is set to 1 and an interrupt request is generated. I Watch Timer Interrupt Table 9.4-1 shows the interrupt control bits and interrupt factors of the watch timer. Table 9.4-1 Interrupt Control Bits of Watch Timer Watch timer Interrupt Factor...
Page 304: Explanation Of Operation Of Watch Timer
CHAPTER 9 Watch timer Explanation of Operation of Watch Timer The watch timer operates as an interval timer or an oscillation stabilization wait time timer of the sub clock.It also supplies an operation clock to the watchdog timer. I Watch timer counter The watch timer counter continues incrementing in synchronization with the sub clock (SCLK) while the sub clock (SCLK) is operating.
Page 305 CHAPTER 9 Watch timer • The overflow flag bit (WTC: WTOF) is set when the interval time is reached at the starting point of the timing at which the watch timer is finally cleared. Clearing overflow flag bit (WTC: WTOF) When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait time timer of sub clock.
Page 306: Program Example Of Watch Timer
CHAPTER 9 Watch timer Program Example of Watch Timer This section gives a program example of the watch timer. I Program Example of Watch Timer Processing specification An interval interrupt at 2 /SCLK (SCLK: sub clock) is generated repeatedly.The internal time is approximately 1.0s (when sub clock operates at 8.192 kHz).
Page 307: Chapter 10 8/16-Bit Ppg Timer
CHAPTER 10 8/16-bit PPG timer This section describes the functions and operations of the 8-/16-bit PPG timer. 10.1 Overview of 8-/16-bit PPG Timer 10.2 Block Diagram of 8-/16-bit PPG Timer 10.3 Configuration of 8-/16-bit PPG Timer 10.4 Interrupts of 8-/16-bit PPG Timer 10.5 Explanation of Operation of 8-/16-bit PPG Timer 10.6 Precautions when Using 8-/16-bit PPG Timer...
Page 308: Overview Of 8-/16-Bit Ppg Timer
• 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output mode • 8 + 8-bit PPG output mode The MB90895 series has two 8-/16-bit PPG timers.This section explains the functions of PPG0/1. PPG2/3 has the same functions as PPG0/1. I Functions of 8-/16-bit PPG Timer The 8-/16-bit PPG timer consists of four eight-bit reload registers (PRLH0/PRLL0, PRLH1/PRLL1) and two PPG down counters (PCNT0, PCNT1).
Page 309 CHAPTER 10 8/16-bit PPG timer I Operation Modes of 8-/16-bit PPG Timer 8-bit PPG output 2-channel independent operation mode The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPG0 and PPG1) to each operate as independent 8-bit PPG timers. Table 10.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode.
Page 310 CHAPTER 10 8/16-bit PPG timer 8 + 8-bit PPG output mode The 8 + 8-bit PPG output mode causes the PPG0 of the 2-channel modules (PPG0 and PPG1) to operate as an 8-bit prescaler and the underflow output of the PPG0 to operate as the count clock of the PPG1. Table 10.1-3 Interval Times in 8+8-bit PPG Output Operation Mode shows the interval times in this mode.
Page 311: Block Diagram Of 8-/16-Bit Ppg Timer
10.2 Block Diagram of 8-/16-bit PPG Timer The MB90895 series contains two 8-/16-bit PPG timers (each with two channels). One 8-/16-bit PPG timer consists of two channels of 8-bit PPG timers. This section shows the block diagrams for the 8-/16-bit PPG timer 0 and 8-/16-bit PPG timer 1.The PPG2 has the same function as the PPG0, and PPG3 has the same function...
Page 312: Block Diagram For 8-/16-Bit Ppg Timer 0
CHAPTER 10 8/16-bit PPG timer 10.2.1 Block Diagram for 8-/16-bit PPG Timer 0 The 8-/16-bit PPG timer 0 consists of the following blocks. I Block Diagram for 8-/16-bit PPG Timer 0 Figure 10.2-2 Block Diagram for 8-/16-bit PPG Timer 0 "H"...
Page 313 CHAPTER 10 8/16-bit PPG timer Details of Pins in Block Diagram Table 10.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 10.2-1 Pins and Interrupt Request Numbers in Block Diagram Channel Output Pin Interrupt Request Number PPG0 P14/PPG0...
Page 314: Block Diagram Of 8-/16-Bit Ppg Timer 1
CHAPTER 10 8/16-bit PPG timer 10.2.2 Block Diagram of 8-/16-bit PPG Timer 1 The 8-/16-bit PPG timer 1 consists of the following blocks. I Block Diagram of 8-/16-bit PPG Timer 1 Figure 10.2-3 Block Diagram of 8-/16-bit PPG Timer 1 "H"...
Page 315 CHAPTER 10 8/16-bit PPG timer Details of pins in block diagram Table 10.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 10.2-2 Pins and Interrupt Request Numbers in Block Diagram Channel Output Pin Interrupt Request Number PPG0 P14/PPG0...
Page 316 CHAPTER 10 8/16-bit PPG timer PPG output control circuit This circuit inverts the pin output level and the output when an underflow occurs.
Page 317: Configuration Of 8-/16-Bit Ppg Timer
CHAPTER 10 8/16-bit PPG timer 10.3 Configuration of 8-/16-bit PPG Timer This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer. I Pins of 8-/16-bit PPG Timer The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 10.3-1 indicates the pin functions and pin settings required to use the 8-/16-bit PPG timer.
Page 318 CHAPTER 10 8/16-bit PPG timer I List of Registers and Reset Values of 8-/16-bit PPG Timer Figure 10.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer PPG0 operating mode control register : H (PPGC1) PPG0 operating mode control register : L (PPGC0) PPG0/1 count clock select register (PPG01)
Page 319: Ppg0 Operation Mode Control Register (Ppgc0)
CHAPTER 10 8/16-bit PPG timer 10.3.1 PPG0 Operation Mode Control Register (PPGC0) The PPG0 operation mode control register (PPGC0) provides the following settings: • Enabling or disabling operation of 8-/16-bit PPG timer • Pin function switching (Enabling or disabling pulse output) •...
Page 320 CHAPTER 10 8/16-bit PPG timer Table 10.3-2 Functions of PPG0 Operation Mode Control Register (PPGC0) bit name Function bit0 Reserved: reserved bit Always set this bit to "1". bit1 Unused bits Read: The value is undefined. bit2 Write: No effect bit3 PUF0: 8-bit PPG output 2-channel independent operation mode,...
Page 321: Ppg1 Operation Mode Control Register (Ppgc1)
CHAPTER 10 8/16-bit PPG timer 10.3.2 PPG1 Operation Mode Control Register (PPGC1) The PPG1 operation mode control register (PPGC1) provides the following settings: • Enabling or disabling operation of 8-/16-bit PPG timer • Pin function switching (Enabling or disabling pulse output) •...
Page 322 CHAPTER 10 8/16-bit PPG timer Table 10.3-3 Functions of PPG1 Operation Mode Control Register (PPGC1) bit name Function bit8 Reserved: reserved bit Always set this bit to "1". bit9 MD1, MD0: These bits set the operation mode of the 8-/16-bit PPG timer. bit10 Operation mode select (Any mode other than 8-bit PPG output 2-channel...
Page 323: Ppg0/1 Count Clock Select Register (Ppg01)
CHAPTER 10 8/16-bit PPG timer 10.3.3 PPG0/1 count clock select register (PPG01) The PPG0/1 count clock select register (PPG01) selects the count clock of the 8-/16-bit PPG timer. I PPG0/1 count clock select register (PPG01) Figure 10.3-4 PPG0/1 count clock select register (PPG01) Reset value 0 0 0 0 0 0 X X bit4...
Page 324 CHAPTER 10 8/16-bit PPG timer Table 10.3-4 Functions of PPG0/1 Count Clock Select Register (PPG01) bit name Function bit0 Undefined Read: The value is undefined. bit1 Write: No effect bit2 PCM2 to PCM0: These bits set the count clock of the 8-/16-bit PPG timer 0. PPG0 count clock select •...
Page 325: Ppg Reload Registers (Prll0/Prlh0, Prll1/Prlh1)
CHAPTER 10 8/16-bit PPG timer 10.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) The value (reload value) from which the PPG down counter starts counting is set in the PPG reload registers.They are an 8-bit register at both Low level and at High level. I PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) Figure 10.3-5 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) bit15 bit14 bit13 bit12 bit11 bit10 bit9...
Page 326: Interrupts Of 8-/16-Bit Ppg Timer
CHAPTER 10 8/16-bit PPG timer 10.4 Interrupts of 8-/16-bit PPG Timer The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter underflows.It corresponds to the EI I Interrupts of 8-/16-bit PPG Timer Table 10.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer. Table 10.4-1 The interrupt control bits of the 8-/16-bit PPG timer PPG0 PPG1...
Page 327 CHAPTER 10 8/16-bit PPG timer I 8-/16-bit PPG Timer Interrupt and EI For details of the interrupt number, interrupt control register, and interrupt vector address, see 3.5 Interrupt. I 8-/16-bit PPG Timer Interrupt and EI OS Function The 8-/16-bit PPG timer corresponds to the EI OS function.
Page 328: Explanation Of Operation Of 8-/16-Bit Ppg Timer
CHAPTER 10 8/16-bit PPG timer 10.5 Explanation of Operation of 8-/16-bit PPG Timer The 8-/16-bit PPG timer outputs a pulse width at any cycle and at any duty ratio continuously. I Operation of 8-/16-bit PPG Timer Output operation of 8-/16-bit PPG timer •...
Page 329: 8-Bit Ppg Output 2-Channel Independent Operation Mode
CHAPTER 10 8/16-bit PPG timer 10.5.1 8-bit PPG output 2-channel independent operation mode In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer with two independent channels.PPG output operation and interrupt request generation can be performed independently for each channel.
Page 330 CHAPTER 10 8/16-bit PPG timer • When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is set (PPGC0: PUF0 = 1, PPGC1: PUF1 = 1).If an interrupt request is enabled at the channel that causes an underflow (PPGC0: PIE0 = 1, PPGC1: PIE1 = 1), the interrupt request is generated.
Page 331: 16-Bit Ppg Output Mode
CHAPTER 10 8/16-bit PPG timer 10.5.2 16-bit PPG output mode In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG timer with one channel. I Setting for 16-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in Figure 10.5-4.
Page 332 CHAPTER 10 8/16-bit PPG timer Operation in 16-bit PPG output operation mode • When either PPG0 pin output or PPG1 pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the same pulse wave is output from both the PPG0 and PPG1 pins. •...
Page 333 CHAPTER 10 8/16-bit PPG timer Output waveform in 16-bit PPG output operation mode • The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle.For example, if the value in the PPG reload register is "0000 ", the pulse width has one count clock cycle, and if the value is "FFFF ", the pulse width has...
Page 334: 8-Bit Ppg Output Mode
CHAPTER 10 8/16-bit PPG timer 10.5.3 8 + 8-bit PPG output mode The PPG0 operates as an 8-bit prescaler and the PPG1 operates using the PPG output of the PPG0 as a clock source. I Setting for 8+8-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in Figure 10.5-6.
Page 335 CHAPTER 10 8/16-bit PPG timer Operation in 8+8-bit PPG output operation mode • The PPG0 operates as the prescaler of the PPG timer and the PPG1 operates using the PPG0 output as a clock source. • When the pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the PPG0 pulse wave is output from the PPG0 pin and the PPG1 pulse wave is output from the PPG1 pin.
Page 336 CHAPTER 10 8/16-bit PPG timer Output waveform in 8-bit PPG output 2-channel independent operation mode • The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. The equations for calculating the pulse width are shown below: PL=T ×...
Page 337: Precautions When Using 8-/16-Bit Ppg Timer
CHAPTER 10 8/16-bit PPG timer 10.6 Precautions when Using 8-/16-bit PPG Timer Precautions when Using 8-/16-bit PPG Timer I Precautions when Using 8-/16-bit PPG Timer Effect on 8-/16-bit PPG timer when using timebase timer output • If the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit PPG timer (PPG01: PCM2 to PCM0 = "111 ", PCS2 to PCS0 = "111 "), deviation may occur in the...
Page 338 CHAPTER 10 8/16-bit PPG timer Setting of PPG reload registers when using 16-bit PPG timer • Use a long-word instruction to set the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) or a word instruction to set the word instruction to set the PPG0 and PPG1 (PRLL0 → PRLL1 or PRLH0 → PRLH1) in this order.
Page 339: Chapter 11 Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module This chapter explains the functions and operations of the delayed interrupt generation module. 11.1 Overview of Delayed Interrupt Generation Module 11.2 Block Diagram of Delayed Interrupt Generation Module 11.3 Configuration of Delayed Interrupt Generation Module 11.4 Explanation of Operation of Delayed Interrupt Generation Module 11.5 Precautions when Using Delayed Interrupt Generation Module 11.6 Program Example of Delayed Interrupt Generation Module...
Page 340: Overview Of Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module 11.1 Overview of Delayed Interrupt Generation Module The delayed interrupt generation module generates the interrupt for task switching. The hardware interrupt request can be generated/cancelled by software. I Overview of Delayed Interrupt Generation Module By using the delayed interrupt generation module, a hardware interrupt request can be generated or cancelled by software.
Page 341: Block Diagram Of Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module 11.2 Block Diagram of Delayed Interrupt Generation Module The delayed interrupt generation module consists of the following blocks: • Interrupt request latch • Delayed interrupt request generate/cancel register (DIRR) I Block Diagram of Delayed Interrupt Generation Module Figure 11.2-1 Block Diagram of Delayed Interrupt Generation Module Internal data bus S Interrupt...
Page 342: Configuration Of Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module 11.3 Configuration of Delayed Interrupt Generation Module This section lists registers and reset values in the delayed interrupt generation module. I List of Registers and Reset Values Figure 11.3-1 List of Registers and Reset Values in Delayed Interrupt Generation Module Delay interrupt request generation/ release register (DIRR) : Undefined...
Page 343: Delayed Interrupt Request Generate/Cancel Register (Dirr)
CHAPTER 11 Delayed interrupt generation module 11.3.1 Delayed interrupt request generate/cancel register (DIRR) The delayed interrupt request generate/cancel register (DIRR) generates or cancels a delayed interrupt request. I Delayed interrupt request generate/cancel register (DIRR) Figure 11.3-2 Delayed interrupt request generate/cancel register (DIRR) Reset value XXXXXXX0 bit8...
Page 344: Explanation Of Operation Of Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module 11.4 Explanation of Operation of Delayed Interrupt Generation Module The delayed interrupt generation module has a function for generating or canceling an interrupt request by software. I Explanation of Operation of Delayed Interrupt Generation Module Using the delayed interrupt generation module requires the setting shown in Figure 11.4-1.
Page 345: Precautions When Using Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module 11.5 Precautions when Using Delayed Interrupt Generation Module This section explains the precautions when using the delayed interrupt generation module. I Precautions when Using Delayed Interrupt Generation Module • The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to "0"...
Page 346: Program Example Of Delayed Interrupt Generation Module
CHAPTER 11 Delayed interrupt generation module 11.6 Program Example of Delayed Interrupt Generation Module This section gives a program example of the delayed interrupt generation module. Program Example of Delayed Interrupt Generation Module Processing specification The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to generate a delayed interrupt request and performs task switching.
Page 347: Chapter 12 Dtp/External Interrupt
CHAPTER 12 DTP/external interrupt This chapter explains the functions and operations of DTP/external interrupt. 12.1 Overview of DTP/External Interrupt 12.2 Block Diagram of DTP/External Interrupt 12.3 Configuration of DTP/External Interrupt 12.4 Explanation of Operation of DTP/External Interrupt 12.5 Precautions when Using DTP/External Interrupt 12.6 Program Example of DTP/External Interrupt Function...
Page 348: Overview Of Dtp/External Interrupt
CHAPTER 12 DTP/external interrupt 12.1 Overview of DTP/External Interrupt The DTP/external interrupt sends interrupt requests from external peripheral devices or data transfer requests to the CPU to generate an external interrupt request, or starts the OS).RX input of CAN controller can be used as external interrupt input. I DTP/External Interrupt Function The interrupt request input from an external peripheral device to the external interrupt input pins (INT7 to INT4) or RX pin is generated in the same way as interrupts by peripheral resources.
Page 349: Block Diagram Of Dtp/External Interrupt
CHAPTER 12 DTP/external interrupt 12.2 Block Diagram of DTP/External Interrupt The block diagram of the DTP/external interrupt is shown below. I Block Diagram of DTP/External Interrupt Figure 12.2-1 Block Diagram of DTP/External Interrupt Detection level setting register (ELVR) served served served served served...
Page 350 CHAPTER 12 DTP/external interrupt DTP/external interrupt input detector This circuit detects interrupt requests or data transfer requests generated from external peripheral devices. The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting register (ELVR) is detected is set to 1 (EIRR: ER).
Page 351: Configuration Of Dtp/External Interrupt
CHAPTER 12 DTP/external interrupt 12.3 Configuration of DTP/External Interrupt This section lists and details the pins, interrupt factors, and registers in the DTP/ external interrupt. I Pins of DTP/External Interrupt The pins used by the DTP/external interrupt serve as general-purpose I/0 ports. Table 12.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt Table 12.3-1 Pins of DTP/External Interrupt Pin Name...
Page 352: Dtp/External Interrupt Factor Register (Eirr)
CHAPTER 12 DTP/external interrupt 12.3.1 DTP/external interrupt factor register (EIRR) This register holds DTP/external interrupt factors. When a valid signal is input to the DTP/external interrupt pin or RX pin, the corresponding interrupt request flag bit is set to "1". I DTP/external interrupt factor register (EIRR) Figure 12.3-2 DTP/external interrupt factor register (EIRR) Reset value...
Page 353: Dtp/External Interrupt Enable Register (Enir)
CHAPTER 12 DTP/external interrupt 12.3.2 DTP/external interrupt enable register (ENIR) The DTP/external interrupt enable register (ENIR) enables/disables the DTP/external interrupt request for external interrupt pins (INT7 to INT4) and the RX pin respectively. I DTP/external interrupt enable register (ENIR) Figure 12.3-3 DTP/external interrupt enable register (ENIR) Reset value 00000000 served...
Page 354: Detection Level Setting Register (Elvr) (High)
CHAPTER 12 DTP/external interrupt 12.3.3 Detection Level Setting Register (ELVR) (High) The detection level setting register (High) sets the levels or edges of input signals that cause interrupt factors in INT7 to INT4 of the DTP/external interrupt pins. I Detection Level Setting Register (ELVR) (High) Figure 12.3-4 Detection Level Setting Register (ELVR) (High) Reset value 00000000...
Page 355: Detection Level Setting Register (Elvr) (Low)
CHAPTER 12 DTP/external interrupt 12.3.4 Detection Level Setting Register (ELVR) (Low) The detection level setting register (ELVR) (Low) sets the levels or edges of input signals that cause interrupt factors in the RX pin. I Detection Level Setting Register (ELVR) (Low) Figure 12.3-5 Detection Level Setting Register (ELVR) (Low) Reset value 00000000...
Page 356: Explanation Of Operation Of Dtp/External Interrupt
CHAPTER 12 DTP/external interrupt 12.4 Explanation of Operation of DTP/External Interrupt The DTP/external interrupt circuit has an external interrupt function and a DTP function.The setting and operation of each function is explained. I Setting of DTP/External Interrupt Circuit Using the DTP/external interrupt requires, the setting shown in Figure 12.4-1. Figure 12.4-1 Setting of DTP/External Interrupt Circuit bit15 14 9 bit8 bit7 6...
Page 357 CHAPTER 12 DTP/external interrupt Selecting of DTP or external interrupt function Whether the DTP function or the external interrupt function is executed depends on the setting of the OS enable bit in the corresponding interrupt control register (ICR: ISE). If the ISE bit is set to "1", the EI OS is enabled and the DTP function is executed.
Page 358 CHAPTER 12 DTP/external interrupt Figure 12.4-2 shows operation of DTP/external interrupt. Figure 12.4-2 Operation of DTP/External Interrupt DTP/external interrupt circuit Other request Interrupt controller ELVR Interrupt EIRR processing ENIR Factor OS start-up DTP/external interrupt request generating Memory Peripheral data trnsmission Descriptor renewal Interrupt controller reception judge...
Page 359: External Interrupt Function
CHAPTER 12 DTP/external interrupt 12.4.1 External Interrupt Function The DTP/external interrupt has an external interrupt function for generating an interrupt request by detecting the signal (edge or level) in the DTP/external interrupt pin or RX pin. I External Interrupt Function •...
Page 360: Dtp Function
CHAPTER 12 DTP/external interrupt 12.4.2 DTP Function The DTP/external interrupt has the DTP function that detects the signal from an external peripheral device through the DTP/external interrupt pin or RX pin to start Extended Intelligent I/O Service (EI OS). I DTP Function The DTP function detects the signal level set by the detection level setting register of the DTP/external interrupt function to start the EI •...
Page 361: Precautions When Using Dtp/External Interrupt
CHAPTER 12 DTP/external interrupt 12.5 Precautions when Using DTP/External Interrupt This section explains the precautions when using the DTP/external interrupt. I Precautions when Using DTP/External Interrupt Circuit Condition of external-connected peripheral device when DTP function is used • When using the DTP function, the peripheral device must automatically clear a data transfer request when data transfer is performed.
Page 362 CHAPTER 12 DTP/external interrupt Figure 12.5-2 DTP/External Interrupt Factor and Interrupt Request Generated when Interrupt Request Enabled DTP/externalinterrupt factor (ehen "H" level detection) Terminated interrupt factor Interrupt request to interrupt controller Being inactive by clearing the DTP/external interrupt request flag bit (EIRR: ER) Precautions on interrupts •...
Page 363: Program Example Of Dtp/External Interrupt Function
CHAPTER 12 DTP/external interrupt 12.6 Program Example of DTP/External Interrupt Function This section gives a program example of the DTP/external interrupt function. I Program Example of DTP/External Interrupt Function Processing specification An external interrupt is generated by detecting the rising edge of the pulse input to the INT4 pin. Coding example ICR06 0000B6H...
Page 364 CHAPTER 12 DTP/external interrupt Programming sample of DTP Function Processing specification • Channel 0 of Extended Intelligent I/O Service (EI OS) is started upon detection of the High level of the signal input to the INT4 pin. • RAM data is output to port 0 by DTP processing (EI OS).
Page 365 CHAPTER 12 DTP/external interrupt LOOP: User processing LOOP ;---------Interrupt program------------------------------------- WARI: CLRB I:ER4 ;Clear INT4 interrupt request flag User processing RETI ;Recovery from interrupt processing CODE ENDS ;---------Vector setting------------------------------------------ VECT CSEG ABS=0FFH 00FF9CH ;Setting vector to interrupt number #24(18 WARI 00FFDCH ;Reset vector setting START...
Page 366 CHAPTER 12 DTP/external interrupt...
Page 367: Chapter 13 8/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter This chapter explains the functions and operation of 8-/ 10-bit A/D converter. 13.1 Overview of 8-/10-bit A/D Converter 13.2 Block Diagram of 8-/10-bit A/D Converter 13.3 Configuration of 8-/10-bit A/D Converter 13.4 Interrupt of 8-/10-bit A/D Converter 13.5 Explanation of Operation of 8-/10-bit A/D Converter 13.6 Precautions when Using 8-/10-bit A/D Converter...
Page 368: Overview Of 8-/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter 13.1 Overview of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital value by using the RC sequential-comparison converter system. • An input signal can be selected from the input signals of the analog input pins for 8 channels.
Page 369: Block Diagram Of 8-/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter 13.2 Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter consists of following blocks. I Block Diagram of 8-/10-bit A/D Converter Figure 13.2-1 Block Diagram of 8-/10-bit A/D Converter A/D control Interrupt requext output status register (ADCS)
Page 370 CHAPTER 13 8/10-bit A/D converter Details of pins in block diagram Table 13.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter Table 13.2-1 Pins and Interrupt Request Numbers in Block Diagram Pin Name/Interrupt Request Number in Block Actual Pin Name/Interrupt Request Diagram Number...
Page 371 CHAPTER 13 8/10-bit A/D converter Decoder This decoder sets the A/D conversion start channel select bits and the A/D conversion end channel select bits in the A/D control status register (ADCS: ANS2 to ANS0 and ANE2 to ANE0) to select the analog input pin to be used for A/D conversion.
Page 372: Configuration Of 8-/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter 13.3 Configuration of 8-/10-bit A/D Converter This section explains the pins, registers, and interrupt factors of the A/D converter. I Pins of 8-/10-bit A/D Converter The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports.Listed below are the pin functions and the settings required for use of the 8-/10-bit A/D converter.
Page 373 CHAPTER 13 8/10-bit A/D converter I List of Registers and Reset Values of 8-/10-bit A/D Converter Figure 13.3-1 List of Registers and Reset Values of 8-/10-bit A/D Converter A/D control status register upper (ADCS: H) A/D control status register lower (ADCS: L) A/D data register upper (ADCR: H) A/D data register lower (ADCR: L)
Page 374: A/D Control Status Register (High) (Adcs: H)
CHAPTER 13 8/10-bit A/D converter 13.3.1 A/D Control Status Register (High) (ADCS: H) The A/D control status register (High) (ADCS: H) provides the following settings: • Starting A/D conversion function by software • Selecting start trigger for A/D conversion • Storing A/D conversion results in A/D data register to enable or disable interrupt request •...
Page 375 CHAPTER 13 8/10-bit A/D converter Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS: H) (1/2) bit name Function bit8 Reserved: reserved bit Always set this bit to "0". bit9 STRT: This bits starts the 8-/10-bit A/D converter by software. A/D conversion software When set to "1": Starts 8-/10-bit A/D converter start bit...
Page 376 CHAPTER 13 8/10-bit A/D converter Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS: H) (2/2) bit name Function bit15 BUSY: This bit forcibly terminates the 8-/10-bit A/D converter.When read, A/D conversion-on flag this bit indicates whether the 8-/10-bit A/D converter is operating or stopped.
Page 377: A/D Control Status Register (Low) (Adcs: L)
CHAPTER 13 8/10-bit A/D converter 13.3.2 A/D Control Status Register (Low) (ADCS: L) The A/D control status register (Low) (ADCS: L) provides the following settings: • Selecting A/D conversion mode • Selecting start channel and end channel of A/D conversion I A/D Control Status Register (Low) (ADCS: L) Figure 13.3-3 A/D Control Status Register (Low) (ADCS: L) Reset value...
Page 378 CHAPTER 13 8/10-bit A/D converter Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS: L) (1/2) bit name Function bit0 ANE2 to ANE0: These bits set the channel at which A/D conversion terminated. A/D conversion end Start channel <...
Page 379 CHAPTER 13 8/10-bit A/D converter Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS: L) (2/2) bit name Function bit6 MD1, MD0: These bits set the A/D conversion mode. bit7 A/D conversion mode Single-shot conversion mode 1: select bits •...
Page 380: A/D Data Register (High) (Adcr: H)
CHAPTER 13 8/10-bit A/D converter 13.3.3 A/D Data Register (High) (ADCR: H) The higher five bits in the A/D data register (ADCR: H) select the compare time, sampling time and resolution of A/D conversion. Bits 9 and 8 in the A/D data register (ADCR) are explained in Section 13.3-4 A/D Data Register (Low) (ADCR: L).
Page 381 CHAPTER 13 8/10-bit A/D converter Table 13.3-4 Functions of A/D Data Register (High) (ADCR: H) bit name Function bit11 CT1, CT0: These bits set the A/D conversion compare time. bit12 Compare time select bits • These bits set the time required from when analog input is A/ D-converted until it is stored in the data bits (D9 to D0).
Page 382: A/D Data Register (Low) (Adcr: L)
CHAPTER 13 8/10-bit A/D converter 13.3.4 A/D Data Register (Low) (ADCR: L) The A/D data register (Low) (ADCR: L) stores the A/D conversion results. Bits 8 and 9 in the A/D data register (ADCR) in this section. I A/D Data Register (Low) (ADCR: L) Figure 13.3-5 A/D Data Register (Low) (ADCR: L) bit9 Reset value...
Page 383: Analog Input Enable Register (Ader)
CHAPTER 13 8/10-bit A/D converter 13.3.5 Analog input enable register (ADER) The analog input enable register (ADER) enables or disables the analog input pins to be used in the 8-/10-bit A/D converter. I Analog input enable register (ADER) Figure 13.3-6 Analog input enable register (ADER) Reset value 11111111 bit0...
Page 384 CHAPTER 13 8/10-bit A/D converter Table 13.3-6 Functions of Analog Input Enable Register (ADER) bit name Function bit0 ADE7 to ADE0: These bits enable or disable the analog input of the pin to be Analog input enable bits used for A/D conversion. When set to "0": Disables analog input bit7 When set to "1": Enables analog input...
Page 385: Interrupt Of 8-/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter 13.4 Interrupt of 8-/10-bit A/D Converter When A/D conversion is terminated and its results are stored in the A/D data register (ADCR), the 8-/10-bit A/D converter generates an interrupt request.The EI OS function can be used. I Interrupt of A/D Converter When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to...
Page 386: Explanation Of Operation Of 8-/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter 13.5 Explanation of Operation of 8-/10-bit A/D Converter The 8-/10-bit A/D converter has the following A/D conversion modes.Set each mode according to the setting of the A/D conversion mode select bits in the A/D control status register (ADCS: MD1, MD0).
Page 387: Single-Shot Conversion Mode
CHAPTER 13 8/10-bit A/D converter 13.5.1 Single-shot conversion mode In the single conversion mode, A/D conversion is performed sequentially from the start channel to the end channel.The A/D conversion pauses after A/D conversion for the end channel. I Setting of Single-shot Conversion Mode Operating the 8-/10-bit A/D converter in the single conversion mode requires the setting shown in Figure 13.5-1.
Page 388 CHAPTER 13 8/10-bit A/D converter [Conversion order in single-shot conversion mode] Table 13.5-1 gives an example of the conversion order in the single-shot conversion mode. Table 13.5-1 Conversion Order in Single-shot Conversion Mode Start Channel End Channel Conversion Order in Single-shot Conversion Mode →...
Page 389: Continuous Conversion Mode
CHAPTER 13 8/10-bit A/D converter 13.5.2 Continuous conversion mode In the continuous conversion mode, A/D conversion is performed sequentially from the start channel to the end channel.When A/D conversion for the end channel is terminated, it is continued after returning to the start channel. I Setting of Continuous Conversion mode Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in Figure 13.5-2.
Page 390 CHAPTER 13 8/10-bit A/D converter [Conversion order in continuous conversion mode] Table 13.5-2 gives an example of the conversion order in the continuous conversion mode. Table 13.5-2 Conversion Order in Continuous Conversion Mode Start Channel End Channel Conversion Order in Continuous Conversion Mode →...
Page 391: Pause-Conversion Mode
CHAPTER 13 8/10-bit A/D converter 13.5.3 Pause-conversion mode In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each channel.When the start trigger is input after the A/D conversion pauses at the termination of the A/D conversion for the end channel, A/D conversion is continued after returning to the start channel.
Page 392 CHAPTER 13 8/10-bit A/D converter [When start and end channels are the same] • If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to ANE0), A/D conversion for one channel set as the start channel (= end channel), and pause are repeated. [Conversion order in pause-conversion mode] Table 13.5-3 gives an example of the conversion order in the pause-conversion mode.
Page 393: Conversion Using Ei 2 Os Function
CHAPTER 13 8/10-bit A/D converter 13.5.4 Conversion Using EI OS Function The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using the EI OS function. I Conversion Using EI The use of the EI OS enables the A/D-converted data protection function to transfer multiple data to memory without the loss of converted data even if A/D conversion is performed continuously.
Page 394: A/D-Converted Data Protection Function
CHAPTER 13 8/10-bit A/D converter 13.5.5 A/D-converted Data Protection Function A/D conversion with the output an interrupt request enabled activates the A/D conversion data protection function. I A/D-converted Data Protection Function in 8-/10-bit A/D Converter The 8-/10-bit A/D converter has only one A/D data register (ADCR) for holding A/D-converted data. When the results of A/D conversion are determined upon completion, data in the A/D data register is updated.Therefore, the A/D conversion results may be lost if the A/D conversion results already stored are not read before data in the A/D data register is rewritten.The A/D-converted data protection function in the...
Page 395 CHAPTER 13 8/10-bit A/D converter Processing flow of A/D conversion data protection function when EI OS used Figure 13.5-5 shows the processing flow of the A/D conversion data protection function when the EI OS is used. Figure 13.5-5 Processing flow of A/D conversion data protection function when EI OS used OS setting A/D sequential conversion...
Page 396 CHAPTER 13 8/10-bit A/D converter Notes: • The A/D conversion data protection function is activated only when an interrupt request is enabled.Set the interrupt request enable bit in the A/D control status register (ADCS: INTE) to "1". • When the EI OS function is used to transfer the A/D conversion results to memory, do not disable output of an interrupt request.If output of an interrupt request is disabled during a pause of A/D conversion (ADCS: INTE = 0), A/D conversion may be restarted to rewrite...
Page 397: Precautions When Using 8-/10-Bit A/D Converter
CHAPTER 13 8/10-bit A/D converter 13.6 Precautions when Using 8-/10-bit A/D Converter Precautions when using the 8-/10-bit A/D converter are given below: I Precautions when Using 8-/10-bit A/D Converter Analog input pin • The analog input pins serve as a general-purpose I/O port of the port 5.To use the pin as an analog input pin, set the port-5 direction register (DDR5) and analog input enable register (ADER) to switch it to an analog input pin.
Page 398 CHAPTER 13 8/10-bit A/D converter...
Page 399: Chapter 14 Uart0
CHAPTER 14 UART0 This chapter explains the functions and operation of the UART0. 14.1 Overview of UART0 14.2 Block Diagram of UART0 14.3 Configuration of UART0 14.4 Interrupt of UART0 14.5 UART0 baud rate 14.6 Explanation of Operation of UART0 14.7 Precautions when using UART0...
Page 400: Overview Of Uart0
CHAPTER 14 UART0 14.1 Overview of UART0 The UART0 is a general-purpose serial-data communication interface for synchronous or asynchronous communication with external devices. • Incorporates a bidirectional communication function (clock synchronous and asynchronous modes) • The master/slave communication function (multiprocessor mode) is incorporated. •...
Page 401 CHAPTER 14 UART0 Table 14.1-2 Operation Mode of UART0 Data length Synchronous Length of Stop Operating mode type With Parity No Parity Normal mode 7 bits or 8 bits Asynchronous 1 bit or 2 bits Multiprocessor Asynchronous mode Clock Clock synchronous None synchronous...
Page 402: Block Diagram Of Uart0
CHAPTER 14 UART0 14.2 Block Diagram of UART0 The UART0 consists of the following block. I Block Diagram of UART0 Figure 14.2-1 Block Diagram of UART0 Control bus Reception interrupt Dedicated request output Transmission baud rate clock generator Transmission 16-bit Clock interrupt Reception...
Page 403 CHAPTER 14 UART0 Details of Pins in Block Diagram The actual pin names and interrupt request numbers used in the UART0 are as follows: SCK pin: P31/SCK0/RD TX pin: P43/TX: P30/SOT0/ALE SIN pin: P32/SIN0/WRL Transmit interrupt number: #39 (27 Receive interrupt number: #40 (28 Clock selector The clock selector selects the transmission/reception clock from among the dedicated baud rate generator, external input clock, and internal clock (clock supplied from 16-bit reload timer 0).
Page 404 CHAPTER 14 UART0 transmission and reception. Serial status register (SSR) The status register checks the transmission/reception status and error status and enables/disables transmission/reception interrupt requests. Serial input data register The register retains the receive data.The serial input is converted and then stored in this register. Serial output data register 0 (SODR0) The register sets the transmit data.Data written to this register is serial-converted and then output.
Page 405: Configuration Of Uart0
CHAPTER 14 UART0 14.3 Configuration of UART0 The UART0 pins, interrupt factors, register list and details are shown. I Pins of UART0 The pins used in the UART0 serve also as general-purpose I/O ports. Table 14.3-1 indicates the pin functions and the setting necessary for use in the UART0. Table 14.3-1 Pins of UART0 Pin Name Pin Function...
Page 406 CHAPTER 14 UART0 I List of Registers in UART0 Figure 14.3-1 List of Registers and Reset Values in UART0 Serial control register (SCR0) Serial mode register (SMR0) Serial status register (SSR0) Serial input data register (SIDR0) /serial output data register (SODR0) Note : Function as SIDR0 when reading, function as SODR0 when writing Serial edge select register (SES0) Communication prescaler control...
Page 407: Serial Control Register 0 (Scr0)
CHAPTER 14 UART0 14.3.1 Serial control register 0 (SCR0) Serial control register 0 (SCR0) is used to set the parity bit, select the stop bit length and data length, select the frame data format in operation mode 1, clear the reception error flag, and to enable/disable transmission and reception.
Page 408 CHAPTER 14 UART0 Table 14.3-2 Functions of Serial Control Register 0 (SCR0) bit name Function bit8 TXE: The bit enables or disables the UART0 for transmission. transmit enable bit When the bit is set to "0": Transmission is disabled. When the bit is set to "1": Transmission is enabled. Note: When transmission is disabled, the device stops transmitting after transmitting the current data from the serial output data register.
Page 409: Serial Mode Register 0 (Smr0)
CHAPTER 14 UART0 14.3.2 Serial mode register 0 (SMR0) Serial mode register 0 (SMR0) is used to select the operation mode, select the baud rate clock, and to disable/enable the output of serial data and clock signal to pins. I Serial mode register 0 (SMR0) Figure 14.3-3 Serial mode register 0 (SMR0) Reset value 00000000...
Page 410 CHAPTER 14 UART0 Table 14.3-3 Functions of Serial Mode Register 0 (SMR0) bit name Function bit0 SOE: Enable or disable output of serial data. Serial-data output enable When the bit is set to "0": The pin is set as a general-purpose I/O port. When the bit is set to "1": The pin is set as a serial data output pin.
Page 411: Serial Status Register 0 (Ssr0)
CHAPTER 14 UART0 14.3.3 Serial status register 0 (SSR0) Serial status register 0 (SSR0) is used to check the reception/transmission status and error status and to enable/disable interrupts. I Serial status register (SSR0) Figure 14.3-4 Serial status register (SSR0) Reset value 00001X00 bit8 Transmission interrupt enable bit...
Page 412 CHAPTER 14 UART0 Table 14.3-4 Function of Serial Status Register 0 (SSR0) bit name Function bit8 TIE: Enable or disable send interrupt. Transmission interrupt When the bit is set to "1": A transmission interrupt request is generated when enable bit the data written to serial output data register 0 is transmitted to the send shift register (SSR0:TDRE=1).
Page 413: Serial Input Data Register 0 (Sidr0) And Serial Output Data Register 0 (Sodr0)
CHAPTER 14 UART0 14.3.4 Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0) The serial input data register and serial output data register are allocated to the same address.The register functions as the serial data input register at a read; the register functions as the serial data output register at a write.
Page 414 CHAPTER 14 UART0 I Serial output data register 0 (SODR0) Figure 14.3-6 Serial output data register 0 (SODR0) bit0 Reset value XXXXXXXX W : Write only X : Undefined The serial output data register 0 (SODR0) is a data buffer register for transmitting serial data. •...
Page 415: Communication Prescaler Control Register 0 (Cdcr0)
CHAPTER 14 UART0 14.3.5 Communication Prescaler Control Register 0 (CDCR0) The communication prescaler control register 0 (CDCR0) is used to set the baud rate of the dedicated baud rate generator for the UART0. • Starts/stop the communication prescaler • Sets the division ratio for machine clock I Communication Prescaler Control Register 0 (CDCR0) Figure 14.3-7 Communication Prescaler Control Register Reset value...
Page 416: Serial Edge Select Register 0 (Ses0)
CHAPTER 14 UART0 14.3.6 Serial edge select register 0 (SES0) Serial edge select register 0 (SES0) inverts the clock signal of the UART0 using an inverter.The register logically inverts the shift clock signal input to the UART0 from Low level to High level and from falling edge to rising edge, or from High level to Low level and from rising edge to falling edge.The inversion acts on the serial clock output, too.
Page 417: Interrupt Of Uart0
CHAPTER 14 UART0 14.4 Interrupt of UART0 The UART0 has reception and transmission interrupts and can generate interrupt requests in the following events. • Receive data is loaded to the serial input data register 0 (SIDR0). • A receive error (parity error, overrun error, framing error) occurs. •...
Page 418 OS can be started separately for receive interrupts and transmit interrupts. At reception: MB90895 series cannot use interrupt vectors as it contains no I C interface. At transmission: Since the interrupt control register (ICR14) is shared with the UART0 for reception interrupts, EI OS can be started only when no interrupt is used for transmission by the UART0.
Page 419: Generation Of Receive Interrupt And Timing Of Flag Set
CHAPTER 14 UART0 14.4.1 Generation of Receive Interrupt and Timing of Flag Set Interrupts during reception are one generated upon completion of reception (SSR:RDRF) and one generated upon occurrence of a reception error (SSR:PE, ORE, FRE). I Generation of Receive Interrupt and Timing of Flag Set Receive data load flag and each receive error flag sets When data is received, it is stored in serial input data register 0 (SIDR0) upon detection of the stop bit (in operation mode 0 or 1) or of the data’s last bit (SIDR0: D7) (in operation mode 2).When a reception error...
Page 420 CHAPTER 14 UART0 Reception and timing of flag set are shown in Figure 14.4-1. Figure 14.4-1 Reception and Timing of Flag Set Reception data (operating mode 0) Reception data (operating mode 1) Reception data (operating mode 2) SSR0 : PE, ORE, FRE SSR0 : RDRF Reception interrupt generating : PE flag is disabled to detect in mode 1.
Page 421: Generation Of Transmit Interrupt And Timing Of Flag Set
CHAPTER 14 UART0 14.4.2 Generation of Transmit Interrupt and Timing of Flag Set An interrupt during transmission is generated when serial output data register 0 (SODR0) becomes empty, or ready to accommodate the next data to transmit. I Generation of Transmit Interrupt and Timing of Flag Set Set and clear of transmit data empty flag bit The transmit data write flag bit (SSR0: TDRE) is set when the transmit data written to serial output data register 0 (SODR0) is transferred to the transmission shift register, making it ready to write the next data to...
Page 422 CHAPTER 14 UART0 Timing of transmit interrupt request A transmission interrupt request is generated when the transmit data write flag bit (SSR0: TDRE) is set with transmission interrupts enabled (SSR0: TIE = 1). Note: If the transmission in progress is disabled (SCR0: TXE = 1, and reception is also disabled with RXE = 0 in operation mode 1), the transmit data write flag bit is set (SSR0: TDRF = 1), the transmission shift register stops shifting, then the UART0 is disabled.
Page 423: Uart0 Baud Rate
CHAPTER 14 UART0 14.5 UART0 baud rate The UART0 transmission/reception clock is selected from among the following options: • Dedicated baud rate generator • Internal clock (16-bit reload timer output) • External clock (clock input to SCK pin) I Select of UART0 Baud Rate The UART0 baud rate select circuit comprises as shown in Figure 14.5-1.The clock input source can be selected from among the following three types: Baud rate by dedicated baud rate generator...
Page 424 CHAPTER 14 UART0 Figure 14.5-1 UART0 Baud Rate Selector SMR0: CS2 to CS0 (Clock input source select bit) Clock selector CS2 to CS0 = "000 " to "100 " [Dedicated baud rate generator] Division circuit φ /3, φ /4, [Clock sync] φ...
Page 425: Baud Rate By Dedicated Baud Rate Generator
CHAPTER 14 UART0 14.5.1 Baud rate by dedicated baud rate generator The baud rate that can be set when the output clock of the dedicated baud rate generator is selected as the transfer clock of the UART0 is shown. I Baud rate by dedicated baud rate generator The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits (SMR0: CS2 to CS0) to "000 "...
Page 426 CHAPTER 14 UART0 Division ratio based on communication prescaler (common between asynchronous and clock synchronous modes) The frequency divide ratio of the machine clock is set by the divide ratio select bits (CDCR0: DIV3 to DIV0) in the communication prescaler control register. Table 14.5-1 Division Ratio Based on Communication Prescaler Communication Prescaler Control Divide...
Page 427 CHAPTER 14 UART0 Baud Rate (Clock Synchronous) Table 14.5-3 Baud Rate (Clock Synchronous) Baud rate selection bit Baud Rate (bps) Calculation φ φ φ /div=2MHz /div=4MHz /div=8MHz φ Reserved / div) / 2 φ 500K / div) / 2 φ 250K 500K / div) / 2...
Page 428: Baud Rate By Internal Timer (16-Bit Reload Timer)
CHAPTER 14 UART0 14.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) The setting when selecting the internal clock supplied from the 16-bit reload timer 1 as the clock input source of the UART0 and the baud rate calculation are shown below. I Baud Rate by Internal Timer (16-bit Reload Timer Output) The baud rate based on the internal timer (16-bit reload timer 0 output) is set by setting the clock input source select bits (SMR0: CS2 to CS0) to "110...
Page 429 CHAPTER 14 UART0 Calculation expression for baud rate φ Asynchronous baud rate = × × X (n + 1) φ Clock synchronous baud rate = × X (n + 1) φ: Machine clock X: Count clock frequency divide ratio for 16-bit reload timer (2, 8, 32) n: 16-bit reload register setting value (0 to 65,535) for 16-bit reload timer (0 to 65,535) Example of setting baud rates and reload register setting values (machine clock frequency: 7.3728 MHz)
Page 430: Baud Rate By External Clock
CHAPTER 14 UART0 14.5.3 Baud rate by external clock This section explains the setting when selecting the external clock as the transmit/ receive clock of the UART0. I Baud rate by external clock The following settings are required for selecting a baud rate depending on the external clock input: •...
Page 431: Explanation Of Operation Of Uart0
CHAPTER 14 UART0 14.6 Explanation of Operation of UART0 The UART0 has the bidirectional serial communication function (operation modes 0 and 2) and master/slave-connection communication function (operation mode 1). I Operation of LIN-UART Operating mode The UART0 has three types of operation modes, they can set the inter-CPU connection mode or data communication mode.
Page 432 CHAPTER 14 UART0 Inter-CPU connection method Either 1-to-1 connection or master/slave type connection can be selected for the inter-CPU controller.In both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for all CPUs.The operation modes are selected as follows. •...
Page 433: Operation In Asynchronous Mode (Operation Mode 0 Or 1)
CHAPTER 14 UART0 14.6.1 Operation in asynchronous mode (operation mode 0 or 1) When the UART0 is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. I Operation in Asynchronous Mode Format of transmit/receive data Transmission and reception always begin with the start bit (Low level);...
Page 434 CHAPTER 14 UART0 Transmission • Data to transmit is written to serial output data register 0 (SODR0) with the transmit data write flag bit (SSR0: TDRE) containing "1". • Transmission starts when the transmission enable bit (SCR0:TXE) in the serial control register is set to "1"with the data to transmit written.
Page 435 CHAPTER 14 UART0 Figure 14.6-2 example of normal operating Communication period Non communication period Non communication period Marc level Start bit Stop bit Data (01010101 transmission) Reception clock Sampling clock Reception clock(8-pulse) Sampling clock is built from 1/16 divided of the reception clock. Recognition of maicrocontroller side (01010101 reception)
Page 436 CHAPTER 14 UART0 Parity bit The addition of a parity bit can be set only in operation mode 0.The parity addition enable bit (SCR0: PEN) and parity select bit (SCR0:P) can be used to select whether to use parity and to set the even or odd parity, respectively.
Page 437: Operation At Clock Synchronous Mode (Operating Mode 2)
CHAPTER 14 UART0 14.6.2 Operation at clock synchronous mode (operating mode 2) When the UART0 is used in operation mode 2, the transfer mode is clock synchronous. I Operation in Clock Synchronous Mode Format of transmit/receive data In clock synchronous mode, 8-bit data is transmitted and received on an LSB-first basis.The start and stop bits are not added to the transmit/receive data.
Page 438 CHAPTER 14 UART0 Clock Supply In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be supplied. • When data is transmitted with the internal clock (dedicated baud rate generator or internal timer) selected (SMR0: CS2 to CS0 = "000 "...
Page 439 CHAPTER 14 UART0 Terminating communications Upon completion of transmitting/receiving one frame of data, the receive data load flag bit (SSR0: RDRF) is set to 1.When data is received, check the overrun error flag bit (SSR0: ORE) to ensure that the communication has performed normally.
Page 440: Bidirectional Communication Function (Operation Modes 0 And 2)
CHAPTER 14 UART0 14.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) In operation modes 0 and 2, serial bidirectional communication can be performed in a one-to-one connection.Operation modes 0 and 2 use asynchronous and clock- synchronous transfers, respectively. I Bidirectional Communication Function The UART0 requires the settings shown in Figure 14.6-6 to operate in operation mode 0 or 2.
Page 441 CHAPTER 14 UART0 Communication procedure Communications start at any timing from the transmitting end when transmit data is provided.On the transmission side, load transmit data into the serial output data register (SODR0) and set the transmission enable bit (SCR0: TXE) in the serial control register to 1 to start transmission. Figure 14.6-8 gives an example of transferring receive data to the transmitting end to inform the transmitting end of normal reception.
Page 442: Master/Slave Type Communication Function (Multi Processor Mode)
CHAPTER 14 UART0 14.6.4 Master/slave type communication function (multi processor mode) Operation mode 1 allows communication between multiple CPUs connected in a master/slave configuration.Note, however, that the function is available only to the master side. I Master/Slave Mode Communication Function The UART0 requires the settings shown in Figure 14.6-9 to operate in operation mode 1.
Page 443 CHAPTER 14 UART0 Function selection At master/slave type communication, select the operation mode and data transfer type. Since the parity check function cannot be used in operation mode 1, set the parity enable bit (SCR0: PEN) to 0. Table 14.6-3 Select of Master/Slave Communication Function Operating mode Synchro Data...
Page 444 CHAPTER 14 UART0 Communication procedure Communication is started by the master CPU by transmitting address data. The address data is data with the A/D bit set to "1". The address data bit (SCR0: A/D) is added to select the slave CPU that the master CPU communicates with.When the program identifies address data and finds a match with the allocated address, each slave CPU starts communications with the master CPU.
Page 445: Precautions When Using Uart0
CHAPTER 14 UART0 14.7 Precautions when using UART0 Use of the UART0 requires the following precautions. I Precautions when using UART0 Enabling sending and receiving The UART0 has the transmission enable bit (SCR0: TXE) and reception enable bit (SCR0: RXE) provided for transmission and reception.
Page 446 CHAPTER 14 UART0...
Page 447: Chapter 15 Uart1
CHAPTER 15 UART1 This chapter explains the functions and operation of the UART. Overview of UART1 Block Diagram of UART1 Configuration of UART1 Interrupt of UART1 UART1 Baud Rate Explanation of Operation of UART1 Precautions when Using UART1 Program Example for UART1...
Page 448: Overview Of Uart1
CHAPTER 15 UART1 15.1 Overview of UART1 The UART1 is a general-purpose serial-data communication interface for synchronous or asynchronous communication with external devices. • Incorporates a bidirectional communication function (clock synchronous and asynchronous modes) • Incorporates a master/slave type communication function (in multiprocessor mode: only master) •...
Page 449 CHAPTER 15 UART1 Table 15.1-2 Operation Mode of UART1 Data length Synchronous Length of Stop Operating mode type With Parity No Parity Asynchronous mode (Normal 7 bits or 8 bits Asynchronous mode) 1 bit or 2 bits Multiprocessor mode Asynchronous Synchronous mode Synchronous None...
Page 450: Block Diagram Of Uart1
CHAPTER 15 UART1 15.2 Block Diagram of UART1 The UART1 consists of the following block. I Block Diagram of UART1 Figure 15.2-1 Block Diagram of UART1 Control bus Reception interrupt request output Dedicated baud Transmission rate generator clock Transmission interrupt 16-bit Clock request output...
Page 451 CHAPTER 15 UART1 Details of Pins in Block Diagram The actual pin names and interrupt request numbers used in the UART1 are as follows: SIN1 pin: P40/SIN1 SCK1 pin: P41/SCK1 SOT1 pin: P42/SOT1 Transmit interrupt number 1: #38 (26 Receive interrupt number 1: #37 (25 Clock selector The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external input clock, and internal clock (clock supplied from 16-bit reload timer).
Page 452 CHAPTER 15 UART1 Serial mode register 1 (SMR1) This register: Selects operation mode Selects clock input source (baud rate) Sets dedicated baud rate generator Selects clock speed (clock division value) when using dedicated baud rate generator Enables or disables output of serial data and clock pins Initialize UART Serial control register 1 (SCR1) This register:...
Page 453: Configuration Of Uart1
CHAPTER 15 UART1 15.3 Configuration of UART1 The UART1 pins, interrupt factors, register list and details are shown. UART1 Pin The pins used in the UART1 serve as general-purpose I/O port. indicates the pin functions and the setting necessary for use in the UART1. Table 15.3-1 UART1 Pin Pin Name Pin Function...
Page 454 CHAPTER 15 UART1 I List of Registers in UART1 Figure 15.3-1 List of Registers and Reset Values in UART1 Serial control register 1 (SCR1) Serial mode register 1 (SMR1) Serial status register 1 (SSR1) Serial input data register 1 (SIDR1) /serial output data register 1 (SODR1) Note : Function as SIDR1 when reading, function as SODR1 when writing.
Page 455: Serial Control Register 1 (Scr1)
CHAPTER 15 UART1 15.3.1 Serial control register 1 (SCR1) The serial control register 1 (SCR1) performs the following: setting parity bit, selecting stop bit length and data length, selecting frame data format in operation mode 1, clearing receive error flag, and enabling/disabling of transmitting/receiving. I Serial control register 1 (SCR1) Figure 15.3-2 Serial control register 1 (SCR1) Reset value...
Page 456 CHAPTER 15 UART1 Table 15.3-2 Functions of Serial Control Register 1 (SCR1) bit name Function bit8 TXE: Enable or disable the UART1 for sending. Transmit enable bit When set to "0": Transmission disabled When set to "1": Transmission enabled Note: When transmitting is disabled during transmitting, transmitting stops after the data in the serial input data register being transmitted is completed in the serial input data register.-...
Page 457: Serial Mode Register 1 (Smr1)
CHAPTER 15 UART1 15.3.2 Serial mode register 1 (SMR1) The serial mode register 1 (SMR1) performs selecting operation mode, selecting baud rate clock, and disabling/enabling of output of serial data and clock to pin. I Serial mode register 1 (SMR1) Figure 15.3-3 Serial mode register 1 (SMR1) Reset value 00000000...
Page 458 CHAPTER 15 UART1 Table 15.3-3 Functions of Serial Mode Register 1 (SMR1) bit name Function bit0 SOE: Enable or disable output of serial data. Serial-data output When set to "0": "General-purpose I/O port" set enable bit When set to "1": "Serial data output pin" set bit1 SCKE: Switch between input and output of the serial clock.
Page 459: Serial Status Register 1 (Ssr1)
CHAPTER 15 UART1 15.3.3 Serial status register 1 (SSR1) The serial status register 1 (SSR1) checks the transmission/reception status and error status and enables/disables interrupts. I Serial status register 1 (SSR1) Figure 15.3-4 Serial status register 1 (SSR1) Reset value 00001000 bit8 Transmission interrupt generating enable bit...
Page 460 CHAPTER 15 UART1 Table 15.3-4 Functions of Serial Status Register 1 (SSR1) (1/2) bit name Function bit8 TIE: Enable or disable send interrupt. Transmit interrupt When set to "1": A receive interrupt request is issued when request enable bit data written to the serial output data register 1 (SODR1) is sent to the transmit shift register (bit 11: TDRE = 1).
Page 461 CHAPTER 15 UART1 Table 15.3-4 Functions of Serial Status Register 1 (SSR1) (2/2) bit name Function bit14 ORE: Detect an overrun error in receiving. Overrun error flag bit • This bit is set to "1" when an overrun error occurs. •...
Page 462: Serial Input Data Register 1 (Sidr1) And Serial Output Data Register 1 (Sodr1)
CHAPTER 15 UART1 15.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1) The serial input data register and serial output data register are allocated to the same address.At read, the register functions as SIDR1. At write, the register functions as SODR.
Page 463 CHAPTER 15 UART1 I Serial output data register 1 (SODR1) Figure 15.3-6 Serial output data register 1 (SODR1) bit0 Reset value XXXXXXXX R : Read only X : Undefined The serial output data register 1 (SODR1) is a data buffer register for transmitting serial data. •...
Page 464: Communication Prescaler Control Register 1 (Cdcr1)
CHAPTER 15 UART1 15.3.5 Communication Prescaler Control Register 1 (CDCR1) The communication prescaler control register 1 (CDCR1) is used to set the baud rate of the dedicated baud rate generator for the UART1. • Starts/stop the communication prescaler • Sets the division ratio for machine clock I Communication Prescaler Control Register 1 (CDCR1) Figure 15.3-7 Communication Prescaler Control Register 1 (CDCR1) Reset value...
Page 465 CHAPTER 15 UART1 Table 15.3-5 Functions of Communication Prescaler Control Register 1 (CDCR1) (2/2) bit name Function bit15 This bit enables or disables the communication prescaler. Communication When set to "0": Stops communication prescaler prescaler control bit When set to "1": Operates communication prescaler...
Page 466: Interrupt Of Uart1
CHAPTER 15 UART1 15.4 Interrupt of UART1 The UART1 has a receive and a transmit interrupts, and the following factors can issue interrupt requests. • Receive data is loaded to the serial input data register 1 (SIDR1). • A receive error (parity error, overrun error, framing error) occurs. •...
Page 467 CHAPTER 15 UART1 Reception Interrupt When a receive interrupt is enabled (SSR1 register bit 9: RIE = 1), a receive interrupt request is issued at completion of data receiving (SSR1 register bit 12: RDRF = 1) or when any one of the overrun error (SSR1 register bit 14: ORE = 1), framing error (SSR 1 register bit 13: FRE = 1), and parity error (SSR 1 register bit 15: PE = 1) occurs.
Page 468: Generation Of Receive Interrupt And Timing Of Flag Set
CHAPTER 15 UART1 15.4.1 Generation of Receive Interrupt and Timing of Flag Set Interrupts at receiving include the receive completion (SSR1 register bit 12: RDRF), and the receive error (SSR1 register bit 15, 14, 13: PE, ORE, FRE). I Generation of Receive Interrupt and Timing of Flag Set Receive data load flag and each receive error flag sets When data is received, it is stored in the serial input data register (SIDR) when the stop bit is detected (in operation modes 0 and 1: Asynchronous normal mode, Asynchronous multiprocessor mode) or when the...
Page 469 CHAPTER 15 UART1 Figure 15.4-1 Reception and Timing of Flag Set Reception data (operating mode 0) Reception data (operating mode 1) Reception data (operating mode 2) SSR1 PE, ORE, FRE SSR1 RDRF Reception interrupt generating : PE flag is not detected in operating mode 1. PE and FRE flag are detected in operating mode 2.
Page 470: Generation Of Transmit Interrupt And Timing Of Flag Set
CHAPTER 15 UART1 15.4.2 Generation of Transmit Interrupt and Timing of Flag Set The transmit interrupt is generated when the serial output data register (SODR1) is empty, and is in a state where the next transmitted data can be written. I Generation of Transmit Interrupt and Timing of Flag Set Set and clear of transmit data empty flag bit The send data write flag bit (SSR1 register bit 11: TDRE) is set when the send data written to the serial...
Page 471: Uart1 Baud Rate
CHAPTER 15 UART1 15.5 UART1 Baud Rate One of the following can be selected as the UART1 transmit/receive clock. • Dedicated baud rate generator • Internal clock (16-bit reload timer output) • External clock (clock input to SCK1 pin) I Select of UART1 Baud Rate The UART1 baud rate select circuit comprises as shown in .The clock input source can be selected from among the following three types: Baud rate by dedicated baud rate generator...
Page 472 CHAPTER 15 UART1 Figure 15.5-1 UART Baud Rate Selector SMR1: CS2 to CS0 (Clock input source select bit) Clock selector CS2 to CS0 = "000 " to "101 " [Dedicated baud rate generator] Division circuit [Clock synchronous] φ/1, φ/2, φ/3, φ/4, φ...
Page 473: Baud Rate By Dedicated Baud Rate Generator
CHAPTER 15 UART1 15.5.1 Baud rate by dedicated baud rate generator The baud rate that can be set when the output clock of the dedicated baud rate generator is selected as the transfer clock of the UART1 is shown. I Baud rate by dedicated baud rate generator The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits in the serial mode register (SMR1 register bit 5 to 3: CS2 to CS0) to "000 "...
Page 474 CHAPTER 15 UART1 Division ratio based on communication prescaler (common between asynchronous and clock synchronous modes) The division ratio of the machine clock is set by the division ratio select bits in the communication prescaler control register (CDCR1 register bit 10 to 8: DIV2 to DIV0). Table 15.5-1 Division Ratio Based on Communication Prescaler DIV2 DIV1...
Page 475 CHAPTER 15 UART1 Baud rate (clock mode) The baud rate in the synchronous mode is generated by dividing the output clock of the communication prescaler by 1, 2, 4, 8, 16 and 32.The division ratio is set by the clock input source select bits (SMR1 register bit 5 to 3: CS2 to CS0).
Page 476: Baud Rate By Internal Timer (16-Bit Reload Timer)
CHAPTER 15 UART1 15.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) The setting when selecting the internal clock supplied from the 16-bit reload timer 1 as the clock input source of the UART1 and the baud rate calculation are shown below. I Baud Rate by Internal Timer (16-bit Reload Timer Output) The baud rate based on the internal timer (16-bit reload timer output) is set by setting the clock input source select bits (SMR1 register bit 5 to 3: CS2 to CS0) to "110...
Page 477 CHAPTER 15 UART1 Example of setting baud rates and reload register setting values (machine clock frequency: 7.3728 MHz) Table 15.5-4 Baud Rate and Reload Value Reload Value Clock Asynchronous (start-stop Clock synchronous Baud Rate synchronization) (bps) N = 2 (machine N = 2 (machine N = 2...
Page 478: Baud Rate By External Clock
CHAPTER 15 UART1 15.5.3 Baud rate by external clock This section explains the setting when selecting the external clock as the transmit/ receive clock of the UART1. I Baud rate by external clock To select a baud rate by the external clock input, the following settings are essential: •...
Page 479: Explanation Of Operation Of Uart1
CHAPTER 15 UART1 15.6 Explanation of Operation of UART1 The UART1 has master/slave type connection communication function (operation mode 1: asynchronous multiprocessor mode) in addition to bidirectional serial communication functions (operation modes 0 and 2: asynchronous normal mode and clock synchronous mode) I Operation of UART1 Operating mode The UART1 has three types of operation modes, they can set the inter-CPU connection mode or data...
Page 480 CHAPTER 15 UART1 asynchronous multiprocessor mode (SMR1 register bit 7, 6: MD1, MD0 = "01B" is set. Select operation mode 1 (asynchronous multiprocessor mode) and use it as the master. For this connection, select no parity 8-bit data length. Synchronous type For the operation modes, either the asynchronous mode (start-stop synchronization) or the clock- synchronous mode can be selected.
Page 481: Operation In Asynchronous Mode (Operation Mode 0 Or 1)
CHAPTER 15 UART1 15.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) When the UART1 is used in operation mode 0 (asynchronous normal mode) or operation mode 1 (asynchronous multiprocessor mode), the asynchronous transfer mode is selected. I Operation in Asynchronous Mode Format of transmit/receive data Transmission and reception always start with the start bit (Low level);...
Page 482 CHAPTER 15 UART1 Transmission • Transmit data is written to the serial output data register 1 (SODR1) with the transmit data write flag bit (SSR1 register bit 11: TDRE) set to "1". • Transmission starts when transmit data is written and the transmit enable bit of the serial control register (SCR1 register bit 8: TXE) is set to "1".
Page 483 CHAPTER 15 UART1 Figure 15.6-2 example of normal operating Communication period Non communication period Non communication period Marc level Start bit Stop bit Data (01010101 transmission) Reception clock Sampling clock Reception clock(8-pulse) Sampling clock is built from 1/16 divided of the reception clock. Recognition of maicrocontroller side (01010101 reception)
Page 484 CHAPTER 15 UART1 The transmit/receive data when the parity bit enabled are shown in Figure 15.6-4. Figure 15.6-4 Transmit/Receive Data when Parity Bit Enabled Reception Parity error generated SIN1 with reception in even parity (SCR1: PEN = 1, P = 0) Transmission Transmission in even parity SOT1...
Page 485: Operation In Clock Synchronous Mode (Operation Mode 2)
CHAPTER 15 UART1 15.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) When the UART1 is used in operation mode 2, the transfer mode is clock synchronous. I Operation in Clock Synchronous Mode Format of transmit/receive data In the synchronous mode, 8-bit data is transmitted/received on LSB-first.The start and stop bits are not added to the transmit/receive data.
Page 486 CHAPTER 15 UART1 11: TDRE = 0) in the serial output data register (SODR1). Also, before and after transmitting, always return to the mark level (High level). Error detection Only overrun errors can be detected.Parity and framing errors cannot be detected. Setting of register shows the setting of the control register in transmitting serial data from the transmitting end to the receiving end using the clock synchronous mode (operation mode 2).
Page 487: Bidirectional Communication Function (Operation Modes 0 And 2)
CHAPTER 15 UART1 15.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) In operation modes 0 and 2 (asynchronous normal mode, clock synchronous mode), normal serial bidirectional communications using 1-to-1 connection can be performed.For operation mode 0 (asynchronous normal mode), the asynchronous mode is used;...
Page 488 CHAPTER 15 UART1 Figure 15.6-7 Example of Bidirectional Communication Connect for UART Output Input CPU-1 CPU-2 Communication procedure Communications start at any timing from the transmitting end when transmit data is provided.At the transmitting end, set transmit data in the serial output data register (SODR1) and set the transmitting enable bit in the serial control register (SCR1 register bit 8: TXE) to 1 to start transmitting.
Page 489: Master/Slave Type Communication Function (Multiprocessor Mode)
CHAPTER 15 UART1 15.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) Operation mode 1 (asynchronous multiprocessor mode) enables communications by the master/slave connection of more than one CPU.Only the master CPU functions. I Master/Slave Mode Communication Function To operate the UART1 in operation mode 1 (asynchronous multiprocessor mode), the setting shown in is required.
Page 490 CHAPTER 15 UART1 Figure 15.6-10 Example of Master/Slave Mode Communication Connect for UART1 SOT1 SIN1 Master CPU Slave CPU #0 Slave CPU #1 Function selection At master/slave type communication, select the operation mode and data transfer type. Since the parity check function cannot be used in operation mode 1 (asynchronous multiprocessor mode), set the parity add enable bit (SCR1 register bit 15: PEN) to 0.
Page 491 CHAPTER 15 UART1 Communication procedure Communications start when the master CPU transmits address data. The address data is data with the A/D bit set to 1. The address/data select bit (SCR1 register bit 11: A/D) is added to select the slave CPU that the master CPU communicates with.When the program identifies address data and finds a match with the allocated address, each slave CPU starts communications with the master CPU.
Page 492: Precautions When Using Uart1
CHAPTER 15 UART1 15.7 Precautions when Using UART1 Use of the UART1 requires the following precautions. I Precautions when Using UART1 Enabling sending and receiving The send enable bit (SCR1 register bit 8: TXE) and receive enable bit (SCR1 register bit 9: RXE) are provided for sending and receiving.
Page 493: Program Example For Uart1
CHAPTER 15 UART1 15.8 Program Example for UART1 This section gives a program example for the UART1. Program Example for UART1 Processing contents The bidirectional communication function (normal mode) of the UART1 is used to perform serial transmission/reception. • Set operation mode 0, asynchronous mode (normal), 8-bit data length, 2-bit stop bit length, and no parity.
Page 494 CHAPTER 15 UART1 I:SSR1,#00000010B ; Disable transmission interrupt and enable reception interrupt I:SODR1,#13H ; Write transmission data ILM,#07H ; Setting ILM in PS to level 7 CCR,#40H ; Enable interrupt LOOP: MOV A,#00H ; No limit roop A,#01H LOOP ; ------Interrupt program-------------------------------------------- WARI: A,SIDR1 ;...
Page 495: Chapter 16 Can Controller
CHAPTER 16 CAN controller This chapter explains the functions and operations of the CAN controller. 16.1 Overview of CAN Controller 16.2 Block Diagram of CAN Controller 16.3 Configuration of CAN Controller 16.4 Interrupts of CAN Controller 16.5 Explanation of Operation of CAN Controller 16.6 Precautions when Using CAN Controller 16.7 Program Example of CAN Controller...
Page 496: Overview Of Can Controller
CHAPTER 16 CAN controller 16.1 Overview of CAN Controller The CAN (controller area network) is a serial communication protocol conformed to CAN Ver.2.0A and Ver.2.0B.Transmitting and receiving can be performed in the standard frame format and the extended frame format. I Features of CAN controller •...
Page 497: Block Diagram Of Can Controller
CHAPTER 16 CAN controller 16.2 Block Diagram of CAN Controller The CAN controller consists of two types of registers; one controls the CAN controller and the other controls each message buffer. I Block Diagram of CAN Controller Figure 16.2-1 Block Diagram of CAN Controller Operating clock (TQ) MC-16LX bus CPU operating...
Page 498 CHAPTER 16 CAN controller Bit timing register (BTR) This register sets the division ratio at which CAN bit timing is generated. Control status register (CSR) This register controls the operation of the CAN controller.It indicates the state of transmitting/receiving and the CAN bus, controls interrupts, and controls the bus halt and indicates its state.
Page 499 CHAPTER 16 CAN controller Receive RTR register (RRTRR) When a remote frame is stored in a message buffer, the bit corresponding to the number of the message buffer is set. Receive overrun register (ROVRR) This register sets the bit corresponding to the number of the buffer that overruns when the message is received.
Page 500: Configuration Of Can Controller
CHAPTER 16 CAN controller 16.3 Configuration of CAN Controller This section explains the pins and, related registers, interrupt factors of the CAN controller. I Pins of CAN Controller Table 16.3-1 CAN controller pin Pin name Function Pin setting during used by CAN Transmitting output pin Set transmitting output pin General purpose I/O port...
Page 501 CHAPTER 16 CAN controller I CAN Controller Registers Figure 16.3-1, Figure 16.3-2 and Figure 16.3-3 list the registers of the CAN controller. Figure 16.3-1 Registers of CAN Controller (Control Registers) CAN controller control register bit15 bit8 bit7 bit0 Reset value Reserved area BVALR (Message buffer valid register) 00000000...
Page 502 CHAPTER 16 CAN controller Figure 16.3-2 Registers of CAN Controller (ID Register and DLC Register) Message buffer (ID register) bit15 bit8 bit7 bit0 Reset value XXXXXXXX XXXXXXXX RAM (general purpose RAM) (16byte) XXXXXXXX XXXXXXXX IDR0 (ID register 0) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IDR1 (ID register 1)
Page 503 CHAPTER 16 CAN controller Figure 16.3-3 Registers of CAN Controller (DTR Register) Message buffer (DTR register) bit15 bit8 bit7 bit0 Reset value XXXXXXXX XXXXXXXX DTR0 (Data register 0) (8byte) XXXXXXXX XXXXXXXX DTR1 (Data register 1) (8byte) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR2 (Data register 2) (8byte) XXXXXXXX...
Page 504: Control Status Register (High) (Csr: H)
CHAPTER 16 CAN controller 16.3.1 Control Status Register (High) (CSR: H) The control status register (CSR) controls operation of the CAN controller.The control status register (High) (CSR: H) transmits and receives the message and indicates the node status. I Control Status Register (High) (CSR: H) Figure 16.3-4 Control Status Register (High) (CSR: H) Reset value 0 0 X X X 0 0 0...
Page 505 CHAPTER 16 CAN controller Table 16.3-2 Functions of Control Status Register (High) (CSR: H) bit name Function bit8 NS1, NS0: The combination of the NS1 and NS0 bits indicates the current bit9 Node status bits node status. "00 ": Error active "01 ": Warning (error active) "10...
Page 506: Control Status Register (Low) (Csr: L)
CHAPTER 16 CAN controller 16.3.2 Control Status Register (Low) (CSR: L) The control status register (CSR) controls operation of the CAN controller.The control status register (Low) (CSR: L) enables and disables transmit interrupt and node status transition interrupt and, controls bus halt and indicates the node status. I Control Status Register (Low) (CSR: L) Figure 16.3-5 Control Status Register (Low) (CSR: L) Reset value...
Page 507 CHAPTER 16 CAN controller Table 16.3-3 Functions of Control Status Register (Low) (CSR: L) (1/2) bit name Function bit0 HALT: This bit controls the bus halt.The halt state of the bus can be checked by reading the HALT bit. Bus halt bit At reading "0": on bus operation "1": halting bus operation...
Page 508 CHAPTER 16 CAN controller Table 16.3-3 Functions of Control Status Register (Low) (CSR: L) (2/2) bit name Function bit2 NIE: This bit controls generation of a node status transition interrupt when the node status transits (CSR: NT = 1). Node status When set to "0": Disables interrupt generation transition When set to "1": Enables interrupt generation...
Page 509: Last Event Indication Register (Leir)
CHAPTER 16 CAN controller 16.3.3 Last event indication register (LEIR) This register indicates the state of the last event (LEIR). I Last event indication register (LEIR) Figure 16.3-6 Last event indication register (LEIR) bit7 Reset value 0 0 0 X X 0 0 0 bit1 bit2 bit0...
Page 510 CHAPTER 16 CAN controller Table 16.3-4 Function of the last event display register (LEIR) Bit name Function bit0 MBP2 to 0: These bits indicate the number (x) of the message buffer where the last event message buffer occurs which is corresponding to each message buffer pointer bit. bit2 pointer bit Receiving completed: Indicates number (x) of message buffer that completes...
Page 511: Receive/Transmit Error Counter (Rtec)
CHAPTER 16 CAN controller 16.3.4 Receive/Transmit Error Counter (RTEC) The receive/transmit error counter (RTEC) indicates the number of times an error occurs at transmitting and receiving the message.It counts up when transmit or receive errors occurs and counts down when transmitting and receiving are performed normally.
Page 512 CHAPTER 16 CAN controller I Node Status Transition due to Error Occurrence In the CAN controller, the node status transits according to the error count of the receive/transmit error counter (RTEC).Figure 16.3-8 shows the node status transition. Figure 16.3-8 Node Status Transition Hardware reset When transfering, need to release of bus operation stop...
Page 513: Bit Timing Register (Btr)
CHAPTER 16 CAN controller 16.3.5 Bit timing register (BTR) The bit timing register (BTR) sets the prescaler and bit timing.Set this after halting the bus (CSR: HALT = 1). I Bit timing register (BTR) Figure 16.3-9 Bit timing register (BTR) bit 15 Reset value TS2.2...
Page 514 • PROP_SEG (propagation segment): The physical delay among networks is adjusted. • PHASE_SEG (phase segment): The phase shift due to oscillation errors is adjusted. Bit time segments of Fujitsu CAN controller The propagation segment (PROP_SEG) and phase segment 1 (PHASE_SEG1) are used as a single segment of time segment 1 (TSEG1).The phase segment 2 (PHASE_SEG2) is used as the time segment 2 (TSEG2).
Page 515 CHAPTER 16 CAN controller I Calculation of Bit Timing Figure 16.3-12 and Figure 16.3-13 show the calculation example of bit timing, respectively, assuming input clock (CLK), time quantum (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1, 2 (TSEG1, TSEG2), re-synchronous jump width (RSJW), frequency divided (PSC). Figure 16.3-12 Calculation of Bit Timing •...
Page 516 CHAPTER 16 CAN controller Figure 16.3-13 Calculation Example of Bit Timing Example : When 1TQ is 1/20 bit timing at 100Kbps (1/100Kbps/20) Condition : (resynchronous jump width is 4TQ, delay time is 50µs) × (1) Calculations of time quantum (TQ) [TQ = (PSC + 1) CLK] (Unit: µs) Division of input clock (PSC+1)
Page 517: Message Buffer Validating Register (Bvalr)
CHAPTER 16 CAN controller 16.3.6 Message buffer validating register (BVALR) The message buffer valid register (BVALR) enables or disables the message buffers and indicates their status. I Message buffer validating register (BVALR) Figure 16.3-14 Message buffer validating register (BVALR) Reset value 00000000 bit0 Message buffer enable bit 0...
Page 518 CHAPTER 16 CAN controller Table 16.3-8 Functions of Message Buffer Enable Register Bit name Function bit0 BVAL7 to 0: These bits enable or disable transmitting and receiving of the Message buffer enable message to and from the message buffer (x). bit7 bits 7 to 0 When set to 0: No message can be transmitted and received to...
Page 519: Ide Register (Ider)
CHAPTER 16 CAN controller 16.3.7 IDE register (IDER) The IDE register (IDER) sets the frame format of the message buffer used during transmitting and receiving.Transmitting and receiving are enabled in the standard frame format (ID11 bits) and the extended frame format (ID29 bits). I IDE register (IDER) Figure 16.3-15 IDE register (IDER) Reset value...
Page 520 CHAPTER 16 CAN controller Table 16.3-9 Functions of IDE Register (IDER) Bit name Function bit0 IDE7 to 0: Set the frame format used in the message buffer (x). ID Format select bits 7 When set to 0: Uses message buffer (x) in standard format (ID11 bit7 to 0 bits)
Page 521: Transmit Request Register (Treqr)
CHAPTER 16 CAN controller 16.3.8 Transmit request register (TREQR) The transmission request register (TREQR) sets a transmit request for each message buffer and indicates its status. I Transmit request register (TREQR) Figure 16.3-16 Transmit request register (TREQR) Reset value 00000000 bit0 Transmission request bit 0 (message buffer 0) TREQ0...
Page 522 CHAPTER 16 CAN controller Table 16.3-10 Functions of Transmission Request Register (TREQR) Bit name Function bit0 TREQ7 to 0: These bits starts transmitting for the message buffer (x). Transmission request When set to 0: No effect on operation bit7 bits 7 to 0 When set to 1: Starts transmitting for message buffer (x) - If more than one transmit complete bit is set (TREQx = 1), transmitting is started with the lower number of the...
Page 523: Transmit Rtr Register (Trtrr)
CHAPTER 16 CAN controller 16.3.9 Transmit RTR register (TRTRR) This register sets the frame format of transmit message for the message buffers. I Transmit RTR register (TRTRR) Figure 16.3-17 Transmit RTR register (TRTRR) Reset value 0 0 0 0 0 0 0 0 bit0 Remote frame setting bit 0 TRTR0...
Page 524 CHAPTER 16 CAN controller • When "0" is written to each bit in the transmit RTR register (TRTRR), the data frame format is set. When "1" is written to each bit, the remote frame format is set. Table 16.3-11 Functions of Transmission RTR Register (TRTRR) Bit name Function bit0...
Page 525: Remote Frame Receive Waiting Register (Rfwtr)
CHAPTER 16 CAN controller 16.3.10 Remote frame receive waiting register (RFWTR) Remote frame receiving wait register (RFWTR) sets whether a remote frame receiving wait occurs or not, when transmission request of data frame is set. I Remote frame receive waiting register (RFWTR) Figure 16.3-18 Remote frame receive waiting register (RFWTR) Reset value XXXXXXXX...
Page 526 CHAPTER 16 CAN controller Table 16.3-12 Functions of Remote Frame Receiving Wait Register (RFWTR) Bit name Function bit0 RFWT7 to 0: These bits set whether to wait for reception of a remote frame Remote frame receive for the message buffer (x) for which a request to transmit a data bit7 bits 7 to 0 frame is set.
Page 527: Transmission Cancel Register (Tcanr)
CHAPTER 16 CAN controller 16.3.11 Transmission cancel register (TCANR) The transmission cancel register (TCANR) sets cancellation of a transmission request for the message buffer in the transmit wait state. I Transmit cancel register (TCANR) Figure 16.3-19 Transmit cancel register (TCANR) Reset value 00000000 bit0...
Page 528 CHAPTER 16 CAN controller Table 16.3-13 Functions of Transmission Cancel Register (TCANR) Bit name Function bit0 TCAN7 to 0: These bits cancel a transmission request for the message buffer Transmission on cancel (x) in the transmit wait state. bit7 bits 7 to 0 When set to 0: No effect on operation When set to 1: Cancels transmission request for message buffer •...
Page 529: Transmit Complete Register (Tcr)
CHAPTER 16 CAN controller 16.3.12 Transmit complete register (TCR) The transmission complete register (TCR) indicates whether a data transmission from the message buffer completes.When an output of interrupt is enabled at completing transmitting, an interrupt request is output when transmission is completed. I Transmit complete register (TCR) Figure 16.3-20 Transmit complete register (TCR) Reset value...
Page 530 CHAPTER 16 CAN controller Table 16.3-14 Functions of Transmission Complete Register (TCR) Bit name Function bit0 TC7 to 0: These bits indicate whether the message buffer (x) completes Transmission complete transmitting message. bit7 bits 7 to 0 When message transmitting completed: 1 is set to the TCx bit corresponding to the message buffer (x) that completes transmitting.
Page 531: Transmit Complete Interrupt Enable Register (Tier)
CHAPTER 16 CAN controller 16.3.13 Transmit complete interrupt enable register (TIER) The transmission complete interrupt enable register (TIER) enables or disables a transmit complete interrupt for each message buffer. I Transmit complete interrupt enable register (TIER) Figure 16.3-21 Transmit complete interrupt enable register (TIER) Reset value 0 0 0 0 0 0 0 0 bit0...
Page 532 CHAPTER 16 CAN controller Table 16.3-15 Functions of Transmission Complete Interrupt Enable Register (TIER) Bit name Function bit0 TIE7 to 0: These bits enable or disable a transmission complete interrupt Transmission complete for the message buffer (x). bit7 interrupt enable bits 7 to When set to 0: Disables transmit complete interrupt for message buffer (x) When set to 1: Enables transmit complete interrupt for message...
Page 533: Receive Complete Register (Rcr)
CHAPTER 16 CAN controller 16.3.14 Receive complete register (RCR) The reception complete register (RCR) indicates whether the reception of data to the message buffer (x) completes. When an interrupt is enabled at completion of receiving, an interrupt request is generated. I Receive complete register (RCR) Figure 16.3-22 Receive complete register (RCR) Reset value...
Page 534 CHAPTER 16 CAN controller Table 16.3-16 Functions of Reception Complete Register (RCR) Bit name Function bit0 RC7 to0: These bits indicate whether the message buffer (x) completes Reception complete bit 7 message transmitting. bit7 to 0 When message receiving completed: 1 is set to the RCx bit corresponding to the message buffer (x) that completes receiving.
Page 535: Receive Rtr Register (Rrtrr)
CHAPTER 16 CAN controller 16.3.15 Receive RTR register (RRTRR) The reception RTR register (RRTRR) indicates that the remote frame is stored in the message buffer. I Receive RTR register (RRTRR) Figure 16.3-23 Receive RTR register (RRTRR) Reset value 0 0 0 0 0 0 0 0 bit0 Remot frame receive bits0 RRTR0...
Page 536 CHAPTER 16 CAN controller Table 16.3-17 Functions of Reception RTR Register (RRTRR) Bit name Function bit0 RRTR7 to 0: These bits indicate that the message buffer (x) receives a remote Remote frame receive frame. bit7 bits 7 to 0 When remote frame is received: 1 is set to the RRTRx bit corresponding to the message buffer (x) that receives a remote frame.
Page 537: Receive Overrun Register (Rovrr)
CHAPTER 16 CAN controller 16.3.16 Receive overrun register (ROVRR) The reception overrun register (ROVRR) indicates that an overrun occurs (the corresponding message buffer is in the receive complete state) at storing the received message in the message buffer. I Receive overrun register (ROVRR) Figure 16.3-24 Receive overrun register (ROVRR) Reset value 0 0 0 0 0 0 0 0...
Page 538 CHAPTER 16 CAN controller Table 16.3-18 Functions of Reception Overrun Register (ROVRR) Bit name Function bit0 ROVR7 to 0: These bits indicate that an overrun occurs at storing the received Reception overrun bit 7 message in the message buffer that had completed receiving. bit7 to 0 At overrun: 1 is set to the ROVRx bit corresponding to the...
Page 539: Receive Complete Interrupt Enable Register (Rier)
CHAPTER 16 CAN controller 16.3.17 Receive complete interrupt enable register (RIER) The reception complete interrupt enable register (RIER) enables or disables a reception complete interrupt for each message buffer. I Receive complete interrupt enable register (RIER) Figure 16.3-25 Receive complete interrupt enable register (RIER) Reset value 0 0 0 0 0 0 0 0 bit0...
Page 540 CHAPTER 16 CAN controller Table 16.3-19 Functions of Reception Complete Interrupt Enable Register (RIER) Bit name Function bit0 RIE7 to 0: These bits enable or disable a reception complete interrupt for Reception complete the message buffer (x). bit7 interrupt enable bits 7 to When set to 0: Disables reception complete interrupt for message buffer (x) When set to 1: Enables reception complete interrupt for message...
Page 541: Acceptance Mask Select Register (Amsr)
CHAPTER 16 CAN controller 16.3.18 Acceptance mask select register (AMSR) The acceptance mask select register (AMSR) selects the mask (acceptance mask) format for comparison between the identifier (ID) of the received message and the message buffer. I Acceptance mask select register (AMSR) Figure 16.3-26 Acceptance mask select register (AMSR) bit15 Reset value...
Page 542 CHAPTER 16 CAN controller Table 16.3-20 Functions of Acceptance Mask Select Register (AMSR) Bit name Function bit0 ASM7.0 to 0.0, 7.1 to These bits select the mask (acceptance mask) format for 0.1: comparison between the received message ID and message buffer ID (IDR) for the message buffer (x).
Page 543: Acceptance Mask Select Register (Amr)
CHAPTER 16 CAN controller 16.3.19 Acceptance Mask Select Register (AMR) The CAN controller contains two acceptance mask registers (AMR0 and AMR1), each of which can be used in the standard frame format (ID11 bits, AM28 to AM18) and the extended frame format (ID29 bits, AM28 to AM0). I Acceptance Mask Select Register (AMSR) Figure 16.3-27 Acceptance Mask Select Register (AMSR) bit7...
Page 544 CHAPTER 16 CAN controller Table 16.3-21 Functions of Acceptance Mask Register (AMR) Bit name Function bit0 AM21 to AM28: These bits set whether to compare or mask each bit at collating Acceptance mask bit 28 the acceptance code set in the ID register (IDR: IDx) with the to 21 (BYTE0) received message ID.
Page 545: Message Buffers
CHAPTER 16 CAN controller 16.3.20 Message Buffers The message buffers consist of ID register, DLC register, and data register and are used for transmission/reception of messages. I Message Buffers • There are 8 message buffers. • One message buffer x (x = 0 to 7) consists of the ID register (IDRx), DLC register (DLCRx), and data register (DTRx).
Page 546: Id Register (Idrx, X = 7 To 0)
CHAPTER 16 CAN controller 16.3.21 ID Register (IDRx, x = 7 to 0) The ID register (IDR) sets the ID of the message buffer used for transmitting and receiving.In the standard frame format 11 bits from ID28 to ID18 are used, and in the extended frame format 29 bits from ID28 to ID0 are used.
Page 547 CHAPTER 16 CAN controller Table 16.3-22 Functions of ID Register (IDR) Bit name Function bit0 ID28 to 21: These bits set the acceptance code or transmit message ID to be ID bit 28 to 21(BYTE0) collated with the received message ID. Standard frame format (IDER: IDEx = 0): 11 bits from ID28 to ID18 are used.
Page 548 CHAPTER 16 CAN controller Setting example of ID register (IDR) Table 16.3-23 gives a setting example of the ID register (IDR) in the standard and extended frame formats. Table 16.3-23 Example of ID Setting in Standard and Extended Frame Formats Standard frame format Extended frame format ID (Dec)
Page 549: Dlc Register (Dlcr)
CHAPTER 16 CAN controller 16.3.22 DLC Register (DLCR) DLC register (DLCR) for message buffer. The DLC register (DLCR) sets the data length of the message to be transmitted or received. I DLC Register (DLCR) Figure 16.3-29 DLC Register (DLCR) bit7 bit6 bit5 bit4...
Page 550: Data Register (Dtr)
CHAPTER 16 CAN controller 16.3.23 Data Register (DTR) Data register (DTR) for message buffer. The data register (DTR) sets the messages at transmitting or receiving a data frame.The data length can be set from 0 to 8 bytes. I Data Register (DTR) Figure 16.3-30 Data Register (DTR) bit 7 Reset value...
Page 551: Interrupts Of Can Controller
CHAPTER 16 CAN controller 16.4 Interrupts of CAN Controller The CAN controller has a transmit complete interrupt, receive complete interrupt and node state transition interrupt, and can generate interrupts when; • The transmission complete bit (TCR: TCx) is set. • The reception complete bit (RCR: RCx) is set. •...
Page 552 CHAPTER 16 CAN controller Node status transition interrupt When the node status of the CAN controller changes, "1" is set to the NT bit in the control status register (CSR).If a node status transition interrupt is enabled (CSR: NIE = 1) when NT = 1, a node status transition interrupt is generated.When "0"...
Page 553: Explanation Of Operation Of Can Controller
CHAPTER 16 CAN controller 16.5 Explanation of Operation of CAN Controller This section explains the procedures for transmitting and receiving messages and the setting of bit timing, frame format, ID and acceptance filter. I Explanation of Operation of CAN Controller The following sections provide more details of the operation of CAN controller.
Page 554: Transmission
CHAPTER 16 CAN controller 16.5.1 Transmission Figure 16.5-1 shows a transmission flowchart. I Transmission procedure Figure 16.5-1 Transmission Flowchart Set transmission request register (TREQR:TREQx=1) Clear transmission completio register (TCR:TCx=0) NO:0 Set transmission request? (TREQR:TREQx) YES:1 NO:0 Remote frame reception waiting? (RFWTR:RFWTx) YES:1 NO:0...
Page 555 CHAPTER 16 CAN controller Starting transmission Setting of transmission request To start transmitting, set the TREQx bit in the transmission request register to "1" which corresponding to the message buffer (x) that transmits the message.When the TREQx bit is set, the transmission complete register is cleared (TCR: TCx = 0).
Page 556 CHAPTER 16 CAN controller Completing transmission Success of transmission When transmission is terminated normally, the TCx bit in the transmission complete register is set.The transmission request register and receive RTR register (TREQR: TREQx = 0, RRTRR: RRTRx = 0) are cleared.
Page 557: Reception
CHAPTER 16 CAN controller 16.5.2 Reception Figure 16.5-2 shows a reception flowchart. I Reception procedure Figure 16.5-2 Reception Flowchart Detecting start of frame (SOF) in data frame or remote frame With message buffer (X) through acceptance filt? Reception successed? Determining message buffer (X) storing receives message Storing received message in message buffer (X)
Page 558 CHAPTER 16 CAN controller Starting reception Reception is started when the start-of-frame (SOF) of a data frame or remote frame is detected on the CAN bus. Acceptance filter The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDER: IDEx = 0).The received message in the extended frame format is compared with the message buffer (x) set in the extended frame format (IDER: IDEx = 1).
Page 559 CHAPTER 16 CAN controller • The message buffers should be arranged in order of ascending number (x) as follows; - Smallest number (x): Acceptance mask set to full-bit comparison - Middle number (x): Acceptance mask registers 0 and 1 used - Largest number (x): Acceptance mask set to "full-bit masking"...
Page 560 CHAPTER 16 CAN controller Reception overrun When another received message is stored in the message buffer that has completed receiving (RCR: RCx = 1), a reception overrun occurs.When a reception overrun occurs, "1" is set to the ROVRx bit in the reception overrun register corresponding to the number of the message buffer (x) where the reception overrun occurs.
Page 561: Procedures For Transmitting And Receiving
CHAPTER 16 CAN controller 16.5.3 Procedures for Transmitting and Receiving The section explains the procedure for transmission/reception of message. I Presetting Setting of bit timing • Set the bit timing register (BTR) after halting the bus operation (CSR: HALT = 1). Setting of frame format •...
Page 562 CHAPTER 16 CAN controller I Procedure for Transmitting message Buffer (x) Figure 16.5-4 shows a procedure for the transmit setting. Figure 16.5-4 Flowchart of Procedure for Transmit Setting START Setting of bit timing Bit timing register (BTR) Setting of frame for mat IDE register (IDER) Setting of ID ID register (IDR)
Page 563 CHAPTER 16 CAN controller Procedure for Transmitting message Buffer (x) After completion of presetting, set the message buffer (x) enabled (BVALR: BVALx =1) by message buffer enable register. Setting transmit data length code • Set the transmit data length code (byte count) to the DLC3 to DLC0 bits in the DLC register (DLCR). •...
Page 564 CHAPTER 16 CAN controller Setting of transmission request To set a transmission request, set the TREQx bit in the transmission request register to "1". Canceling transmission request • To cancel the transmission request held in the message buffer (x), write 1 to the TCANx bit in the transmission cancel register.
Page 565 CHAPTER 16 CAN controller I Procedure for Receiving Message Buffer (x) Figure 16.5-5 shows the procedure for the receiving setting. Figure 16.5-5 Flowchart of Procedure for Receive Setting START Setting of bit timing Bit timing register (BTR) Setting of frame for mat IDE register (IDER) Setting of ID ID register (IDR)
Page 566 CHAPTER 16 CAN controller Starting receiving To start receiving after the completion of setting, set the BVALx bit in the message buffer enable register (BVALR) to "1" and enable the message buffer (x). Canceling bus halt After the completion of setting bit timing and transmission, write "0" to the HALT bit in the control status register (CSR: HALT) to cancel the bus halt.
Page 567 CHAPTER 16 CAN controller Figure 16.5-6 Example of Reception Interrupt Processing RCx=1 at interrupt generation Received message is read A:=ROVRx ROVRx:=0 A=0? RCx: 0...
Page 568: Setting Multiple Message Reception
CHAPTER 16 CAN controller 16.5.4 Setting Multiple Message Reception • When there is insufficient time to receive messages such as frequently received messages or messages with different IDs, more than one message buffer can be combined to a multiple message buffer to give the CPU sufficient time to process received messages.
Page 569 CHAPTER 16 CAN controller Figure 16.5-7 Example of Operation of Multiple Message Buffer AMS7 AMS6 AMS5 Initialization AMSR Acceptance Maskregister choice AM28 to AM18 IDE7 IDE6 IDE5 AMR0 0000 1111 111 IDER ID28 to ID18 Message Buffers5 0101 0000 000 0101 0000 000 ROVRR Message Buffers6...
Page 570: Precautions When Using Can Controller
CHAPTER 16 CAN controller 16.6 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. I Caution for disabling message buffers by BVAL bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to transmit messages).
Page 571: Program Example Of Can Controller
CHAPTER 16 CAN controller 16.7 Program Example of CAN Controller This section shows the program example of CAN controller. I Program Example of CAN Transmission and Reception Processing specification • Set buffer 5 of CAN to data frame transmit mode and buffer 0 to data frame receive mode. •...
Page 572 CHAPTER 16 CAN controller Coding example ;//Data format ste (CAN resets) MOVW BTR,#05CC7H ;Baud Rate set100Kbps ; (Machine clock=16MHz) MOVW IDER,#0000H ;Setting of frame for mat ; (0:standard,1:extended) MOVW IDR51,#0A000H ;Data frame 5 ID set (ID=5) MOVW IDR01,#2000H ;Data frame 0 ID set (ID=1) MOVW AMSR,#0000H ;Acceptance mask select register ;...
Page 573: Chapter 17 Address Match Detecting Function
CHAPTER 17 Address Match Detecting Function This chapter explains the address match detection functions and its operation. 17.1 Overview of Address Match Detection Function 17.2 Block Diagram of Address Match Detection Function 17.3 Configuration of Address Match Detection Function 17.4 Explanation of Operation of Address Match Detection Function 17.5 Program Example of Address Match Detection Function...
Page 574: Overview Of Address Match Detection Function
CHAPTER 17 Address Match Detecting Function 17.1 Overview of Address Match Detection Function If the address of the instruction to be processed next after the instruction currently being processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be INT9 instruction, and branches to interrupt processing program.
Page 575: Block Diagram Of Address Match Detection Function
CHAPTER 17 Address Match Detecting Function 17.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR) • Detect address setting registers I Block Diagram of Address Match Detection Function Figure 17.2-1 shows the block diagram of the address match detection function.
Page 576: Configuration Of Address Match Detection Function
CHAPTER 17 Address Match Detecting Function 17.3 Configuration of Address Match Detection Function This section details the registers used by the address match detection function. I List of Registers and Reset Values of Address Match Detection Function Figure 17.3-1 List of Registers and Reset Values of Address Match Detection Function Address detection control registes (PACSR) Detect address setting registers 0 (PADR0) : High...
Page 577: Address Detection Control Register (Pacsr)
CHAPTER 17 Address Match Detecting Function 17.3.1 Address detection control register (PACSR) The address detection control register (PACSR) enables or disables output of an interrupt at an address match.When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. I Address detection control register (PACSR) Figure 17.3-2 Address detection control register (PACSR) Reset value...
Page 578 CHAPTER 17 Address Match Detecting Function Table 17.3-1 Functions of Address Detection Control Register (PACSR) bit name Function bit0 Reserved: reserved bit Always set this bit to "0". bit1 AD0E: The address match detection operation with the detect address Address match detection setting register 0 (PADR0) is enabled or disabled.
Page 579: Detect Address Setting Registers (Padr0, Padr1)
CHAPTER 17 Address Match Detecting Function 17.3.2 Detect address setting registers (PADR0, PADR1) The value of an address to be detected is set in the detect address setting registers.When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
Page 580 CHAPTER 17 Address Match Detecting Function I Functions of Detect Address Setting Registers • There are two detect address setting registers (PADR0 and PADR1) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 17.3-2 Address Setting of Detect Address Setting Registers Register Name Interrupt Address Setting...
Page 581: Explanation Of Operation Of Address Match Detection Function
CHAPTER 17 Address Match Detecting Function 17.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 and PADR1), the address match detection function will replace the first instruction with the INT9 instruction ("01 ") and branch to interrupt processing program.
Page 582: Example Of Using Address Match Detection Function
CHAPTER 17 Address Match Detecting Function 17.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. I System Configuration and E PROM Memory Map System configuration Figure 17.4-2 gives an example of the system configuration using the address match detection function.
Page 583 CHAPTER 17 Address Match Detecting Function PROM Memory Map Figure 17.4-3 shows the allocation of the patch program and data at storing the patch program in E PROM. Figure 17.4-3 Allocation of E PROM Patch Program and Data PROM Address 0 0 0 0 Patch program byte count 0 0 0 1...
Page 584 • Address match detection is enabled (PACSR: AD0E = 1, AD1E = 1) INT9 Interrupt processing • Interrupt processing is performed by the INT9 instruction.MB90895 series has no interrupt request flag by address match detection.Therefore, if the stack information in the program counter is discarded, the detect address cannot be checked.When checking the detect address, check the value of program counter...
Page 585 CHAPTER 17 Address Match Detecting Function I Operation of Address Match Detection Function at Storing Patch Program in E PROM Figure 17.4-4 shows the operation of the address match detection function at storing the patch program in PROM. Figure 17.4-4 Operation of Address Match Detection Function at Storing Patch Program in E PROM 000000 Patch program...
Page 586 CHAPTER 17 Address Match Detecting Function I Flow of Patch Processing Figure 17.4-5 shows the flow of patch processing using the address match detection function. Figure 17.4-5 Flow of Patch Processing PROM 0000 Patch program byte count :80 0001 Detect address(Low) 0002 Detect address(Middle) :80 0003...
Page 587: Program Example Of Address Match Detection Function
CHAPTER 17 Address Match Detecting Function 17.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. I Program Example of Address Match Detection Function Processing specification If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed.
Page 588 CHAPTER 17 Address Match Detecting Function...
Page 589: Chapter 18 Rom Mirroring Function Selection Module
CHAPTER 18 ROM Mirroring Function Selection Module This chapter describes the functions and operations of the ROM mirroring function select module. 18.1 Overview of ROM Mirroring Function Selection Module 18.2 ROM Mirroring Function Selection Register (ROMM)
Page 590: Overview Of Rom Mirroring Function Selection Module
CHAPTER 18 ROM Mirroring Function Selection Module 18.1 Overview of ROM Mirroring Function Selection Module The ROM mirroring function select module provides a setting so that ROM data in the FF bank can be read by access to the 00 bank. I Block Diagram of ROM Mirroring Function Select Module Figure 18.1-1 Block Diagram of ROM Mirroring Function Select Module ROM Mirroring Function Select register...
Page 591 CHAPTER 18 ROM Mirroring Function Selection Module I Memory Space when ROM Mirroring Function Enabled/Disabled Figure 18.1-3 shows the availability of access to memory space when the ROM mirroring function is enabled or disabled Figure 18.1-3 Memory Space when ROM Mirroring Function Enabled/Disabled (in Single Chip Mode) When ROM mirroring When ROM mirroring function is enabled...
Page 592: Rom Mirroring Function Selection Register (Romm)
CHAPTER 18 ROM Mirroring Function Selection Module 18.2 ROM Mirroring Function Selection Register (ROMM) The ROM mirroring function select register (ROMM) enables or disables the ROM mirroring function.When the ROM mirroring function is enabled, ROM data in the FF bank can be read by access to the 00 bank. I ROM Mirroring Function Select Register (ROMM) Figure 18.2-1 ROM Mirroring Function Select Register (ROMM) Reset Value...
Page 593: Chapter 19 512 Kbit Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY This chapter describes the function and operation of the 512 Kbit flash memory. 19.1 "Overview of 512 Kbit Flash Memory" 19.2 "Registers and Sector/Bank Configuration of Flash Memory" 19.3 "Flash Memory Control Status Register (FMCS)" 19.4 "Flash Memory Write Control Register (FWR0/1)"...
Page 594: Overview Of 512 Kbit Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.1 Overview of 512 Kbit Flash Memory There are three ways of programming and erasing flash memory as follows: 1. Programming and erasing using parallel writer 2. Programming and erasing using serial writer 3. Programming and erasing by executing program This chapter describes the above "3.
Page 595: Registers And Sector/Bank Configuration Of Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.2 Registers and Sector/Bank Configuration of Flash Memory This section explains the registers and the sector/bank configuration of flash memory. I List of Registers and Reset Values of Flash Memory Figure 19.2-1 List of Registers and Reset Values of Flash Memory ´...
Page 596 CHAPTER 19 512 KBIT FLASH MEMORY Figure 19.2-2 Sector Configuration of 512 Kbit Flash Memory Flash memory CPU address Writer address* F F 0 0 0 0 7 0 0 0 0 SA0 (4 Kbytes) FF0FFF 7 0 F F F F F 1 0 0 0 7 1 0 0 0 SA1 (4 Kbytes)
Page 597: Flash Memory Control Status Register (Fmcs)
CHAPTER 19 512 KBIT FLASH MEMORY 19.3 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS) functions are shown in Figure 19.3-1 "Functions of Flash Memory Control Status Register (FMCS)". I Flash Memory Control Status Register (FMCS) Figure 19.3-1 Flash Memory Control Status Register (FMCS) Reset value 0 0 0 X 0 0 0 0...
Page 598 CHAPTER 19 512 KBIT FLASH MEMORY Table 19.3-1 Functions of Flash Memory Control Status Register (FMCS) Bit Name Function bit 0 to bit 3 Reserved: Reserved Always set these bits to 0. bits bit 4 RDY: This bit shows the programming/erasing status of flash memory. Flash memory •...
Page 599 CHAPTER 19 512 KBIT FLASH MEMORY Note: The flash memory operation flag bit (RDYINT) and flash memory programming/erasing status bit (RDY) do not change simultaneously. A program should be created so as to identify the termination of programming/erasing using either the RDYINT bit or RDY bit. Automatic algorithm end timing RDYINT bit...
Page 600: Flash Memory Write Control Register (Fwr0/1)
CHAPTER 19 512 KBIT FLASH MEMORY 19.4 Flash Memory Write Control Register (FWR0/1) The flash memory write control register (FWR0/1) is a register in the flash memory interface, used to set the accidental write preventive function for the flash memory. I Flash memory write control register (FWR0/1) The flash memory write control register (FWR0/1) contains the write-enable/protect bits for individual sectors (SA0 to SA9).
Page 601 CHAPTER 19 512 KBIT FLASH MEMORY Figure 19.4-2 Flash Memory Write-Protect, Write-Enable, Accidental-Write-Preventive Status Example in the Flash Memory Write Control Register (FWR0/1) Register Register Initialize Initialize write write accidental- Write Write write- Write protected protected prevent enabled SA0E Write Write accidental-write-prevent protected...
Page 602 CHAPTER 19 512 KBIT FLASH MEMORY Table 19.4-1 Functions of Flash Memory Write Control Register (FWR0/1) Bit Name Function bit 10 to Reserved: Reserved bits Always set these bits to 0. bit 15 bit 0 to bit 9 These bits are used to set the accidental write preventive function SA9E to SA0E: Accidental write for the individual sectors of the flash memory.
Page 603 CHAPTER 19 512 KBIT FLASH MEMORY I Flash Memory Write Control Register (FWR0/1) Setting Flow Set the FMCS:WE bit, then set the bits for sectors to write to and the bits for sectors to be prevented from an accidental write in the flash memory write control register (FWR0/1) to "1" and "0", respectively.
Page 604 CHAPTER 19 512 KBIT FLASH MEMORY I Setting of FMCS:WE When writing the flash memory, after setting the FMCS:WE bit to "1" in order to be write-enabled, then set the flash memory write control register (FWR0/1). In case of FMCS:WE is "0", writing is disabled even if the flash memory write control register (FWR0/1) is write-enabled.
Page 605: How To Start Automatic Algorithm Of Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.5 How to Start Automatic Algorithm of Flash Memory There are four commands for starting the automatic algorithm of flash memory: read/ reset, write, chip erase. The sector erase command controls suspension and resumption. I Command Sequence Table Table 19.5-1 lists the commands to be used to program or erase the flash memory.
Page 606 CHAPTER 19 512 KBIT FLASH MEMORY I Notes on Command Issuance Pay attention to the following points when issuing commands in the command sequence table: • Write-enable each required sector before issuing the first command. • The upper address "U" bits (bits 15 to 12) used when commands are issued must have the same value as RA, PA, and SA, from the first command on.
Page 607: Reset Vector Addresses In Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.6 Reset Vector Addresses in Flash Memory The MB90F897 uses hardwired reset vectors. In CPU mode, any read access to addresses FFFFDCH to FFFFDFH returns a hardware- fixed value. In flash memory mode, by contrast, these addresses are accessible. Writing to these addresses is therefore meaningless.
Page 608: Check The Execution State Of Automatic Algorithm
CHAPTER 19 512 KBIT FLASH MEMORY 19.7 Check the Execution State of Automatic Algorithm Since the programming/erasing flow is controlled by the automatic algorithm, hardware sequence flag can check the internal operating state inside of flash memory. I Hardware Sequence Flags Overview of hardware sequence flag The hardware sequence flag consists of the following 5-bit outputs: •...
Page 609 CHAPTER 19 512 KBIT FLASH MEMORY Explanation of hardware sequence flag Table 19.7-2 "List of Hardware Sequence Flag Functions" lists the functions of the hardware sequence flag. Table 19.7-2 List of Hardware Sequence Flag Functions State State change in Programming Æ Completed DQ7 →...
Page 610: Data Polling Flag (Dq7)
CHAPTER 19 512 KBIT FLASH MEMORY 19.7.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is a hardware sequence flag which mainly used to notify that the automatic algorithm is executing or has been completed using the data polling function.
Page 611 CHAPTER 19 512 KBIT FLASH MEMORY At sector erasing suspension • Read access during sector erasing suspension causes flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. Flash memory outputs bit 7 (DATA: 7) of the read value at the address specified by the signal address if the address specified by the address signal does not belong to the sector being erased.
Page 612: Toggle Bit Flag (Dq6)
CHAPTER 19 512 KBIT FLASH MEMORY 19.7.2 Toggle Bit Flag (DQ6) The toggle bit flag is a hardware sequence flag used to notify that the automatic algorithm is being executed or in the end state using the toggle bit function. I Toggle Bit Flag (DQ6) Table 19.7-5 "State Transition of Toggle Bit Flag (State Change at Normal Operation)"...
Page 613: Timing Limit Over Flag (Dq5)
CHAPTER 19 512 KBIT FLASH MEMORY 19.7.3 Timing Limit Over Flag (DQ5) The timing limit over flag (DQ5) is a hardware sequence flag that notifies flash memory that the execution of the automatic algorithm has exceeded a prescribed time (the time required for programming/erasing).
Page 614: Sector Erase Timer Flag (Dq3)
CHAPTER 19 512 KBIT FLASH MEMORY 19.7.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag is used to notify during the period of waiting for sector erasing after the sector erase command has started. I Sector Erase Timer Flag (DQ3) Table 19.7-9 "State Transition of Sector Erase Timer Flag (State Change at Normal Operation)"...
Page 615: Toggle Bit 2 Flag (Dq2)
CHAPTER 19 512 KBIT FLASH MEMORY 19.7.5 Toggle Bit 2 Flag (DQ2) The toggle bit 2 flag (DQ2) is a hardware sequence flag that notifies flash memory that sector erasing is being suspended using the toggle bit function. I Toggle Bit Flag (DQ2) Table 19.7-11 "State Transition of Toggle Bit Flag (State Change at Normal Operation)"...
Page 616 CHAPTER 19 512 KBIT FLASH MEMORY At sector erasing suspension • If a continuous read access is made in the state of the sector erasing suspension, flash memory outputs 1 and 0 alternately when the read address is the sector being erased and bit 2 (DATA: 2) for the read value of the read address when the read address is not the sector being erased.
Page 617: Details Of Programming/Erasing Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.8 Details of Programming/Erasing Flash Memory This section explains the procedure for inputting commands starting the automatic algorithm, and for read/reset of flash memory, programming, chip erasing, sector erasing, sector erasing suspension and sector erasing resumption. I Detailed Explanation of Programming and Erasing Flash Memory The automatic algorithm can be started by programming the command sequence of read/reset, programming, chip erasing, sector erasing, sector erasing suspension and erasing resumption...
Page 618: Read/Reset State In Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.8.1 Read/Reset State in Flash Memory This section explains the procedure for inputting the read/reset command to place flash memory in the read/reset state. I Read/Reset State in Flash Memory • Flash memory can be placed in the read/reset state by transmitting the read/reset command in the command sequence table from CPU to flash memory.
Page 619: Data Programming To Flash Memory
CHAPTER 19 512 KBIT FLASH MEMORY 19.8.2 Data programming to flash memory This section explains the procedure for inputting the program command to program data to flash memory. I Data Programming to Flash Memory • In order to start the data programming automatic algorithm, continuously transmit the program command in the command sequence table from CPU to flash memory.
Page 620 CHAPTER 19 512 KBIT FLASH MEMORY Figure 19.8-1 Example of Data Programming Procedure Start FMCS: WE (bit5) Programming enabled FFWR0/1 Accidental write preventive function setting (Accidental write preventive sector: 0, writing sector :1 ) Program command sequence (1)FFUAAA XXAA (2)FFU554 XX55 (3)FFUAAA XXA0...
Page 621: Data Erase From Flash Memory (Chip Erase)
CHAPTER 19 512 KBIT FLASH MEMORY 19.8.3 Data Erase from Flash Memory (Chip Erase) This section explains the procedure for inputting the chip erase command to erase all data from flash memory. I All Data Erase from Flash Memory (Chip Erase) •...
Page 622: Erasing Any Data In Flash Memory (Sector Erasing)
CHAPTER 19 512 KBIT FLASH MEMORY 19.8.4 Erasing Any Data in Flash Memory (Sector Erasing) This section explains the procedure for inputting the sector erase command to erase any data in flash memory. Sector-by-sector erasing is enabled and multiple sectors can be specified at the same time.
Page 623 CHAPTER 19 512 KBIT FLASH MEMORY Figure 19.8-2 Example of Sector Erasing Procedure Start FMCS: WE (bit5) Programming enabled FFWR0/1 Accidental write preventive function setting (Accidental write preventive sector: 0, writing sector :1 ) Erase command sequence (1) FFAAAA XXAA (2) FF5554 XX55 (3) FFAAAA...
Page 624: Sector Erase Suspension
CHAPTER 19 512 KBIT FLASH MEMORY 19.8.5 Sector Erase Suspension This section explains the procedure for inputting the sector erase suspend command to suspend sector erasing. Data can be read from the sector not being erased. I Sector Erase Suspension •...
Page 625: Sector Erase Resumption
CHAPTER 19 512 KBIT FLASH MEMORY 19.8.6 Sector Erase Resumption This section explains the procedure for inputting the sector erase resume command to resume erasing of the suspended flash memory sector. I Erase Resumption • Suspended sector erasing can be resumed by continuously transmitting the sector erase resume command in the command sequence table from CPU to flash memory.
Page 626 CHAPTER 19 512 KBIT FLASH MEMORY...
Page 627: Chapter 20 Dual Operation Flash
CHAPTER 20 DUAL OPERATION FLASH This chapter describes the functions and operation of Dual Operation Flash. 20.1 Overview of Dual Operation Flash 20.2 Register for Dual Operation Flash 20.3 Operation of Dual Operation Flash...
Page 628: Overview Of Dual Operation Flash
CHAPTER 20 DUAL OPERATION FLASH 20.1 Overview of Dual Operation Flash Dual Operation Flash consists of the upper bank (4K x 4) and lower bank (16K x 2 + 4K x 4), allowing concurrent execution of an erase/program and a read in the two banks, which is not allowed in conventional flash products.
Page 629: Register For Dual Operation Flash
CHAPTER 20 DUAL OPERATION FLASH 20.2 Register for Dual Operation Flash The following register is used for operation of Dual Operation Flash: • Sector switching register (SSR0) I Sector switching register (SSR0) Figure 20.2-1 shows the configuration of the sector switching register (SSR0). Please use byte access for write/read to the sector switching register.
Page 630 CHAPTER 20 DUAL OPERATION FLASH I SEN0 bit access sector map Figure 20.2-2 shows the access sector map based on the SEN0 setting. Figure 20.2-2 The access sector map based on the SEN0 setting CPU address FF0000 SA0:4K SA0:4K FF0FFF FF1000 SA1:4K SA1:4K...
Page 631: Operation Of Dual Operation Flash
CHAPTER 20 DUAL OPERATION FLASH 20.3 Operation of Dual Operation Flash Described below is the operation of Dual Operation Flash. Pay particular attention to the following points when using Dual Operation Flash: • Interrupt occurring when the upper bank is reprogrammed •...
Page 632 CHAPTER 20 DUAL OPERATION FLASH I Operation during Write/Erase • If the interrupt is generated during write/erase to flash memory, the write/erase operation to flash memory is prohibited in interrupt routine. If there are two or more write/erase routines, the next write/erase routine should be execution after the an write/erase routine step-by-step.
Page 633: Appendix
APPENDIX The appendices provide the I/O map and outline of instructions. APPENDIX A Instructions APPENDIX B Register Index APPENDIX C Pin Function Index APPENDIX D Interrupt Vector Index...
Page 634: Appendix A Instructions
APPENDIX APPENDIX A Instructions Appendix A describes the instructions used by the F MC-16LX. A.1 Instruction Types A.2 Addressing A.3 Direct Addressing A.4 Indirect Addressing A.5 Execution Cycle Count A.6 Effective Address Field A.7 How to Read the Instruction List A.8 F2MC-16LX Instruction List A.9 Instruction Map...
Page 635: Instruction Types
APPENDIX A Instructions Instruction Types The F MC-16LX supports 351 types of instructions. I Instruction Types • 41 transfer instructions (byte) • 38 transfer instructions (word or long word). • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) •...
Page 636: Addressing
APPENDIX Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied).When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.Some instructions permit the user to select several types of addressing.
Page 637 APPENDIX A Instructions I Effective Address Field Table A.2-1 Effective Address Field lists the address formats specified by the effective address field. Table A.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts (RL1) correspond to the byte, word, and long None word types in order from the left.
Page 638: Direct Addressing
APPENDIX Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. I Direct addressing Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure A.3-1 Example of immediate addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution 2 2 3 3 4 4 5 5 After execution...
Page 639 APPENDIX A Instructions Figure A.3-2 Example of register direct addressing (This instruction transfers the eight low-order bits of A to the general-purpose MOV R0, A register R0.) Before execution 0 7 1 6 2 5 3 4 Memory space After execution 0 7 1 6 2 5 6 4 Memory space Direct branch addressing (addr16)
Page 640 APPENDIX Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure A.3-4 Example of direct branch addressing (addr24) (This instruction causes an unconditional branch by direct branch 24-bit JMPP 333B20H addressing.)
Page 641 APPENDIX A Instructions Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 642 APPENDIX I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure A.3-8 Example of I/O direct bit addressing (io:bp) (This instruction sets bits by I/O direct bit addressing.) SETB I:0C1H:0...
Page 643 APPENDIX A Instructions Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 644 APPENDIX Table A.3-2 CALLV vector list Instruction Vector address L Vector address H CALLV #0 XXFFFE XXFFFF CALLV #1 XXFFFC XXFFFD CALLV #2 XXFFFA XXFFFB CALLV #3 XXFFF8 XXFFF9 CALLV #4 XXFFF6 XXFFF7 CALLV #5 XXFFF4 XXFFF5 CALLV #6 XXFFF2 XXFFF3 CALLV #7 XXFFF0...
Page 645: Indirect Addressing
APPENDIX A Instructions Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. I Indirect addressing Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 646 APPENDIX Figure A.4-2 Example of register indirect addressing with post increment (@RWj+ j = 0 to 3) (This instruction reads data by register indirect addressing with post MOVW A, @RW1+ increment and stores it in A.) Before execution 0 7 1 6 2 5 3 4 Memory space D 3 0 F...
Page 647 APPENDIX A Instructions Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure A.4-4 Example of long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an...
Page 648 APPENDIX Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general- purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure A.4-6 Example of register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a...
Page 649 APPENDIX A Instructions Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure A.4-8 Configuration of the register list RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. Figure A.4-9 Example of register list (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple...
Page 650 APPENDIX Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure A.4-10 Example of accumulator indirect addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Page 651 APPENDIX A Instructions Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure A.4-12 Example of indirect specification branch addressing (@ear) (This instruction causes an unconditional branch by register indirect addressing.) JMP @@RW0 Before execution 3 C 2 0...
Page 652: Execution Cycle Count
APPENDIX Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, correction value determined by the condition, and the number of cycles for instruction fetch. I Execution Cycle Count In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Page 653 APPENDIX A Instructions Table A.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16- bit even address...
Page 654: Effective Address Field
APPENDIX Effective Address Field Table A.6-1 effective address field. I Effective Address Field Table A.6-1 Effective Address Field (1/2) Byte count of extended address port number Code Representation Address format of byte (RL0) Register direct: Individual parts (RL1) − correspond to the byte, word, and long word types in order from the left.
Page 655 APPENDIX A Instructions Table A.6-1 Effective Address Field (2/2) Byte count of extended address port number Code Representation Address format of byte @RW0+disp16 @RW1+disp16 Register indirect with 16-bit displacement @RW2+disp16 @RW3+disp16 @RW0+RW7 Register indirect with index @RW1+RW7 Register indirect with index @PC+disp16 PC indirect with 16-bit displacement addr16...
Page 656: How To Read The Instruction List
APPENDIX How to Read the Instruction List Table A.7-1 Description of Items in the Instruction List describes the items used in the MC-16LX Instruction List, and Table A.7-2 Explanation on Symbols in the Instruction List describes the symbols used in the same list. I Description of instruction presentation items and symbols Table A.7-1 Description of Items in the Instruction List (1/2) Item...
Page 657 APPENDIX A Instructions Table A.7-1 Description of Items in the Instruction List (2/2) Item Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *:Read Modify Write instruction −...
Page 658 APPENDIX Table A.7-2 Explanation on Symbols in the Instruction List (2/2) Representation Explanation #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16...
Page 659: F 2 Mc-16Lx Instruction List
APPENDIX A Instructions MC-16LX Instruction List The table lists the instructions used by the F MC-16LX family. MC-16LX Instruction List Table A.8-1 41 Transfer instructions (byte) Mnemonic Operation MOV A,dir byte (A) <-- (dir) MOV A,addr16 byte (A) <-- (addr16) MOV A,Ri byte (A) <-- (Ri) MOV A,ear...
Page 660 APPENDIX Table A.8-2 38 Transfer instructions (byte) Mnemonic Operation MOVW A,dir word (A) <-- (dir) MOVW A,addr16 word (A) <-- (addr16) MOVW A,SP word (A) <-- (SP) MOVW A,RWi word (A) <-- (RWi) MOVW A,ear word (A) <-- (ear) MOVW A,eam 3 + (a) word (A) <-- (eam) MOVW A,io...
Page 661 APPENDIX A Instructions Table A.8-3 42 Addition/subtraction instructions (byte, word, long word) Mnemonic Operation A,#imm8 byte (A) <-- (A) + imm8 A,dir byte (A) <-- (A) + (dir) A,ear byte (A) <-- (A) + (ear) A,eam 4 + (a) byte (A) <-- (A) + (eam) ear,A byte (ear) <-- (ear) + (A) eam,A...
Page 662 APPENDIX Table A.8-4 12 Increment/decrement instructions (byte, word, long word) Mnemonic Operation byte (ear) <-- (ear) + 1 5+(a) 2 x (b) byte (eam) <-- (eam) + 1 byte (ear) <-- (ear) - 1 5+(a) 2 x (b) byte (eam) <-- (eam) - 1 INCW word (ear) <-- (ear) + 1 INCW...
Page 663 APPENDIX A Instructions Table A.8-6 11 Unsigned multiplication/division instructions (word, long word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) DIVU A,ear word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) DIVU A,eam word (A) / byte (eam)
Page 664 APPENDIX Table A.8-7 11 Signed multiplication/division instructions (word, long word) Mnemonic Operation word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) A,ear word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) A,eam word (A) / byte (eam) quotient -->...
Page 665 APPENDIX A Instructions Table A.8-8 39 Logic 1 instructions (byte, word) Mnemonic Operation A,#imm8 byte (A) <-- (A) and imm8 A,ear byte (A) <-- (A) and (ear) A,eam 4+(a) byte (A) <-- (A) and (eam) ear,A byte (ear) <-- (ear) and (A) eam,A 5+(a) 2 x (b)
Page 666 APPENDIX Table A.8-9 6 Logic 2 instructions (long word) Mnemonic Operation ANDL A,ear long (A) <-- (A) and (ear) ANDL A,eam 7+(a) long (A) <-- (A) and (eam) A,ear long (A) <-- (A) or (ear) A,eam 7+(a) long (A) <-- (A) or (eam) XORL A,ear long (A) <-- (A) xor (ear)
Page 667 APPENDIX A Instructions Table A.8-12 18 Shift instructions (byte, word, long word) Mnemonic Operation RORC byte (A) <-- With right rotation carry ROLC byte (A) <-- With left rotation carry RORC byte (ear) <-- With right rotation carry RORC 5+(a) 2 x (b) byte (eam) <-- With right rotation carry ROLC...
Page 668 APPENDIX Table A.8-13 31 Branch 1 instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/BNE Branch on (Z) = 0 BC/BLO Branch on (C) = 1 BNC/BHS Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0 Branch on (T) = 1...
Page 669 APPENDIX A Instructions Table A.8-14 19 Branch 2 instructions Mnemonic Operation S T N Z V C R CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9...
Page 670 APPENDIX Table A.8-15 28 Other control instructions (byte, word, long word) Mnemonic Operation PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (A) PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (AH) PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (PS) PUSHW rlst (SP) <-- (SP) - 2n, ((SP)) <-- (rlst)
Page 671 APPENDIX A Instructions Table A.8-16 21 Bit operand instructions Mnemonic Operation MOVB A,dir:bp byte (A) <-- (dir:bp)b MOVB A,addr16:bp byte (A) <-- (addr16:bp)b MOVB A,io:bp byte (A) <-- (io:bp)b MOVB dir:bp,A 2 x (b) bit (dir:bp)b <-- (A) MOVB addr16:bp,A 2 x (b) bit (addr16:bp)b <-- (A) MOVB...
Page 672 APPENDIX Table A.8-18 10 String instructions Mnemonic Operation MOVS / MOVSI byte transfer @AH+ <-- @AL+, counter = RW0 MOVSD byte transfer @AH- <-- @AL-, counter = RW0 SCEQ / SCEQI byte search @AH+ <-- AL, counter RW0 SCEQD byte search @AH- <-- AL, counter RW0 FILS / FILSI 6m+6 byte fill @AH+ <-- AL, counter RW0...
Page 673: Instruction Map
APPENDIX A Instructions Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. The F MC-16LX instruction map is given below. I Structure of Instruction Map Figure A.9-1 Structure of Instruction Map Basic page map : Byte 1 Character string...
Page 674 APPENDIX Figure A.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction..Instruction code Byte 1 Byte 2 Operand Operand [Basic page map] [Extended page map] (*1) *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 675 APPENDIX A Instructions Table A.9-2 Basic Page Map...
Page 676 APPENDIX Table A.9-3 Bit Operation Instruction Map (first byte = 6C...
Page 677 APPENDIX A Instructions Table A.9-4 Character String Operation Instruction Map (first byte = 6E...
Page 678 APPENDIX Table A.9-5 2-byte Instruction Map (first byte = 6F...
Page 679 APPENDIX A Instructions Table A.9-6 ea Instruction 1 (first byte = 70...
Page 680 APPENDIX Table A.9-7 ea Instruction 2 (first byte = 71...
Page 681 APPENDIX A Instructions Table A.9-8 ea Instruction 3 (first byte = 72...
Page 682 APPENDIX Table A.9-9 ea Instruction 4 (first byte = 73...
Page 683 APPENDIX A Instructions Table A.9-10 ea Instruction 5 (first byte = 74...
Page 684 APPENDIX Table A.9-11 ea Instruction 6 (first byte = 75...
Page 685 APPENDIX A Instructions Table A.9-12 ea Instruction 7 (first byte = 76...
Page 686 APPENDIX Table A.9-13 ea Instruction 8 (first byte = 77...
Page 687 APPENDIX A Instructions Table A.9-14 ea Instruction 9 (first byte = 78...
Page 688 APPENDIX Table A.9-15 MOVEA RWi, ea Instruction (first byte = 79...
Page 689 APPENDIX A Instructions Table A.9-16 MOV Ri, ea Instruction (first byte = 7A...
Page 690 APPENDIX Table A.9-17 MOVW RWi, ea Instruction (first byte = 7B...
Page 691 APPENDIX A Instructions Table A.9-18 MOV ea, Ri Instruction (first byte = 7C...
Page 692 APPENDIX Table A.9-19 MOVW ea, Rwi Instruction (first byte = 7D...
Page 693 APPENDIX A Instructions Table A.9-20 XCH Ri, ea Instruction (first byte = 7E...
Page 694 APPENDIX Table A.9-21 XCHW RWi, ea Instruction (first byte = 7F...
Page 695: Appendix B Register Index
APPENDIX B Register Index APPENDIX B Register Index I Register Index Table B-1 Register Index (1/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 000000 (Reserved area) 000001 XXXXXXXX PDR1 Port 1 data register port 1 000002 XXXXXXXX PDR2...
Page 696 APPENDIX Table B-1 Register Index (2/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 000026 00000000 SMR1 Serial mode register 1 000027 00000100 SCR1 Serial control register 1 UART1 SIDR1/ Serial input data register 1/ 000028 XXXXXXXX SODR1 serial output data register 1...
Page 697 APPENDIX B Register Index Table B-1 Register Index (3/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 000047 (Reserved area) 00004F 000050 XXXXXXXX IPCP0 Input capture data register0 000051 XXXXXXXX 000052 XXXXXXXX IPCP1 Input capture data register1 000053 XXXXXXXX 000054...
Page 698 APPENDIX Table B-1 Register Index (4/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 000080 00000000 BVALR Message buffer validating register (BVALR) CAN controller 000081 (Reserved area) 000082 00000000 TREQR Transmission complete register CAN controller 000083 (Reserved area) 000084 00000000...
Page 699 APPENDIX B Register Index Table B-1 Register Index (5/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 0000AB (Reserved area) 0000AD 512-Kbit flash 0000AE 000X0000 FMCS Flash memory control status register memory 0000AF (Reserved area) 0000B0 00000111 ICR00 Interrupt control register 00...
Page 700 APPENDIX Table B-1 Register Index (6/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion Detect address setting register 0 001FF0 XXXXXXXX (Low) Detect address setting register 0 001FF1 XXXXXXXX PADR0 (Middle) Detect address setting register 0 001FF2 XXXXXXXX (High)
Page 701 APPENDIX B Register Index Table B-1 Register Index (7/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 003918 (Reserved area) 00392F 003930 (Reserved area) 003BFF 003C00 RAM (general-purpose RAM) 003C0F 003C10 XXXXXXXX IDR0 ID register 0 003C13 XXXXXXXX CAN controller...
Page 702 APPENDIX Table B-1 Register Index (8/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 003C18 XXXXXXXX IDR2 ID register 2 003C1B XXXXXXXX 003C1C XXXXXXXX IDR3 ID register 3 003C1F XXXXXXXX 003C20 XXXXXXXX IDR4 ID register 4 003C23 XXXXXXXX 003C24...
Page 703 APPENDIX B Register Index Table B-1 Register Index (9/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 003C40 XXXXXXXX DTR0 Data register 0 003C47 XXXXXXXX 003C48 XXXXXXXX DTR1 Data register 1 003C4F XXXXXXXX 003C50 XXXXXXXX DTR2 Data register 2 003C57 XXXXXXXX...
Page 704 APPENDIX Table B-1 Register Index (10/10) Register Page Address Abbrevia Register Name Reset Value Resource Name Number tion 003D0B (Reserved area) Remote frame receive waiting register 003D0C XXXXXXXX RFWTR CAN controller (RFWTR) 003D0D (Reserved area) Transmission complete interrupt enable 00000000 003D0E TIER CAN controller...
Page 705: Appendix C Pin Function Index
APPENDIX C Pin Function Index APPENDIX C Pin Function Index I Pin Function Index Table C-1 Pin Function Index (1/2) Page Page Number Circuit Number for Number for Pin Name Functional description Type Function Block Explanation Diagram − input pin for A/D converter −...
Page 706 APPENDIX Table C-1 Pin Function Index (2/2) Page Page Number Circuit Number for Number for Pin Name Functional description Type Function Block Explanation Diagram P10 to P13 General-purpose I/O ports 29 to 32 Trigger input pins for input capture channels 0 IN0 to IN3 to 3 General-purpose I/O ports (high current output...
Page 707: Appendix D Interrupt Vector Index
APPENDIX D Interrupt Vector Index APPENDIX D Interrupt Vector Index I Interrupt Vector Index Table D-1 Interrupt Vector Index (1/2) Interrupt Interrupt Control Address in Vector Table Page Number Interrupt Factor Number Address Middle High − − Reset FFFFDC FFFFDD FFFFDE −...
Page 708 APPENDIX Table D-1 Interrupt Vector Index (2/2) Interrupt Interrupt Control Address in Vector Table Page Number Interrupt Factor Number Address Middle High − Reserved FFFF80 FFFF81 FFFF82 0000BA ICR10 − Reserved FFFF7C FFFF7D FFFF7E − Reserved FFFF78 FFFF79 FFFF7A 0000BB ICR11 −...
Page 709 CM44-10127-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-16LX 16 bit Microcontroller MB90895 series Hardware Manual October 2003 the first edition FUJITSU LIMITED Electronic Devices Published Business Promotion Dept. Edited...

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F2mc-16lx

Fujitsu MB90895 Series Hardware Manual

Chapter 1 Overview

Chapter 2 Handling Devices

Chapter 3 Cpu

Chapter 4 I/O Port

CHAPTER 5 Timebase Timer

CHAPTER 6 Watchdog Timer

CHAPTER 7 16-Bit I/O Timer

CHAPTER 8 16-Bit Reload Timer

CHAPTER 9 Watch Timer

CHAPTER 10 8/16-Bit PPG Timer

CHAPTER 11 Delayed Interrupt Generation Module

CHAPTER 12 Dtp/External Interrupt

CHAPTER 13 8/10-Bit A/D Converter

Chapter 14 Uart0

Chapter 15 Uart1

CHAPTER 16 CAN Controller

CHAPTER 17 Address Match Detecting Function

CHAPTER 18 ROM Mirroring Function Selection Module

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