Page 1 FUJITSU SEMICONDUCTOR MICROCONTROLLER MB90420/5 (A) SERIES MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 3 Version/Revision: V1.0 Translation: V1.4 August 2000 ©2000 FUJITSU LIMITED Printed in Japan Circuit diagrams utilizing Fujitsu products are included as a mean of illustrating typical semiconductor applications. Complete information sufficient for construction proposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable.
Page 4: Table Of Contents
CONTENTS Chapter 1 General ........................ 1-1 1.1 Overview of Product ........................1-3 1.2 Features ............................1-4 1.3 Block Diagram..........................1-6 1.4 Package Dimension ........................1-7 1.5 Pin Assignment .......................... 1-9 1.6 Pin Description......................... 1-11 1.7 I/O Circuits ..........................1-14 1.8 Notes on Handling Devices..................... 1-16 Chapter 2 CPU ........................
Page 5 Chapter 4 Clock........................4-1 4.1 Overview of Clock........................4-3 4.2 Block Diagram of Clock Generation Section ................4-5 4.3 Clock Select Register (CKSCR)....................4-7 4.4 Clock Mode..........................4-9 4.5 Oscillation Stabilization Wait Time ..................4-12 4.6 Connection of Oscillator and External Clock ................4-13 Chapter 5 Low-Power Consumption Mode................. 5-1 5.1 Overview of Low-power Consumption Mode ................5-3 5.2 Block Diagram of Low-power Consumption Controller ............5-5 5.3 Low-power Consumption Mode Control Register (LPMCR) ..........5-7...
Page 6 Chapter 7 Mode Setting ....................... 7-1 7.1 Mode Setting ..........................7-3 7.2 Mode Pins (MD2 to MD0) ......................7-4 7.3 Mode Data ........................... 7-5 Chapter 8 I/O Port......................... 8-1 8.1 Overview of I/O Port........................8-3 8.2 Registers and Assignment of Pins Serving as External Pins ..........8-5 8.3 Port 0 ............................
Page 7 9.4 Operation of Watchdog Timer, Time-base Timer, and Watch Timer ........9-11 9.4.1 Operation of Watchdog Timer..................9-12 9.4.2 Operation of Time-base Timer ..................9-14 9.4.3 Operation of Watch Timer ....................9-16 9.5 Precautions at Using Watchdog Timer and Time-base Timer ..........9-17 9.6 Program Examples of Watchdog Timer and Time-base Timer ..........9-19 Chapter 10 16-bit Reload Timer..................
Page 8 12.5 Interrupt of UART ....................... 12-18 12.5.1 Generation of Receive Interrupt and Timing of Flag Set ........12-20 12.5.2 Generation of Transmit Interrupt and Timing of Flag Set........12-21 12.6 Baud Rate of UART ......................12-22 12.6.1 Baud Rate by Dedicated Baud Rate Generator............ 12-24 12.6.2 Baud Rate by Internal Timer (16-bit Reload Timer) ..........
Page 9 Chapter 15 Stepping Motor Controller................15-1 15.1 Outline of Stepping Motor Controller .................15-3 15.2 Stepping Motor Controller Registers..................15-4 15.2.1 PWM Control Register ....................15-5 15.2.2 PWM1&2 Compare Registers ...................15-6 15.2.3 PWM 1&2 Select Registers ..................15-7 15.3 Explanation of Operation of Stepping Motor Controller...........15-8 15.4 Precautions at Using Stepping Motor Controller ............15-10 Chapter 16 DTP/External Interrupt Circuit................
Page 10 19.6 Explanation of 8-/10-bit A/D Converter Operation ............19-16 19.6.1 Conversion Using EI2OS..................19-19 19.6.2 A/D-converted Data Protection Function.............. 19-20 19.7 Precautions at Using 8-/10-bit A/D Converter ..............19-22 19.8 Sample Program 1 for 8-/10-bit A/D Converter (EI OS Start in Single-shot Mode) ..19-23 19.9 Sample Program 2 for 8-/10-bit A/D Converter (EI OS Start in Continuous Mode) ..
Page 11 23.6.11 Transmission Cancel Register (TCANR) ...............23-21 23.6.12 Transmission Complete Register (TCR)..............23-22 23.6.13 Transmission Interrupt Enable Register (TIER)............23-22 23.6.14 Reception Complete Register (RCR) ..............23-23 23.6.15 Remote Request Receive Register (RRTRR) ............23-23 23.6.16 Receive Overrun Register (ROVRR) ..............23-24 23.6.17 Reception Interrupt Enable Register (RIER) ............23-24 23.6.18 Acceptance Mask Select Register (AMSR) ............23-25 23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ........23-26 23.6.20 Message Buffers ......................23-27...
Page 12 25.7 Details of Programming to and Erasing from Flash Memory ........25-16 25.7.1 Read/reset State in Flash Memory ................ 25-16 25.7.2 Data Programming to Flash Memory ..............25-17 25.7.3 All Data Erasing from Flash Memory (Chip Erase) ..........25-19 25.7.4 Erasing any Data in Flash Memory (Sector Erase)..........
Page 13 Figures Fig. 1.1 Block Diagram .........................1-6 Fig. 1.2 Package Dimension (QFP100) ..................1-7 Fig. 1.3 Package Dimension (LQFP100) ..................1-8 Fig. 1.4 Pin Assignment (QFP100) ....................1-9 Fig. 1.5 Pin Assignment (LQFP100) ..................1-10 Fig. 1.6 Example of using external clock .................1-17 Fig. 1.7 Power Input Pins (V ) ...................1-17 Fig.
Page 14 Fig. 3.1 Oscillation Stabilization Wait Time of Evaluation Products/Flash and Mask Products at Power-on Reset ................3-5 Fig. 3.2 Oscillation Stabilization Wait Time of Evaluation Products/Flash and Mask Products at Power-on Reset ................3-6 Fig. 3.3 Block Diagram of Internal Reset ................... 3-7 Fig.
Page 15 Fig. 6.19 Use Procedure for EI2OS .....................6-30 Fig. 6.20 Stack Operation at Starting Interrupt Handling ............6-34 Fig. 6.21 Stack Area........................6-35 Fig. 7.1 Classification of Mode ....................7-3 Fig. 7.2 Configuration of Mode Data ...................7-5 Fig. 7.3 Relationship betw een Access Areas and P hysical Addresses in Single-chip M ode .7-6 Fig.
Page 16 Fig. 11.1 Block Diagram ......................11-4 Fig. 11.2 Capture Timing Example for Input Capture ............11-14 Fig. 11.3 Capture Timing for Input Signal ................11-14 Fig. 11.4 Clearing Counter by Overflow................... 11-15 Fig. 11.5 Clearing Counter when Value of 16-bit Free-run Timer Matches Value of Compare Clear Register ................
Page 17 Fig. 14.8 Registers Related to LCD Controller/Driver .............14-12 Fig. 14.9 LCDC Control Register Lower (LCRL) ..............14-13 Fig. 14.10 LCDC Control Register Higher (LCRH) ..............14-15 Fig. 14.11 Correspondence between Display RAM and Common/Segment Output Pins ..14-16 Fig. 14.12 Setting of LCD Controller/Driver................14-18 Fig.
Page 18 Fig. 20.1 Block Diagram of Sound Generator ................20-3 Fig. 20.2 Relationship between Tone Signal and Register Value ........... 20-7 Fig. 20.3 Relationship between Register Value and PWM Pulse ..........20-8 Fig. 21.1 Block Diagram of ROM Correction ................21-3 Fig.
Page 19 Tables Table 1-1 Overview of MB90420/5 (A) Series................1-3 Table 1-2 Features of MB90420/5 (A) Series................1-4 Table 1-3 Pin Description ......................1-11 Table 1-4 I/O Circuits .........................1-14 Table 2-1 Access Space for Each Bank Register and Major Use of Access Space ....2-9 Table 2-2 Addressing and Default Spaces ................2-10...
Page 20 Table 8-1 List of Each Port Functions ..................8-4 Table 8-2 Registers for Each Port....................8-5 Table 8-3 Pins of Port 0....................... 8-6 Table 8-4 Correspondence between Registers and Pins for Port 0 ........8-7 Table 8-5 Function of Registers for Port 0................8-8 Table 8-6 State of Port 0 Pins....................
Page 21 Table 9-6 Time-base Timer Counter Clear and Oscillation Stabilization Wait Time....9-15 Table 10-1 Operation Mode of 16-bit Reload Timer ..............10-3 Table 10-2 Interval Time of 16-bit Reload Timer ...............10-4 Table 10-3 16-bit Reload Timer Interrupt and EI2OS ..............10-4 Table 10-4 Pins of 16-bit Reload Timer ..................10-7 Table 10-5 Function of Each Bit of Timer Control Status Register (upper)
Page 22 Table 25-12 State Transition of Sector Erase Timer Flag (State change at abnormal operation) ..............25-15 Table 26-1 Pins Used for Fujitsu Standard Serial Onboard Writing........26-3 Table 26-2 Flash Microcontroller Programmer System Configuration (Manufactured by Yokogawa Digital Computer Ltd.)..........26-4...
Page 23 1. GENERAL 1.1 Overview of Product ............1-3 1.2 Features................1-4 1.3 Block Diagram..............1-6 1.4 Package Dimension ............1-7 1.5 Pin Assignment ..............1-9 1.6 Pin Description ..............1-11 1.7 I/O Circuits ............... 1-14 1.8 Notes on Handling Devices ..........1-16...
Page 24 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 25: Overview Of Product
The MB90420/5 (A) series is a member of the F MC-16LX family microcontrollers. 1.1 Overview of Product Table 1-1 shows a product overview of the MB90420/5 (A) series. n Overview of product Table 1-1 Overview of MB90420/5 (A) Series Feature...
Page 26: Features
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 1.2 Features Table 1-2 shows features of the MB90420/5 (A) series. n Features Table 1-2 Features of MB90420/5 (A) Series Function Feature UART (2 ch) Full-duplicate double-buffer system Supports asynchronous/synchronous transfer (with start/stop bit)
Page 27 GENERAL (Continued) Function Feature Low voltage Automatic reset at low voltage detection detection reset CPU Operation detection function I/O port Push-pull output and Schmitt trigger input Can be programmed in bit units as I/O or resource signal Flash memory Supports automatic programming, Embedded Algorithm™ , and program/erase/erase suspend/erase restart commands Flag indicates completion of algorithm...
Page 28: Block Diagram
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 1.3 Block Diagram Figure 1.1 shows the block diagram of the MB90420/5 (A) series. n Block diagram* X0,X1 X0A,X1A Clock controller MC-16LX core RSTX Interrupt controller Low voltage detection reset...
Page 29: Package Dimension
GENERAL 1.4 Package Dimension Figures 1.2 and 1.3 show the package dimensions of the MB90420/5 (A) series. n Package dimension FPT-100P-M06 EIAJ code: *QFP100-P-1420-4 Plastic QFP, 100 pins Lead pitch 0.65 mm Package width × 14 × 20 mm package length...
Page 30: Fig. 1.3 Package Dimension (Lqfp100)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Package dimension FPT-100P-M05 EIAJ code: *QFP100-P-1414-1 Plastic LQFP, 100 pins Lead pitch 0.50 mm Package width × 14 × 14 mm package length Lead shape Gull-wing Sealing type Plastic mold...
Page 31: Pin Assignment
GENERAL 1.5 Pin Assignment Figures 1.4 and 1.5 show the pin assignment of the MB90420/5 (A) series. n Pin assignment COM2 COM3 SEG0 P57/SGA SEG1 RSTX SEG2 P56/SGO SEG3 P55(/RX0) SEG4 P54(/TX0) SEG5 SEG6 P87/PWM2M3 MB90420/5(A) series SEG7 P86/PWM2P3 P85/PWM1M3...
Page 32: Fig. 1.5 Pin Assignment (Lqfp100)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Pin assignment RSTX SEG0 P56/SGO SEG1 P55(/RX0) SEG2 P54(/TX0) SEG3 SEG4 P87/PWM2M3 SEG5 P86/PWM2P3 SEG6 P85/PWM1M3 SEG7 P84/PWM1P3 MB90420/5(A) series SEG8 TOP VIEW P83/PWM2M2 SEG9 P82/PWM2P2 SEG10 P81/PWM1M2 SEG11...
Page 33: Pin Description
GENERAL 1.6 Pin Description Table 1-3 shows the pin description of the MB90420/5 (A) series. Table 1-3 Pin Description Pin No. Circuit Pin Name Explanation of Function Type LQFP High-speed oscillation input pin High-speed oscillation output pin Low-speed oscillation input pin...
Page 34 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL (Continued) Pin No. Circuit Pin Name Explanation of Function Type LQFP 99 to COM0 to 97 to 100 100, LCD Controller/driver common output pin COM3 1 to 2 1 to 8,...
Page 35 GENERAL (Continued) Pin No. Circuit Pin Name Explanation of Function Type LQFP General-purpose I/O port (TX01 CAN Interface 0 TX output pin General-purpose I/O port (RX0 CAN Interface 0 RX input pin General-purpose I/O port Sound generator SG0 output pin General-purpose I/O port Sound generator SGA output pin 28 to 31...
Page 36: I/O Circuits
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 1.7 I/O Circuits Table 1-4 gives the I/O circuits. n I/O Circuits Table 1-4 I/O Circuits Classification Circuit Remarks • Oscillation feedback resistor; about 1 MΩ Standby control signal • Has pull-up resistor; about 50 kΩ...
Page 37 GENERAL (Continued) Classification Circuit Remarks • CMOS Output • LCDC Output • Hysteresis input LCDC Output Hysteresis input • CMOS Output • Hysteresis input • Analog input Analog input Hysteresis input • CMOS Output • Hysteresis input Hysteresis input • CMOS High current output •...
Page 38: Notes On Handling Devices
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 1.8 Notes on Handling Devices When handling the devices, pay much attention to the following items: • Conformance with maximum rated voltage (to prevent latch up) • Stability of voltage supply •...
Page 39: Fig. 1.6 Example Of Using External Clock
GENERAL • When using external clock Even when an external clock is used, the oscillation stabilization wait time is required at the power-on reset sub-clock mode or the cancellation of the stop mode. Also, as shown in Figure 1.6, when using the external clock, drive the X0 pin only and leave the X1 pin open.
Page 40: Fig. 1.8 Undefined-Value Output Timing Chart
(Simultaneous application and disconnection of analog power and digital power is allowed). • Pull-up/-down resistor The MB90420/5 (A) series does not support internal pull-up/-down resistors. Use external components if necessary. • Output of undefined values from port at power-on reset At a power-on reset after power-on, undefined values are output from port 0/1.
Page 41: Chapter 2 Cpu
2. CPU 2.1 CPU ................... 2-3 2.2 Memory Space ..............2-4 2.3 Memory Map ..............2-6 2.4 Addressing ................. 2-7 2.5 Allocation of Multi-byte Length Data on Memory....2-11 2.6 Register................2-13 2.7 Dedicated Registers ............2-14 2.8 General-purpose Register ..........2-28 2.9 Prefix Codes..............
Page 42 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 43: Cpu
Adoption of system stack pointer, symmetrical instruction set, and barrel shift instruction • Improved execution speed: 4-byte queue Note: Since only single-chip mode is used for the MB90420/5 (A) series, access is limited only to internal ROM space, internal RAM space, and internal resource space.
Page 44: Memory Space
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.2 Memory Space The memory space of the F MC-16LX is 16 Mbytes and stores I/O, programs, and data. Part of the memory space is used for specific uses such as the expansion intelligent I/O service (EI OS) descriptors, the general- purpose registers, and the vector tables.
Page 45 n ROM Area • Vector table area (address: FFFC00 to FFFFFF – This area is used as the vector tables for vector call instructions, interrupt vectors, and reset vectors. – This area is allocated at the top of the ROM area. The starting address of the corresponding processing routine is set to the address of each vector table as data.
Page 46: Memory Map
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.3 Memory Map The MB90420/5 (A) series memory map is shown by the product. n Memory map Figure 2.2 shows the memory map for the MB90420/5 (A) series. Single-chip mode...
Page 47: Addressing
2.4 Addressing Address generation has two types: linear and bank. In the linear type, the entire 24-bit address is specified directly by an instruction. In the bank type, the upper 8-bit address is specified using the bank register according to the use and the lower 16-bit address is specified by an instruction.
Page 48: Linear Type Addressing
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.4.1 Linear Type Addressing The linear has two addressing types as follows. One is the type in which the 24-bit address is specified directly by the operand, and the other is the type in which lower 24 bits of 32-bit general-purpose register are used for the address.
Page 49: Bank Type Addressing
2.4.2 Bank Type Addressing At bank type addressing, the 16-Mbyte memory space is divided into 256 banks of 64 Kbytes each; the upper 8-bit address is determined by specifying the bank address corresponding to each space at the bank register, and the lower 16-bit address is specified by an instruction. Bank register has following 5 types depending on the use.
Page 50: Fig. 2.6 Example Of Bank Type Addressing
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Figure 2.6 shows the relationships between the memory space divided into banks and each register. For details, see Section 2.7.9. FFFFFF Program space FF0000 : PCB (Program bank register) 0FFFFF...
Page 51: Allocation Of Multi-Byte Length Data On Memory
2.5 Allocation of Multi-byte Length Data on Memory Multi-byte length data is written sequentially to memory starting the lower address. For 32-bit length data, the lower 16 bits are transferred first, and then the upper 16 bits are transferred. If a reset signal is input immediately after the lower data is written, the upper data may not be written.
Page 52: Fig. 2.9 Storage Of Multi-Byte Length Data In Stack
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Storage of multi-byte data in stack Figure 2.9 shows the configuration of multi-byte length data in the stack. PUSHW RW1, RW3 PUSHW RW1, (35A4 (6DF0 Address n RW1 : 35A4...
Page 53: Register
2.6 Register The F MC-16LX has two types of registers: dedicated registers in the CPU and general-purpose registers in the internal RAM. n Dedicated registers and general-purpose register The dedicated registers are dedicated hardware in the CPU, and the use is limited by the CPU architecture. The general-purpose register coexists with RAM in the CPU address space.
Page 54: Dedicated Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.7 Dedicated Registers The CPU has following 11 dedicated registers. • Accumulator (A) • User stack pointer (USP) • System stack pointer (SSP) • Processor status (PS) • Program counter (PC) •...
Page 55: Table 2-3 Initial Values Of Dedicated Registers
Table 2-3 Initial Values of Dedicated Registers Dedicated Register Initial Value Accumulator (A) Undefined User stack pointer (USP) Undefined System stack pointer (SSP) Undefined Processor status (PS) bit 15 to bit 13 bit 12 bit 8 bit 7 bit 0 —...
Page 56: Accumulator (A)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.7.1 Accumulator (A) An accumulator (A) consists of two 16-bit length operation registers (AH and AL) used for temporary storage of the operation result or data. The A register can be used as a 32-, 16-, or 8-bit register. Various operations can be performed between the A register and memory or the other register, or between the AH register and the AL register.
Page 57: Fig. 2.14 Example Of Transfer Between Al And Ah Of Accumulator (A) (8-Bit Immediate Value, Zero-Extended)
• Byte processing arithmetic operation of accumulator When the arithmetic operation instruction for byte processing is executed for the AL register, the upper 8 bits of the pre-operation AL register are ignored, and the upper 8 bits of the operation result become all 0s. •...
Page 58: Fig. 2.16 Example Of 32-Bit Data Transfer To Accumulator (A) (Register Indirect)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL MOVL A, @RW1+6 (This instruction performs long-word length reading using the result obtained by adding the 8- bit length offset to data of RW1, and then stores the read value in the A register.)
Page 59: Stack Pointer (Usp, Ssp)
2.7.2 Stack Pointer (USP, SSP) There are two stack pointers: user stack pointer (USP), and system stack pointer (SSP). Both indicate the data save destination memory address or the return destination memory address when executing the PUSH instruction, the POP instruction, or a subroutine. The upper 8 bits of the stack address are specified using the user stack bank register (USB) or the system stack bank register (SSB).
Page 60: Fig. 2.18 Stack Operation Instructions And Stack Pointers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Figure 2.18 shows an example of the stack operation using the system stack. PUSHW A when S flag = 0 Before execution C6F326 A624 F328 S flag 1234 After execution...
Page 61: Processor Status (Ps)
2.7.3 Processor Status (PS) The processor status (PS) consists of the bits controlling CPU and various bits indicating the CPU status. The PS register consists of the following three registers. • Interrupt level mask register (ILM) • Register bank pointer (RP) •...
Page 62: Condition Code Register (Ps: Ccr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.7.4 Condition Code Register (PS: CCR) The condition code register (PS: CCR) is an 8-bit register consisting of bits indicating the operation result and the transfer data, and the bits controlling acceptance of the interrupt request.
Page 63: Register Bank Pointer (Ps: Rp)
2.7.5 Register Bank Pointer (PS: RP) The register bank pointer (RP) indicates the starting address of the currently used general-purpose register bank, and is used for the real address conversion at general-purpose register addressing. n Register bank pointer (RP) Figure 2.21 shows the configuration of the register bank pointer (RP) register. Initial value bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9...
Page 64: Interrupt Level Mask Register (Ps: Ilm)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.7.6 Interrupt Level Mask Register (PS: ILM) The interrupt level mask register (ILM) is a 3-bit register to indicate the level of the interrupt accepted by the CPU. n Interrupt level mask register (ILM) Figure 2.23 shows the configuration of the interrupt level mask register (ILM).
Page 65: Program Counter (Pc)
2.7.7 Program Counter (PC) The program counter (PC) is a 16-bit counter to indicate the lower 16 bits of the memory address for the next instruction code executed by the CPU. n Program counter (PC) The upper 8 bits of the address storing the next instruction code executed by the CPU are specified for the program bank register (PCB), and the lower 16 bits of that address are specified for PC.
Page 66: Direct Page Register (Dpr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.7.8 Direct Page Register (DPR) The direct page register (DPR) is an 8-bit register to specify bit 8 to bit 15 (address 8 to address 15) of the operand address when executing the instruction using the abbreviated direct addressing.
Page 67: Bank Register (Pcb, Dtb, Usb, Ssb, And Adb)
. The PCB can be read but cannot be written. Bank registers other than the PCB can be both read and written. Note: The MB90420/5 (A) series supports up to the memory space contained in the device. For the operation of each register, see Section 2.4.2. 2-27...
Page 68: General-Purpose Register
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.8 General-purpose Register The general-purpose register is a memory block allocated to RAM addresses 000180 to 00037F in register banks units of 16 bits × 8. A register bank can be used as a general-purpose 8-bit register (byte registers R0 to R7), 16-bit register (word registers RW0 to RW7), or 32-bit register (long word registers RL0 to RL7).
Page 69: Table 2-6 Typical Function Of The General-Purpose Register
n Register bank The register bank can be used as a general-purpose register (byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3) to perform various operations or to serve as a pointer. The long word register can also be used as a linear pointer to directly access the entire memory space.
Page 70: Prefix Codes
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.9 Prefix Codes When an instruction is prefixed by a code, the operation of the instruction can be changed partially. Following three types of prefix code are available: • Bank select prefix (PCB, DTB, ADB, and SPB) •...
Page 71: Bank Select Prefix (Pcb, Dtb, Adb, And Spb)
2.9.1 Bank Select Prefix (PCB, DTB, ADB, and SPB) When an instruction is prefixed by the bank select prefix, the memory space accessed by the instruction can be selected arbitrarily irrespective of the addressing type. n Bank select prefix (PCB, DTB, ADB, SPB) The memory space used when accessing data is defined for each addressing type.
Page 72: Common Register Bank Prefix (Cmr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 2-9 Instructions Requiring Care When Using Bank Select Prefix Instruction Type Instruction Explanation Flag change instruction CCR, #imm8 The prefix affects up to the next instruction. CCR, #imm8 ILM Setting instruction ILM, #imm8 The prefix affects up to the next instruction.
Page 73: Flag Change Inhibit Prefix (Ncc)
2.9.3 Flag Change Inhibit Prefix (NCC) When the flag change inhibit instruction is prefixed by the NCC, the flag change caused by execution of the instruction can be inhibited. n Flag change inhibit prefix To inhibit unnecessary flag change, use the flag change inhibit prefix code (NCC). When the flag change inhibit instruction is prefixed by the NCC, the flag change caused by execution of the instruction can be inhibited.
Page 74: Restrictions On Prefix Code
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2.9.4 Restrictions on Prefix Code The prefix code has the following three restrictions. • The interrupt/hold request is not accepted during the prefix code or the interrupt/hold inhibit instruction. • When the interrupt/hold instruction is prefixed by the prefix code, the effect of the prefix code is delayed.
Page 75: Fig. 2.29 Interrupt/Hold Inhibition Instruction And Prefix Code
• Delay of the effect of the prefix code As shown in Figure 2.29, when the interrupt/hold inhibit instruction is prefixed by the prefix code, the effect of the prefix code is effective for the first instruction after the interrupt/hold inhibit instruction. Interrupt/hold inhibit instruction •...
Page 76 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 2-36...
Page 77: Chapter 3 Reset
3. RESET 3.1 Overview of Reset .............. 3-3 3.2 Reset Factors and Oscillation Stabilization Wait Time ..3-5 3.3 External Reset Pin.............. 3-7 3.4 Reset Operation ..............3-8 3.5 Reset Factor Bit ............... 3-10 3.6 State of Each Pin at Reset ..........3-12...
Page 78 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 79: Overview Of Reset
RESET This chapter explains the reset. 3.1 Overview of Reset When a reset factor occurs, the CPU immediately suspends the current processing and waits until reset is canceled. After the reset is canceled, processing is started at the address indicated by the reset vector. 6 reset factors are shown below.
Page 80 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Software reset A software reset generates an internal reset when “0” is written to the RST bit of the low-power consumption mode control register (LPMCR). A software reset does not require the oscillation stabilization wait time.
Page 81: Reset Factors And Oscillation Stabilization Wait Time
RESET 3.2 Reset Factors and Oscillation Stabilization Wait Time The MB90420 (A)/425 (A) series has 6 reset factors. The oscillation stabilization wait time at a reset depends on the reset factors. n Reset sources and oscillation stabilization wait time Table 3-2 and Figure 3-1 show the oscillation stabilization wait times at power-on reset. /HCLK /HCLK CPU Operation...
Page 82: Table 3-3 Oscillation Stabilization Wait Time Based On Setting Of Clock Selection Register (Ckscr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL /HCLK /HCLK CPU Operation Voltage-lowering Oscillation circuit stabilization stabilization wait wait time time HCLK: Oscillation clock Fig. 3.2 Oscillation Stabilization Wait Time of Evaluation Products/Flash and Mask Products at Power-on Reset...
Page 83: External Reset Pin
RESET 3.3 External Reset Pin The external reset pin (RSTX pin) is a reset dedicated pin which generates the internal reset when the “L” level is input. Only the external pin is reset asynchronously with the CPU operating clock; other pins are reset synchronously with the CPU operating clock.
Page 84: Reset Operation
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 3.4 Reset Operation When a reset is cancelled, the setting of the mode pin selects the read destination of the mode data and reset vector and fetches the mode. This mode fetch determines the CPU operation mode, and the execution starting address after termination of the reset.
Page 85: Fig. 3.6 Transfer Of Reset Vectors And Mode Data
RESET Figure 3.6 shows the transfer of reset vectors and mode data. MC-16LX CPU Core Memory space Mode register FFFFDF Mode data Micro ROM FFFFDE Reset vector bits 23 to 16 Reset sequence FFFFDD Reset vector bits 15 to 8 FFFFDC Reset vector bits 7 to 0 Fig.
Page 86: Reset Factor Bit
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 3.5 Reset Factor Bit The reset factor can be identified by reading the watchdog timer control register (WDTC). n Reset factor bit As shown in the Figure 3.7, each reset factor corresponds with a flip-flop. These data are obtained by reading the watchdog timer control register (WDTC).
Page 87: Fig. 3.8 Configuration Of Reset Factor Bit (Watchdog Timer Control Register)
RESET n Correspondence of reset factor bit and reset factor Figure 3.8 shows the configuration of the reset factor bit of the watchdog timer control register (WDTC), and the Table 3-4 shows the correspondence of the reset bit value and the reset factor. For detail, see Section 7.1.
Page 88: State Of Each Pin At Reset
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 3.6 State of Each Pin at Reset This section explains the state of each pin at reset. n State of pins at reset The state of the pins at reset is determined by the setting of the mode pins (MD2 to MD0 = “011”).
Page 89: Chapter 4 Clock
4. CLOCK 4.1 Overview of Clock .............. 4-3 4.2 Block Diagram of Clock Generation Section ....... 4-5 4.3 Clock Select Register (CKSCR) ......... 4-7 4.4 Clock Mode ................ 4-9 4.5 Oscillation Stabilization Wait Time........4-12 4.6 Connection of Oscillator and External Clock..... 4-13...
Page 90 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 91: Overview Of Clock
CLOCK This chapter explains the clock. 4.1 Overview of Clock The clock generation section controls the operation of the internal clock, which is the operating clock for the CPU and the resources. This internal clock is called the machine clock and one cycle of this clock is called the machine cycle.
Page 92: Fig. 4.1 Clock Supply Map
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Clock supply map Machine clocks generated by the clock generation section are supplied as operating clocks to the CPU and resources. Consequently, the operation of the CPU and resources is affected by switching between the main clock and the PLL clock (clock mode) or by switching the PLL clock multiplier.
Page 93: Block Diagram Of Clock Generation Section
CLOCK 4.2 Block Diagram of Clock Generation Section The clock generation section consists of the following five blocks. • System clock generator • PLL Multiplying circuit • Clock selector • Clock selection register (CKSCR) • Oscillation stabilization wait time selector n Block diagram of clock generator Figure 4.2 gives the block diagram of the clock generation section.
Page 94 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • System clock generation circuit The oscillation clock (HCLK) is generated by the external oscillator. An external clock can also be input. • Sub-clock generation circuit The sub-clock generation circuit generates sub-clocks (SCLK) using the eternal oscillator. External clocks can also be input.
Page 95: Clock Select Register (Ckscr)
CLOCK 4.3 Clock Select Register (CKSCR) The clock select register (CKSCR) switches between the main clock and the PLL clock, selects the oscillation stabilization wait time and the PLL clock multiplication rate. n Configuration of clock select register (CKSCR) Figure 4.3 shows the configuration of the clock select register (CKSCR), and Table 4-1 explains the function of each bit of the register.
Page 96: Table 4-1 Function Of Each Bit Of Clock Select Register (Ckscr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 4-1 Function of Each Bit of Clock Select Register (CKSCR) Bit Name Function • This bit to indicate whether the selected machine clock is the main clock or PLL clock.
Page 97: Clock Mode
CLOCK 4.4 Clock Mode There are two clock modes: Main clock mode, PLL clock mode, and sub-clock mode. n Main clock mode, PLL clock mode and sub-clock mode • Main clock mode The main clock mode uses the 2-divided oscillation clock, as the operating clock for the CPU and resources, to stop the PLL clock.
Page 98 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Note: Even when the MCS bit or SCS bit of the CKSCR is rewritten, the machine clock is not switched immediately. When operating a resource that is dependent on the machine clock, make sure that the machine clock is switched by referencing the MCM bit or SCS bit of the CKSCR.
Page 99: Fig. 4.3 Transition Diagram Of Machine Clock Selection State
CLOCK n Machine clock The PLL clock output from the PLL multiplying circuit, the 2-divided clock of the original oscillation or 4- divided clock of the sub-clock is the machine clock. This machine clock is supplied to the CPU and the resources.
Page 100: Oscillation Stabilization Wait Time
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 4.5 Oscillation Stabilization Wait Time At power-on, canceling stop mode, or switching from the sub-clock to the main clock or to the PLL clock, the oscillation of the oscillation clock is stopped, so the oscillation stabilization wait time is required after oscillation is started.
Page 101: Connection Of Oscillator And External Clock
CLOCK 4.6 Connection of Oscillator and External Clock The MB90420/5 (A) series contains a system clock generator and the clock is generated by connecting an external oscillator. An external clock can also be input. n Connection of oscillator and external clock •...
Page 102 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 4-14...
Page 103: Chapter 5 Low-Power Consumption Mode
5. LOW-POWER CONSUMPTION MODE 5.1 Overview of Low-power Consumption Mode ...... 5-3 5.2 Block Diagram of Low-power Consumption Controller..5-5 5.3 Low-power Consumption Mode Control Register (LPMCR) 5-7 5.4 CPU Intermittent Operation Mode ........5-10 5.5 Standby Mode ..............5-11 5.6 State Transition Diagram..........
Page 104 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 105: Overview Of Low-Power Consumption Mode
LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode. 5.1 Overview of Low-power Consumption Mode The following CPU operation modes are provided by the selection of the operating clock and control of the clock operation. • Clock modes (PLL clock, main clock, and sub-clock modes) •...
Page 106 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Clock mode • PLL Clock mode In PLL clock mode, the CPU and resources operate on a PLL multiplying clock for oscillation clock (HCLK). • Main clock mode In main clock mode, the CPU and resources operate on a 2-divided oscillation clock (HCLK). In this mode, the PLL multiplying circuit stops.
Page 107: Block Diagram Of Low-Power Consumption Controller
LOW-POWER CONSUMPTION MODE 5.2 Block Diagram of Low-power Consumption Controller The low-power consumption controller consists of the following seven blocks. • CPU Intermittent operation selector • Standby controller • CPU Clock controller • Resource clock controller • Pin high-impedance controller •...
Page 108 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • CPU Intermittent operation selector Selects the suspended clock count in CPU intermittent operating mode • Standby controller Controls the CPU clock controller and resource clock controller to transit to or clear low-power consumption mode •...
Page 109: Low-Power Consumption Mode Control Register (Lpmcr)
LOW-POWER CONSUMPTION MODE 5.3 Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) transits/cancels the low-power consumption mode and sets the CPU suspended clock count in the CPU intermittent operation mode. n Low-power consumption mode control register (LPMCR) Figure 5.3 shows the configuration of the low-power consumption mode control register (LPMCR).
Page 110: Table 5-1 Function Of Each Bit Of Low-Power Consumption Mode Control Register (Lpmcr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 5-1 Function of Each Bit of Low-power Consumption Mode Control Register (LPMCR) Bit Name Function • This bit specifies a transition to the time-base timer mode or the stop mode.
Page 111: Table 5-2 Instructions At Transition To Low-Power Consumption Mode
LOW-POWER CONSUMPTION MODE n Access to low-power consumption mode control register With to the low-power consumption mode control register, transition is performed to a low-power consumption mode (stop, sleep, time-base timer or timer mode). Use the instructions listed in Table 5-2 at a transition to a low-power consumption mode.
Page 112: Cpu Intermittent Operation Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 5.4 CPU Intermittent Operation Mode In the CPU intermittent operation mode, the CPU performs the intermittent operation with the external bus and the resources operating fast to reduce power consumption.
Page 113: Standby Mode
LOW-POWER CONSUMPTION MODE 5.5 Standby Mode The standby mode includes the sleep mode (PLL sleep, main sleep and sub-sleep), timer mode, and stop mode. n Operating state in standby mode Table 5.3 shows the operating state in standby mode. Table 5-3 Operating State in Standby Mode Transition Main Sub-...
Page 114: Sleep Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 5.5.1 Sleep Mode The sleep mode stops the CPU operation clock and everything ecept the CPU continues operating. If a transition to the sleep mode is specified using the LPMCR, when the PLL clock mode is already specified, a transition is performed to the PLL sleep mode.
Page 115: Fig. 5.5 Cancellation Of Sleep Mode By Interrupt
LOW-POWER CONSUMPTION MODE n Cancellation of sleep mode The low-power consumption controller cancels the sleep mode at a reset input or a generation of interrupt. • Return by a reset At a reset, sleep mode is initialized to the main clock mode. •...
Page 116: Time-Base Timer Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 5.5.2 Time-base Timer Mode Time-base timer mode stops operations other than the original oscillation, the time-base timer and the watch timer and all functions other than the time-base timer and the watch timer are stopped.
Page 117: Timer Mode
LOW-POWER CONSUMPTION MODE 5.5.3 Timer Mode In the timer mode, functions except the sub-clock and the watch timer stop; almost all the chip functions stop. n Transition to timer mode A transition is performed to the timer mode when 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the sub-clock mode (CKSCR: SCS = 0).
Page 118: Fig. 5.6 Cancellation Of Timer Mode (External Reset)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Figure 5.6 gives a cancellation of timer mode (external reset). Timer mode Oscillation stabilization wait Oscillating Stopped PLL clock Oscillating Main clock CPU clock Stopped Processing Reset sequence Cancellation of reset Cancellation of timer mode Fig.
Page 119: Stop Mode
LOW-POWER CONSUMPTION MODE 5.5.4 Stop Mode Stop mode stops the original oscillation and all functions are stopped. Consequently, data is kept at the lowest power consumption. n Transition to stop mode A transition is performed to the stop mode when 1 is written to the STP bit of the low-power consumption mode control register (LPMCR).
Page 120: Fig. 5.7 Cancellation Of Stop Mode (External Reset)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Figure 5.6 shows the return operation from the stop mode. PST pin Stop mode Oscillation stabilization wait Oscillating Main clock Stopped PLL clock Main clock CPU clock Stopped Processing CPU operation...
Page 121: State Transition Diagram
LOW-POWER CONSUMPTION MODE 5.6 State Transition Diagram The transition diagram of operation state and transition condition of the MB90420/5 (A) series are shown. n State transition diagram External reset, watchdog timer reset, CPU Lowering of power operation detection reset or software reset...
Page 122: Table 5-4 Operation State In Low-Power Consumption Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Operation state in low-power consumption mode Table 5-4 Operation State in Low-power Consumption Mode Time- Operation Main Sub- Clock base Resource Timer State Clock clock Clock Resource Timer Operate...
Page 123: Pin State In Standby Mode, At Reset
LOW-POWER CONSUMPTION MODE 5.7 Pin State in Standby Mode, at Reset The state in the standby mode, at reset is shown by the each memory access mode. n Pin state in single-chip mode Table 5-5 shows each pin state in single chip mode. Table 5-5 Each Pin State in Single Chip Mode Standby Mode Pin Name...
Page 124: Precautions At Using Low-Power Consumption Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 5.8 Precautions at Using Low-power Consumption Mode Precautions at using the low-power consumption mode are shown below. • Transition to standby mode and interrupt • Cancellation of standby mode by interrupt •...
Page 125 LOW-POWER CONSUMPTION MODE n Oscillation stabilization wait time • Oscillation stabilization wait time for oscillation clock In the stop mode, the oscillator for the original oscillation stops, so the oscillation stabilization wait time is required. The oscillation stabilization wait time is taken for the selected time by the WS1 and WS0 bits of the clock select register (CKSCR).
Page 126 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 5-24...
Page 127: Chapter 6 Interrupt
6. INTERRUPT 6.1 Overview of Interrupt ............6-3 6.2 Interrupt Factor and Interrupt Vector........6-5 6.3 Interrupt Control Registers and Resources......6-7 6.4 Hardware Interrupt ............6-13 6.5 Software Interrupt............. 6-21 6.6 EI OS Interrupt ..............6-23 6.7 Exception Handling Interrupt ..........6-33 6.8 Stack Operation for Interrupt Handling ......
Page 128 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 129: Overview Of Interrupt
INTERRUPT This chapter explains the interrupts and the expansion intelligent I/O service (EI OS). 6.1 Overview of Interrupt The F MC-16LX has four interrupt functions for suspending the current processing to transfer control to a program which is defined separately at generation of event. •...
Page 130: Fig. 6.1 General Flow Of Interrupt Operation
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Interrupt Figure 6.1 shows 4 types of interrupt start and return functions process. START Main program Valid hardware interrupt request? Interrupt start/return processing String family* instruction executing EI2OS? Fetch and decode next instruction.
Page 131: Interrupt Factor And Interrupt Vector
INTERRUPT 6.2 Interrupt Factor and Interrupt Vector The F MC-16LX has functions corresponding to 256 types of interrupt factor, and 256 sets of interrupt vector tables are allocated to the most significant addresses. The interrupt vectors are shared by all interrupts. The software interrupt can use all interrupts (INT0 to INT256), but some interrupt vectors are shared by hardware interrupt and exception handling interrupts.
Page 132 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Interrupt factor, interrupt vector, and interrupt control register Table 6-2 shows the relationships between the interrupt factor except software interrupt, and interrupt vector and interrupt control register. Table 6-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register...
Page 133: Interrupt Control Registers And Resources
INTERRUPT 6.3 Interrupt Control Registers and Resources The interrupt control registers (ICR00 to ICR15) exist within the interrupt controller, and correspond to all resources with interrupt functions. The registers control the interrupt and extended intelligent I/O service OS). n Interrupt control register list Table 6-3 lists the resources corresponding to the interrupt control registers.
Page 134: Interrupt Control Register (Icr00 To Icr15)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.3.1 Interrupt Control Register (ICR00 to ICR15) The interrupt control register responds to all resources with interrupt functions and controls processing of interrupt request issuance. Some functions of the register are different at writing and reading.
Page 135: Fig. 6.3 Interrupt Control Register (Icr00 To Icr15) At Reading
INTERRUPT Address Initial value --000111 0000B0 – – 0000BF Interrupt Level Setting Bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) OS Enable Bit The interrupt sequence is started at an interrupt. OS is started at an interrupt. OS Status MSB : Most Significant Bit When EI...
Page 136: Fig. 6.4 Configuration Of Interrupt Control Register (Icr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.3.2 Function of Interrupt Control Register The interrupt control register (ICR00 to ICR15) consists of the following bits with four types of functions. • Interrupt level setting bits (IL2 to IL0) •...
Page 137: Function Of Interrupt Control Register
INTERRUPT n Function of interrupt control register • Interrupt level setting bits (IL2 to IL0) These bits set the interrupt level of the corresponding resource. They are initialized to level 7 (no interrupt) at a reset. Table 6-4 shows the relationships between the interrupt level setting bits and each interrupt level.
Page 138 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • EI OS Channel select bits (ICS3 to ICS0) The EI OS channel is specified using write-only bits. The set value of these bits determines the address of the EI OS descriptor.
Page 139: Hardware Interrupt
INTERRUPT 6.4 Hardware Interrupt The hardware interrupt responds to the interrupt request signals from a resource, suspends the program executed by the CPU and transfers control to the interrupt processing program defined by user. OS and the external interrupt are also executed as a kind of hardware interrupt. n Hardware interrupt •...
Page 140: Fig. 6.5 Hardware Interrupt Request During Writing To The Resource Control Register Area
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Hardware interrupt inhibition No hardware interrupt requests are accepted under following conditions. • Hardware interrupt inhibition during writing to resource control register areas No hardware interrupt requests are accepted during writing to resource control register areas.
Page 141 INTERRUPT 6.4.1 Operation of Hardware Interrupt The operation from the issuance of hardware interrupt request to the completion of interrupt handling is explained below. n Start of hardware interrupt • Operation of resource (interrupt request issuance) The resource with a hardware interrupt request function has an interrupt request flag indicating whether an interrupt request is issued or not and an interrupt enable flag selecting whether an interrupt request to the CPU is enabled or disabled.
Page 142: Operation Of Hardware Interrupt
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Operation of hardware interrupt Figure 6.6 shows the operation from the issuance of hardware interrupt to the completion of interrupt handling. Internal bus PS, PC• • Microcode Check Comparator...
Page 143: Processing At Interrupt Operation
INTERRUPT 6.4.2 Processing at Interrupt Operation When an interrupt request is issued from the resource, the interrupt controller transmits the interrupt level to the CPU. When the CPU is ready to accept the interrupt, the controller suspends the currently executing instruction and executes the interrupt-processing routine or starts the EI OS.
Page 144: Use Procedure For Hardware Interrupt
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.4.3 Use Procedure for Hardware Interrupt Hardware interrupt requires the system stack area, resources, interrupt control registers (ICR), etc., to be set. n Use procedure for hardware interrupt Figure 6.8 shows an example of the use procedure for the hardware interrupt.
Page 145: Multiple Interrupts
INTERRUPT 6.4.4 Multiple Interrupts Multiple hardware interrupts can be performed by setting different interrupt levels in the interrupt level setting bits (IL0 to IL2) of the interrupt control register (ICR) in response to plural interrupt requests from the resource. However, multiple EI OS cannot be started.
Page 146: Hardware Interrupt Handling Time
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.4.5 Hardware Interrupt Handling Time From issuance of the hardware interrupt request to execution of the interrupt-processing routine, it requires the time for the currently executing instruction to be terminated plus the interrupt handling time.
Page 147: Software Interrupt
INTERRUPT 6.5 Software Interrupt The software interrupt is a function for transferring control from the program executed by the CPU to the interrupt processing program defined by user by execution of a software interrupt instruction (INT instruction). The software interrupt is stopped during execution of a software interrupt. n Start of software interrupt •...
Page 148: Fig. 6.11 Operation Of Software Interrupt
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Operation of software interrupt Figure 6.11 shows the operation from generation of the software interrupt to completion of the interrupt handling. Internal bus PS, PC . . . (2) Microcode...
Page 149: Ei Os Interrupt
INTERRUPT 6.6 EI OS Interrupt OS is a function to perform auto data transfer between the resources (I/O) and memory. It generates the hardware interrupt at termination of data transfer. n EI OS is a kind of hardware interrupt. It performs auto data transfer between resources (I/O) and memory. OS performs data exchange with resources (I/O) like DMA (direct memory access) that has been performed conventionally using the interrupt processing program, and automatically branches to the interrupt-processing routine after setting the termination conditions.
Page 150 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Operation of EI Figure 6.12 shows the operation of the EI Memory space By IOA Resource (I/O) I/O register I/O Register Interrupt request By ICS Interrupt control register (ICR)
Page 151: Ei Os Descriptor (Isd)
INTERRUPT 6.6.1 EI OS Descriptor (ISD) in the internal RAM, and consists of 8 bytes × 16 The EI OS descriptor (ISD) is at 000100 to 00017F channels. n Configuration of EI OS descriptor (ISD) ISD consists of 8 bytes × 16 channels, and each ISD is composed as shown in Figure 6.13. correspondence between the channel number and ISD address is as shown in Table 6-10.
Page 152: Each Register Of Ei Os Descriptor (Isd)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.6.2 Each Register of EI OS Descriptor (ISD) The EI OS descriptor (ISD) consists of the following registers. • Data counter (DCT) • I/O Register address pointer (IOA) • EI OS status register (ISCS) •...
Page 153 INTERRUPT n EI OS status register (ISCS) The EI OS status register (ISCS) is 8-bit length and indicates the updating/fixing of the buffer address pointer and the I/O register address pointer, the transfer data format (byte/word), and the transfer direction. Figure 6.16 shows the configuration of ISCS.
Page 154: Fig. 6.17 Configuration Of Buffer Address Pointer (Bap)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Buffer address pointer (BAP) The buffer address pointer (BAP) is a 24-bit register and holds the address used at the next transfer performed by EI OS. Each BAP is independent of each EI...
Page 155: Ei Os Operation
INTERRUPT 6.6.3 EI OS Operation The CPU transfers data when the interrupt request is issued from the resource and starting of EI OS is already set in the corresponding interrupt control register (ICR). After termination of data transfer for the specified count, the hardware interrupt handling is performed automatically.
Page 156: Use Procedure For Ei Os
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.6.4 Use Procedure for EI To use EI OS, the following must be set: system stack area, EI OS descriptor, resources and interrupt control register (ICR). n Use procedure for EI Figure 6.19 shows the EI...
Page 157: Ei Os Handling Time
INTERRUPT 6.6.5 EI OS Handling Time The time required for EI OS handling depends on the following factors. • Setting of EI OS status register (ISCS) • Address (area) indicated by I/O register address pointer (IOA) • Address (area) indicated by buffer address pointer (BAP) •...
Page 158: Table 6-13 Compensation Value (Z) For Interrupt Handling Time
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • At data counter (DCT) count termination (at final data transfer) At EI OS data transfer, since the hardware interrupt is started, the interrupt handling time is added. The OS handling time at count termination is calculated by the following expression.
Page 159: Exception Handling Interrupt
INTERRUPT 6.7 Exception Handling Interrupt In the F MC-16LX, an exception is handled by execution of undefined instruction. The exception handling is basically the same as the interrupt processing. When an exception is detected at the boundary of instructions, exception is handled suspending normal processing. In general, exception handling occurs as a result of an unexpected operation and is recommended to be used only at debugging and starting recovery software.
Page 160: Stack Operation For Interrupt Handling
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.8 Stack Operation for Interrupt Handling When an interrupt is accepted, the values of the dedicated registers are saved automatically in the system stack before branching to the interrupt handling. At interrupt handling termination, the dedicated registers are also returned from the stack automatically.
Page 161: Fig. 6.21 Stack Area
INTERRUPT n Stack operation at returning from interrupt handling When the interrupt return instruction (RETI) is executed at termination of interrupt handling, the values of the dedicated registers are returned from the system stack in the reverse order (PS, PC, PCB, DTB, ADB, DPR, A) of before the start of interrupt handling.
Page 162: Program Example For Interrupt Handling
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 6.9 Program Example for Interrupt Handling An example for interrupt handling program is shown below. n Program example for interrupt handling • Processing specification This is an example for interrupt handling program using external interrupt 0 (INT0).
Page 163 INTERRUPT n Program example for EI OS program (1) The EI OS is started by detecting the H level of the signal input to the INT0 pin. (2) When the H level is input to the INT0 pin, EI OS is started and the data of port 0 is transferred to memory address 3000 (3) The transfer data byte count is 100.
Page 164 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ; - - - - - Interrupt program - - - - - - - - - - - - - - - - - - - - - - - - ;...
Page 165: Chapter 7 Mode Setting
7. MODE SETTING 7.1 Mode Setting ..............7-3 7.2 Mode Pins (MD2 to MD0) ........... 7-4 7.3 Mode Data................7-5...
Page 166 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 167: Mode Setting
(MDx) and value of Mx bit in the mode data. By selecting the operation mode, the normal operation can be started. Note: In the MB90420/5 (A) series, only the single-chip mode is used, so set MD2, MD1, and MD0 to 011, and set M1 and M0 to 00.
Page 168: Mode Pins (Md2 To Md0)
Set MD2 to MD0: 0 = V or 1 = V Note: In the MB90420/5 (A) series, only the single-chip mode is used, so set MD2, MD1, and MD0 to 011, and set M1 and M0 to 00.
Page 169: Mode Data
Table 7-2 Bus Mode Setting Bits and Functions Function Remark Single-chip mode (Setting disabled) Note: In the MB90420/5 (A) series, only the single-chip mode is used, so set MD2, MD1, and MD0 to 011, and set M1 and M0 to 00.
Page 170: Fig. 7.3 Relationship Between Access Areas And Physical Addresses In Single-Chip Mode
Relationships between mode pins and mode data Table 7-3 shows the relationships between mode pins and mode data. Table 7-3 Relationships between Mode Pins and Mode Data Mode Single-chip mode Note: In the MB90420/5 (A) series, only the single-chip mode is used.
Page 171: Chapter 8 I/O Port
8. I/O PORT 8.1 Overview of I/O Port ............8-3 8.2 Registers and Assignment of Pins Serving as External Pins ..............8-5 8.3 Port 0 ................. 8-6 8.4 Port 1 ................8-11 8.5 Port 3 ................8-16 8.6 Port 4 ................8-21 8.7 Port 5 ................
Page 172 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 173: Overview Of I/O Port
This chapter explains the function and operation of the I/O port. 8.1 Overview of I/O Port I/O ports can be used as general-purpose I/O ports (parallel I/O ports). In the MB90420/5 (A) series, there are nine ports (58 pins). Each port pin also serves as a resource I/O pin.
Page 174: Table 8-1 List Of Each Port Functions
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 8-1 List of Each Port Functions Port Input Output Pin Name Function bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1...
Page 175: Registers And Assignment Of Pins Serving As External Pins
I/O PORT 8.2 Registers and Assignment of Pins Serving as External Pins The registers related to I/O port setting are listed as follows. n Registers for I/O ports Table 8-2 lists the registers for each port. Table 8-2 Registers for Each Port Register Name Read/Write Address...
Page 176: Port 0
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.3 Port 0 Port 0 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port. Port 0 is a general-purpose I/O port is mainly explained here.
Page 177: Fig. 8.1 Block Diagram Of Pins Of Port 0
I/O PORT n Block diagram of pins of port 0 Figure 8.1 shows the block diagram of the pins of port 0. Resource input Resource output Resource output enable PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read...
Page 178: Registers For Port 0 (Pdr0, Ddr0)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.3.1 Registers for port 0 (PDR0, DDR0) The registers for port 0 are explained. n Function of registers for port 0 • Port 0 data register (PDR0) The PDR0 register indicates the state of the pins.
Page 179: Operation Of Port 0
I/O PORT 8.3.2 Operation of Port 0 The operation of port 0 is explained. n Operation of port 0 • Operation at output port – When the bit of the corresponding DDR0 register is set to 1, the pin becomes an output port pin. –...
Page 180: Table 8-6 State Of Port 0 Pins
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Page 181: Port 1
I/O PORT 8.4 Port 1 Port 1 is a general-purpose I/O port that serves both as a resource input. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here. The configuration, pins, block diagram of the pins, and registers for port 1 are shown below.
Page 182: Fig. 8.2 Block Diagram Of Pins Of Port 1
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Block diagram of pins of port 1 Figure 8.2 shows the block diagram of the pins of port 1. Resource input Resource output Resource output enable PDR (port data register)
Page 183: Registers For Port 1 (Pdr1, Ddr1)
I/O PORT 8.4.1 Registers for Port 1 (PDR1, DDR1) The registers for port 1 are explained. n Function of registers for port 1 • Port 1 data register (PDR1) The PDR1 register indicates the state of the pins. • Port 1 direction register (DDR1) The DDR1 register sets the I/O direction of the pins for each bit.
Page 184: Operation Of Port 1
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.4.2 Operation of Port 1 The operation of port 1 is explained. n Operation of port 1 • Operation at output port – When the bit of the corresponding DDR1 register is set to 1, the pin becomes an output port pin.
Page 185: Table 8-10 State Of Port 1 Pins
I/O PORT • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR1 register.
Page 186: Port 3
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.5 Port 3 Port 3 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 187: Fig. 8.3 Block Diagram Of Pins Of Port 3
I/O PORT n Block diagram of pins of port 3 Figure 8.3 shows the block diagram of the pins of port 3. Resource output Resource output enable PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read...
Page 188: Registers For Port 3 (Pdr3, Ddr3)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.5.1 Registers for Port 3 (PDR3, DDR3) The registers for port 3 are explained. n Function of registers for port 3 • Data register of port 3 (PDR3) The PDR3 register indicates the state of the pins.
Page 189: Operation Of Port 3
I/O PORT 8.5.2 Operation of Port 3 The operation of port 3 is explained. n Operation of port 3 • Operation at output port – When the bit of the corresponding DDR3 register is set to 1, the pin becomes an output port pin. –...
Page 190: Table 8-14 State Of Port 3 Pins
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCSR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Page 191: Port 4
I/O PORT 8.6 Port 4 Port 4 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 192: Fig. 8.4 Block Diagram Of Pins Of Port 4
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Block diagram of pins of port 4 Figure 8.4 shows the block diagram of the pins of port 4. Resource output Resource output enable PDR (port data register) PDR read...
Page 193: Registers For Port 4 (Pdr4, Ddr4)
I/O PORT 8.6.1 Registers for Port 4 (PDR4, DDR4) The registers for port 4 are explained. n Function of registers for port 4 • Port 4 data register (PDR4) The PDR4 register indicates the state of the pins. • Port 4 direction register (DDR4) The DDR4 register sets the I/O direction of the pins for each bit.
Page 194: Operation Of Port 4
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.6.2 Operation of Port 4 The operation of port 4 is explained. n Operation of port 4 • Operation at output port – When the bit of the corresponding DDR4 register is set to 1, the pin becomes an output port pin.
Page 195: Table 8-18 State Of Port 4 Pins
I/O PORT • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCSR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR4 register.
Page 196: Port 5
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.7 Port 5 Port 5 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 197: Fig. 8.5 Block Diagram Of Pins Of Port 5
I/O PORT n Block diagram of pins of port 5 Figure 8.5 shows the block diagram of the pins of port 5. Resource input Resource output Resource output enable PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read...
Page 198: Registers For Port 5 (Pdr5, Ddr5)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.7.1 Registers for Port 5 (PDR5, DDR5) The registers for port 5 are explained. n Function of port 5 registers • Port 5 data register (PDR5) The PDR5 register indicates the state of the pins.
Page 199: Operation Of Port 5
I/O PORT 8.7.2 Operation of Port 5 The operation of port 5 is explained. n Operation of port 5 • Operation at output port – When the bit of the corresponding DDR5 register is set to 1, the pin becomes an output port pin. –...
Page 200: Table 8-22 State Of Port 5 Pins
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Page 201: Port 6
I/O PORT 8.8 Port 6 Port 6 is a general-purpose I/O port that serves as a A/D converter analog input. Each pin can be switched between the analog input and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 202: Fig. 8.6 Block Diagram Of Pins Of Port 6
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Block diagram of pins of port 6 Figure 8.6 shows the block diagram of the pins of port 6. ADER Analog input PDR (port data register) PDR read Output latch...
Page 203: Registers For Port 6 (Pdr6, Ddr6)
I/O PORT 8.8.1 Registers for Port 6 (PDR6, DDR6, ADER) The registers for port 6 are explained. n Function of port-6 registers • Port 6 data register (PDR6) The PDR6 register indicates the state of the pins. • Port 6 direction register (DDR6) The DDR6 register sets the I/O direction of the pins for each bit.
Page 204: Operation Of Port 6
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.8.2 Operation of Port 6 The operation of port 6 is explained. n Operation of port 6 • Operation at output port – When the bit of the corresponding DDR6 register is set to 1, the pin becomes an output port pin.
Page 205: Table 8-26 State Of Port 6 Pins
I/O PORT • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state. Because the output buffer is set forcibly to OFF.
Page 206: Port 7
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.9 Port 7 Port 7 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 207: Fig. 8.7 Block Diagram Of Pins Of Port 7
I/O PORT n Block diagram of pins of port 7 Figure 8.7 shows the block diagram of the pins of port 7. Resource output Resource output enable PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read...
Page 208: Registers For Port 7 (Pdr7, Ddr7)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.9.1 Registers for Port 7 (PDR7, DDR7) The registers for port 7 are explained. n Function of port-7 registers • Port 7 data register (PDR7) The PDR7 register indicates the state of the pins.
Page 209: Operation Of Port 7
I/O PORT 8.9.2 Operation of Port 7 The operation of port 7 is explained. n Operation of port 7 • Operation at output port – When the bit of the corresponding DDR7 register is set to 1, the pin becomes an output port pin. –...
Page 210: Table 8-30 State Of Port 7 Pins
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCSR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Page 211: Port 8
I/O PORT 8.10 Port 8 Port 8 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 212: Fig. 8.8 Block Diagram Of Pins Of Port 8
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Block diagram of pins of port 8 Figure 8.8 shows the block diagram of the pins of port 8. Resource output Resource output enable PDR (port data register) PDR read...
Page 213: Registers For Port 8 (Pdr8, Ddr8)
I/O PORT 8.10.1 Registers for Port 8 (PDR8, DDR8) The registers for port 8 are explained. n Function of port-8 registers • Port 8 data register (PDR8) The PDR8 register indicates the state of the pins. • Port 8 direction register (DDR8) The DDR8 register sets the I/O direction of the pins for each bit.
Page 214: Operation Of Port 8
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.10.2 Operation of Port 8 The operation of port 8 is explained. n Operation of port 8 • Operation at output port – When the bit of the corresponding DDR8 register is set to 1, the pin becomes an output port pin.
Page 215: Table 8-34 State Of Port 8 Pins
I/O PORT • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCSR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR8 register.
Page 216: Port 9
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.11 Port 9 Port 9 is a general-purpose I/O port that serves both as a resource input and output. Each pin can be switched between the resource and the port by the bit. The function as a general-purpose I/O port is mainly explained here.
Page 217: Fig. 8.9 Block Diagram Of Pins Of Port 9
I/O PORT n Block diagram of pins of port 9 Figure 8.9 shows the block diagram of the pins of port 9. Resource output Resource output enable PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read...
Page 218: Registers For Port 9 (Pdr9, Ddr9)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 8.11.1 Registers for Port 9 (PDR9, DDR9) The registers for port 9 are explained. n Function of port 9 registers • Port 9 data register (PDR9) The PDR9 register indicates the state of the pins.
Page 219: Operation Of Port 9
I/O PORT 8.11.2 Operation of Port 9 The operation of port 9 is explained. n Operation of port 9 • Operation at output port – When the bit of the corresponding DDR9 register is set to 1, the pin becomes an output port pin. –...
Page 220: Table 8-38 State Of Port 9 Pins
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Operation in stop mode or time-base timer mode When the pin state specification bit of the low power consumption mode control register (LPMCSR: SPL) is 1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Page 221: Program Example Using I/O Ports
I/O PORT 8.12 Program Example Using I/O Ports A program example using the I/O ports is shown below. n Program example using I/O ports • Processing specification – All seven-segment (eight-segment when Dp included) LEDs turned on using port 0 and port 1 –...
Page 222 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Cording example PDR0 000000 PDR1 000001 DDR0 000010 DDR1 000011 ;-------------- Main program ---------------------------------------------------- CODE CSEG START: ; Initialized ; PI0 set to L level #XXXXXXXO I:PDR1, #00000000 ; All bits for port 1 pins set to output I:DDR1, #11111111 ;...
Page 223 9. WATCHDOG TIMER/TIME-BASE TIMER/ WATCH TIMER (SUB-CLOCK) 9.1 Overview of Watchdog Timer, Time-base Timer, and Watch Timer ..............9-3 9.2 Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer ..............9-4 9.3 List of Watchdog Timer, Time-base Timer, and Watch Timer Registers ..........9-5 9.4 Operation of Watchdog Timer, Time-base Timer, and Watch Timer ..............
Page 224 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL...
Page 225: Chapter 9 Watchdog Timer/Time-Base Timer/Watch Timer (Sub-Clock)
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) This chapter explains the watchdog timer, time-base timer and watch timer (sub-clock). 9.1 Overview of Watchdog Timer, Time-base Timer, and Watch timer The circuit configuration of the watchdog timer, time-base timer, and watch timer are shown below. •...
Page 226: Block Diagram Of Watchdog Timer, Time-Base Timer, And Watch Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 9.2 Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer The block diagram of the watchdog timer, time-base timer, and watch timer is shown below. n Block diagram of watchdog timer, time-base timer, and watch timer...
Page 227: List Of Watchdog Timer, Time-Base Timer, And Watch Timer Registers
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) 9.3 List of Watchdog Timer, Time-base Timer, and Watch Timer Registers The registers for the watchdog timer, time-base timer, and watch timer are listed below. n List of watchdog timer, time-base timer, and watch timer registers Watchdog control register ←...
Page 228: Watchdog Timer Control Register (Wdtc)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 9.3.1 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) starts and clears the watchdog time, and displays the reset factor. n Watchdog timer control register (WDTC) Watchdog control register ←...
Page 229: Table 9-2 Wt1 And 0 (Interval Time Select Bits)
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) [bits 1, 0] WT1, 0 The WT1 and WT0 bits select the interval time of the watchdog timer. Only the data written at starting the watchdog timer is valid. Data written except at starting the watchdog timer is ignored. These bits are write-only.
Page 230: Time-Base Timer Control Register (Tbtc)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 9.3.2 Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) can control interrupts by the time-base timer and clears the time- base counter. n Time-base timer control register (TBTC) Time-base timer contol register ←...
Page 231: Watch Timer Control Register (Wtc)
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) 9.3.3 Watch timer control register (WTC) The watch timer control register (WTC) selects clock signals, controls interrupts and intervals, and clears the counter. n Watch timer control register (WTC) Clock timer control register ← Bit No. Address: 0000AA WTIE WTC2...
Page 232: Table 9-4 Selection Of Watch Timer Interval
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL [bits 2, 1, 0] WTC2, WTC1, WTC0 WTC2, WTC1, and WTC0 set the interval of watch timer. The setting of interval is given in Table 9-4. Resets initialize these bits to 000. These bits can be both read and written.
Page 233: Operation Of Watchdog Timer, Time-Base Timer, And Watch Timer
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) 9.4 Operation of Watchdog Timer, Time-base Timer, and Watch Timer The operation of the watchdog timer, time-base timer, and watch timer is explained. n Explanation of operation • Watchdog timer The watchdog timer issues a reset request when 0 is not written to the WTE bit of the WDTC register within the predetermined time due to software nullfunction or hardware upset of program.
Page 234: Operation Of Watchdog Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 9.4.1 Operation of Watchdog Timer The watchdog timer issues a reset request when 0 is not written to the WTE bit of the WDTC register within the predetermined time due to software nullfunction or hardware upset of program.
Page 235: Fig. 9.6 Clearing Timing And Watchdog Timer Interval Time
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) n Watchdog timer interval time Figure 9.6 shows the relationship between watchdog timer clearing timing and the watchdog timer interval time. The interval time changes depending on the timing of the watchdog timer clearing, and requires 3.5 to 4.5 times of the count clock cycle.
Page 236: Operation Of Time-Base Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 9.4.2 Operation of Time-base Timer The time-base timer has a timer function for the oscillation stabilization time wait for the clock source of watchdog timer, main clock and PLL clock. It also has the interval interrupt function that generates interrupts at a certain cycle.
Page 237: Table 9-6 Time-Base Timer Counter Clear And Oscillation Stabilization Wait Time
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) n Time-base timer interrupt and EI Table 9-5 shows the time-base timer interrupt and EI Table 9-5 Time-base Timer Interrupt and EI Interrupt-level Register Address of Vector Table Interrupt Register Address Lower Upper Bank Name ×...
Page 238: Operation Of Watch Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 9.4.3 Operation of Watch Timer The watch timer has the timer function for the oscillation stabilization time wait for the clock source of watchdog timer, and sub-clock. It also has the interval interrupt function that generates interrupts at a certain cycle.
Page 239: Precautions At Using Watchdog Timer And Time-Base Timer
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) 9.5 Precautions at Using Watchdog Timer and Time-base Timer The precautions for using the watchdog timer and the effect on the resources by clearing the interrupt request at using time-base timer and by clearing the time-base timer are described below. n Precautions at using watchdog timer •...
Page 240: Fig. 9.7 Operation Of Time-Base Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Operation of time-base timer The operation of the following states is shown in Figure 9.7. • At power-on reset • At transition to sleep mode during operation of interval timer function •...
Page 241: Program Examples Of Watchdog Timer And Time-Base Timer
WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK) 9.6 Program Examples of Watchdog Timer and Time-base Timer Program example of watchdog timer and time-base timer are given below: n Program exapmle of watchdog timer sample program • Processing specification – The watchdog timer is cleared each time in loop of the main program. –...
Page 242 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Program example of time-base timer • Processing specification The 2 /HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly. In this case, the interval time is about 1.0 ms (operation at 4 MHz).
Page 243: Chapter 10 16-Bit Reload Timer
10. 16-BIT RELOAD TIMER 10.1 Overview of 16-bit Reload Timer ........10-3 10.2 Configuration of 16-bit Reload Timer ........ 10-5 10.3 Pins of 16-bit Reload Timer ..........10-7 10.4 Registers for 16-bit Reload Timer........10-8 10.5 Interrupt of 16-bit Reload Timer........10-15 10.6 Operation of 16-bit Reload Timer ........
Page 244 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10-2...
Page 245: Overview Of 16-Bit Reload Timer
16-BIT RELOAD TIMER This chapter explains the functions and the operations of 16-bit reload timer. 10.1 Overview of 16-bit Reload Timer The 16-bit reload timer has two types of clock modes: the internal clock mode which decrements synchronously with three types of internal clocks, and the event count mode which decrements after detecting any edge of the pulse input to the external pin.
Page 246: Table 10-2 Interval Time Of 16-Bit Reload Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Counter operation • Reload mode → FFFF When decrementing causes an underflow (0000 ), the count setting is reloaded and the count continues. An underflow can issue an interrupt request, so the timer can be used as an interval timer.
Page 247: Configuration Of 16-Bit Reload Timer
16-BIT RELOAD TIMER 10.2 Configuration of 16-bit Reload Timer The 16-bit reload timer is composed of the following seven blocks: • Count clock generation circuit • Reload controller • Output controller • Operation controller • 16-bit timer register (TMR0/1L, TMR0/1H) •...
Page 248 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Count clock generation circuit The count clock generation circuit generates the count clock for the 16-bit reload timer from the machine clock or the external input clock. • Reload controller The reload controller controls the reload operation when the timer is started or when an underflow occurs.
Page 249: Pins Of 16-Bit Reload Timer
16-BIT RELOAD TIMER 10.3 Pins of 16-bit Reload Timer Pins of the 16-bit reload timer and a block diagram are explained. n Pins of 16-bit reload timer Pins of the 16-bit reload timer also serve as general-purpose port pins. Table 10-4 shows the function of the pins, I/O type, and setting at using the 16-bit reload timer.
Page 250: Registers For 16-Bit Reload Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.4 Registers for 16-bit Reload Timer The registers for the 16-bit reload timer are shown. n Registers for 16-bit reload timer Figure 10.3 shows the registers for the 16-bit reload timer.
Page 251: Timer Control Status Register (Upper) (Tmcsr0/1H)
16-BIT RELOAD TIMER 10.4.1 Timer Control Status Register (upper) (TMCSR0/1H) Upper bits 11 to 8 and lower bit 7 of the timer control status register (TMCSR0/1) select the operation mode of the 16-bit reload timer and set the operation condition of the 16-bit reload timer. The lower bit 7 (MOD0) is explained here.
Page 252: Table 10-5 Function Of Each Bit Of Timer Control Status Register (Upper) (Tmcsr0, Tmcsr1: H)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 10-5 Function of Each Bit of Timer Control Status Register (upper) (TMCSR0, TMCSR1: H) Bit Name Function • Values at reading are undefined. bit 15 Unused bits • Writing to these bits does not affect operation.
Page 253: Timer Control Status Register (Lower) (Tmcsr0/1L)
16-BIT RELOAD TIMER 10.4.2 Timer Control Status Register (lower) (TMCSR0/1L) Lower 7 bits of the timer control status register (TMCSR0/1) set the operation condition, enable and disable the operation, control interrupt and check the state of the 16-bit reload timer. n Timer control status register (lower) (TMCSR0/1L) Address bit 15...
Page 254: Table 10-6 Function Of Each Bit Of Timer Control Status Register (Lower) (Tmcsr0/1L)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 10-6 Function of Each Bit of Timer Control Status Register (lower) (TMCSR0/1L) Bit Name Function • This bit enables and disables output of the timer output pin. bit 6 OUTE: •...
Page 255: 16-Bit Timer Register (Tmr0/1)
16-BIT RELOAD TIMER 10.4.3 16-bit timer register (TMR0/1) The 16-bit timer register (TMR0/1) can read the count value of the 16-bit decrement counter at any time. n 16-bit timer register (TMR0/1) Figure 10.6 shows the 16-bit timer register (TMR0/1). Initial value Address bit 15 bit 14...
Page 256: 16-Bit Reload Register (Tmrlr0/1L, Tmrlr0/1H)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.4.4 16-bit Reload Register (TMRLR0/1L, TMRLR0/1H) The 16-bit reload register (TMRLR0/1L, TMRLR0/1H) can set the reload value to the 16-bit decrement counter. The value written to this register is loaded into the decrement counter to be decremented.
Page 257: Interrupt Of 16-Bit Reload Timer
16-BIT RELOAD TIMER 10.5 Interrupt of 16-bit Reload Timer The 16-bit reload timer can issue an interrupt request by a counter underflow. Also, the 16-bit reload timer is conforms to the EI n Interrupt of 16-bit reload timer The interrupt control bits and interrupt factors of the 16-bit reload timer are shown in Table 10-7. Table 10-7 Interrupt Control Bits and Interrupt Factors of 16-bit Reload Timer 16-bit Reload Timer Interrupt-request flag bit...
Page 258: Operation Of 16-Bit Reload Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.6 Operation of 16-bit Reload Timer The setting of the 16-bit reload timer and the operation state of the counter are explained. n Setting of 16-bit reload timer • Setting of internal clock mode To operate the 16-bit reload timer as the interval timer, the following setting is required.
Page 259: Fig. 10.10 State Transition Diagram Of Counter
16-BIT RELOAD TIMER n Operation state of counter The counter state is determined by the CNTE bit of the timer control status register (TMCSR0/1L, TMCSR0/1H) and the wait signal of internal signal. The state that can be set includes the stop state (stop state), start trigger wait state (wait state), and operating state (run state).
Page 260: Internal Clock Mode (Reload Mode)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.6.1 Internal Clock Mode (Reload Mode) The 16-bit counter is decremented synchronously with the internal count clock and a counter underflow issues an interrupt request to the CPU. Also, the toggle waveform can be output from the timer output pin.
Page 261: Fig. 10.12 Count Operation In Reload Mode (Operation Of External Trigger)
16-BIT RELOAD TIMER • Operation of external trigger The counter is started when the effective edge (rising, falling, or both edges) is input to the TIN pin. Figure 10.12 shows the operation of the external trigger in the reload mode. Count clock Reload Reload...
Page 262: Internal Clock Mode (One-Shot Mode)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.6.2 Internal Clock Mode (One-shot Mode) The 16-bit counter is decremented synchronously with the internal count clock and a counter underflow issues an interrupt request to the CPU. Also, a rectangular wave indicating counting is in progress can be output from the TOT0/1 pin.
Page 263: Fig. 10.15 Count Operation In One-Shot Mode (Operation Of External Trigger)
16-BIT RELOAD TIMER • Operation of external trigger The counter is started when the effective edge (rising edge, falling edge, or both edges) is input to the TIN0/1 pin. Figure 10.15 shows the operation of the external trigger in the one-shot mode. Count clock Reload Reload...
Page 264: Event Count Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.6.3 Event Count Mode The input edge from the TIN pin is counted and decrement of the 16-bit counter is performed. An interrupt request is issued to the CPU by a counter underflow. Also, toggle waves or rectangular waves can be output from the TOT0/1 pin.
Page 265: Fig. 10.18 Count Operation In One-Shot Mode (Operation Of Event Count Mode)
16-BIT RELOAD TIMER • Operation in one-shot mode → FFFF When the counter value underflows (0000 ), the counter stops at FFFF . An interrupt request is issued at this point when the underflow request flag bit (UF) is 1 and the interrupt request output enable bit (INTE) is 1.
Page 266: Precautions At Using 16-Bit Reload Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 10.7 Precautions at Using 16-bit Reload Timer Precautions at using the 16-bit reload timer are given below. n Precautions at using 16-bit reload timer • Precautions for setting by program –...
Page 267: Program Example Of 16-Bit Reload Timer
16-BIT RELOAD TIMER 10.8 Program Example of 16-bit Reload Timer Program example the 16-bit reload timer operated in the internal clock mode and the event count mode are given below: n Program example of internal clock mode • Processing specification –...
Page 268 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Program example of event counter mode • Processing specification – An interrupt is generated when rising edges of the pulse input to the external event input pin are counted 10000 times by the 16-bit reload timer/counter.
Page 269 11. INPUT CAPTURE 11.1 Overview of Input Capture..........11-3 11.2 Block Diagram of Input Capture........11-4 11.3 List of Input Capture Registers ......... 11-5 11.4 Explanation of Operation ..........11-13...
Page 270 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 11-2...
Page 271: Chapter 11 Input Capture
INPUT CAPTURE This chapter explains the operation of input capture. 11.1 Overview of Input Capture Input capture is composed of one 16-bit free-run timer and four 16-bit input captures. n Configuration • Input capture (× 4) The input capture is composed of the capture register and control register corresponding to four independent external input pins.
Page 272: Block Diagram Of Input Capture
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 11.2 Block Diagram of Input Capture The block diagram of input capture is given below. n Block diagram φ Interrupt #31 (1F MODE IVF IVFE STOP SCLR CLK2 CLK1 CLK0...
Page 273: List Of Input Capture Registers
INPUT CAPTURE 11.3 List of Input Capture Registers The list of registers for the multi-function timer unit is given below. n List of 16-bit free-run timer registers Compare clear register (upper) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8...
Page 274 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n List of input capture registers Input capture data register (upper) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Address: ch0 000061...
Page 275: Detailed Explanation Of Registers For Input Capture
INPUT CAPTURE 11.3.1 Detailed Explanation of Registers for Input Capture Two types of input capture data registers are shown below: • Input capture data register (IPCP0 to IPCP3) • Input capture control register (IPCP) n Input capture data register (IPCP0 to 3) This register holds the value of the 16-bit free-run timer when an effective edge is detected of the corresponding external pin input wave (Perform word access to this register.
Page 276 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL [bits 5, 4] ICE3, ICE2, ICE1, ICE0 These bits enable input capture interrupts. If the interrupt flags (ICP3, ICP2, ICP1 and ICP0) are set when these bits are 1, an input capture interrupt occurs.
Page 277: Detailed Explanation Of Registers For 16-Bit Free-Run Timer
INPUT CAPTURE 11.3.2 Detailed Explanation of Registers for 16-bit Free-run Timer The 16-bit free-run timer has the following three registers: • Data register (TCDT) • Compare clear register (CPCLR) • Timer control status register (TCCS) n Data register (TCDT) Timer data register (upper) bit 15 bit 14 bit 13...
Page 278 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Timer control status register (TCCSH/TCCSL) Timer control status register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Address: 000029 ECKE —...
Page 279 INPUT CAPTURE [bit 7] IVF This bit is the interrupt request flag of the 16-bit free-run timer. This bit is set to 1 when the 16-bit free-run timer overflows. When the interrupt request enable bit (bit 6: IVFE) is set, an interrupt occurs. This bit is cleared by writing 1. Writing 1 has no meaning. 1 can be read by the read-modify-write instruction.
Page 280 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL [bits 2, 1, 0] CLK2, CLK1, CLK0 These bits select the count clock of the 16-bit free-run timer. The clock is changed immediately after writing to these bits, so a performed when the output compare and input capture are in the stop state.
Page 281: Explanation Of Operation
INPUT CAPTURE 11.4 Explanation of Operation The input capture operation is explained. n Operation explanation • 16-bit free-run timer After a reset is canceled, the 16-bit free-run timer starts counting at 0000. This counter value works as the base time of the 16-bit output compare and 16-bit input capture. •...
Page 282: 16-Bit Input Capture
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 11.4.1 16-bit Input Capture When the set effective edge is detected, the 16-bit input capture can write the value of the 16-bit free-run timer into the capture register to generate an interrupt.
Page 283: 16-Bit Free-Run Timer
INPUT CAPTURE 11.4.2 16-bit Free-run Timer After a reset is canceled, the 16-bit free-run timer starts counting at 0000. This counter value works as the base time of the 16-bit output compare and 16-bit input capture. n Operation of 16-bit free-run timer The counter value the is cleared at the following conditions.
Page 284: Fig. 11.6 Clearing Timing Of 16-Bit Free-Run Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Clearing timing of 16-bit free-run timer The clear of counter is performed when matched with a reset, software or compare clear register. The counter clear by a reset or a software is performed concurently with an occurrence of clearing. The counter clear matched with a compare clear register is performed synchronously with count timing.
Page 285: Chapter 12 Uart
12. UART 12.1 Overview of UART............12-3 12.2 Configuration of UART ............. 12-5 12.3 Pin of UART ..............12-8 12.4 Registers for UART ............12-9 12.5 Interrupt of UART ............12-18 12.6 Baud Rate of UART............12-22 12.7 Operation of UART............12-28 12.8 Precautions at Using UART..........
Page 286 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12-2...
Page 287: Overview Of Uart
UART This chapter explains the function and operation of the UART. 12.1 Overview of UART The UART is a general-purpose serial-data communication interface for synchronous or asynchronous communication (start-stop synchronization) with external devices. The UART has both normal bidirectional communication (normal mode) and master/slave mode communication functions (This function is a multiprocessor mode and is supported only by the master side).
Page 288: Table 12-2 Operation Mode Of Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 12-2 Operation Mode of UART Data Length Synchronous/ Operation Mode Length of Stop Bit Asynchronous No Parity With Parity Normal mode 7 or 8 bits Asynchronous 1 bit or 2 bits*...
Page 289: Configuration Of Uart
UART 12.2 Configuration of UART The UART is composed of the following 11 blocks. • Clock selector • Receive controller • Transmit controller • Reception state determining circuit • Receive shift register • Transmit shift register • Mode register (SMR0/1) •...
Page 290: Fig. 12.1 Block Diagram Of Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Block diagram of UART Control bus Receive interrupt signals #39 (28 Transmit clock Dedicated baud <#37 (25 )*> rate generator Receive Clock Transmit interrupt signals 16-bit reload timer clock...
Page 291 UART • Clock selector The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external input clock, and internal clock (clock supplied from 16-bit reload timer). • Receive controller The receive controller is composed of the receive bit counter, start bit detection, and receive parity counter. The receive bit counter counts the receive data, and issues a receive interrupt request when reception of one piece of data is completed according to the set data length.
Page 292: Pin Of Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.3 Pin of UART The function of the UART pins and a block diagram are shown. n Pin UART The pins of UART also serve as general-purpose port pins. Table 12-4 shows the function of the pins, I/O type, and settings required for using the UART.
Page 293: Registers For Uart
UART 12.4 Registers for UART The list of registers for the UART are shown. n List of UART registers Address bit 15 ........... bit 8 bit 7........... bit 0 CH0: 000035 , 34 SCR (control register) SMR (mode register) CH1: 000039 , 38 CH0: 000037 , 36...
Page 294: Control Register (Scr0/1)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.4.1 Control Register (SCR0/1) The control register (SCR0/1) performs the following: setting parity, selecting stop bit length and data length, selecting frame data format in mode 1, clearing receive error flag, and enabling/disabling of transmitting/receiving.
Page 295: Table 12-5 Function Of Each Bit Of Control Register (Scr0/1)
UART Table 12-5 Function of Each Bit of Control Register (SCR0/1) Bit Name Function bit 15 PEN: Bit to select whether to add parity bit (at sending) at serial-data I/O, and whether to detect Parity enable bit parity bit (at receiving) at serial-data I/O Note: Since parity cannot be used in operation mode 1 or 2, always set this bit to 0.
Page 296: Mode Register (Smr0/1)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.4.2 Mode Register (SMR0/1) The mode register (SMR0/1) performs selecting operation mode, selecting baud rate clock, and disabling/enabling of output of serial data and clock to pin. n Mode register (SMR0/1) Address bit 15 ....
Page 297: Table 12-6 Function Of Each Bit Of Mode Register (Smr0/1)
UART Table 12-6 Function of Each Bit of Mode Register (SMR0/1) Bit Name Function • Bits to select the operation mode bit 7 MD1, MD0: bit 6 Operation mode Note: Operation mode 1 (multiprocessor mode) can only be used for the master in selection bits master/slave mode communications.
Page 298: Status Register (Ssr0/1)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.4.3 Status Register (SSR0/1) The status register (SSR0/1) checks the transmission/reception status and error status and enables/disables interrupts. n Status register (SSR0/1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10...
Page 299: Table 12-7 Function Of Each Bit Of Status Register (Ssr0/1)
UART Table 12-7 Function of Each Bit of Status Register (SSR0/1) Bit Name Function • At reception, this bit is set to 1 at a parity error; it is cleared when 0 is written to the bit 15 PE: Parity error flag bit REC bit of the mode register (SMR).
Page 300: Input-Data Register (Sidr0/1) And Output-Data Register (Sodr0/1)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.4.4 Input Data Register (SIDR0/1) and Output Data Register (SODR0/1) The input data register (SIDR0/1) is the receive register for serial data; the output data register (SODR0/1) is the transmit register for serial data. The SIDR0/1 and the SODR0/1 registers are placed at the same address.
Page 301: Communication Prescaler Control Register (Cdcr0/1)
UART 12.4.5 Communication Prescaler Control Register (CDCR0/1) The communication prescaler control register (CDCR0/1) controls the division of the machine clock. n Communication prescaler control register (CDCR0/1) The operation clock for the UART is obtained by dividing the machine clock. The UART is designed to obtain a regular baud rate for various machine clock cycles by this communication prescaler.
Page 302: Interrupt Of Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.5 Interrupt of UART The UART has a receive and a transmit interrupts, and the following factors can issue interrupt requests. • When receive data set in the input data register (SIDR0/1), or at receive error •...
Page 303 UART n Interrupt of UART and EI Table 12-10 Interrupt of UART and EI Interrupt Control Register Vector Table Address Interrupt Interrupt Source Register Address Lower Upper Bank Name ¥ UART1 receive interrupt #37 (25 ICR13 0000BD FFFF68 FFFF69 FFFF6A ∆...
Page 304: Generation Of Receive Interrupt And Timing Of Flag Set
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.5.1 Generation of Receive Interrupt and Timing of Flag Set Interrupts atreceiving include the receive completion (SSR0/1: RDRF), and the receive error (SSR0/1: PE, ORE, FRE). n Generation of receive interrupt and timing of flag set At reception, the receive data is stored in the input data register (SIDR0/1) when the stop bit is detected (operation mode is 0 or 1) or when the end bit of the data (D7) is detected (operation mode is 2).
Page 305: Generation Of Transmit Interrupt And Timing Of Flag Set
UART 12.5.2 Generation of Transmit Interrupt and Timing of Flag Set At transmission, the interrupt is generated in the state which the next data can be written to the output data register (SODR0/1). n Generation of transmit interrupt and timing of flag set The transmit data empty flag bit (SSR0/1: TDRE) is set to 1 when data written to the output data register (SODR0/1) is transferred to the transmit shift register and in the state which the next data can be written.
Page 306: Baud Rate Of Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.6 Baud Rate of UART One of the following can be selected as the UART transmitter/receiver clock. • Dedicated baud rate generator • Internal clock (16-bit reload timer) • External clock (clock input to SCK pin) n Selection of UART baud rate The baud rate selector is shown below.
Page 307: Fig. 12.11 Uart Baud Rate Selector
UART SMR0/1: CS2 to CS0 (Clock select bits) Clock selector When 000 to 101 Oscillation dividing circuit [Dedicated baud rate generator] (Aynchronous) Any one of the 1to 32 division ratio is selected. Machine clock φ (Asynchronous) division ratio The internal fixed Prescaler division ratio is selected.
Page 308: Baud Rate By Dedicated Baud Rate Generator
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.6.1 Baud Rate by Dedicated Baud Rate Generator The baud rate that can be set when the output clock of the dedicated baud rate generator is selected as the transfer clock of the UART is shown.
Page 309: Table 12-13 Selection Of Division Ratio To Obtain Asynchronous Baud Rate
UART • Asynchronous transfer clock division ratio The clock division ratio to obtain the asynchronous baud rate is specified by the CS2 to CS0 bits of the mode register (SMR0/1) as shown in Table 12-13. Table 12-13 Selection of Division Ratio to Obtain Asynchronous Baud Rate Asynchronous (start - stop Calculation Expression...
Page 310: Baud Rate By Internal Timer (16-Bit Reload Timer)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.6.2 Baud Rate by Internal Timer (16-bit Reload Timer) The setting when selecting the internal clock supplied from the 16-bit reload timer as the transfer clock of the UART and the baud rate calculation are shown below.
Page 311: Baud Rate By External Clock
UART 12.6.3 Baud Rate by External Clock The setting when selecting the external clock as the transfer clock of the UART and the baud rate calculation are shown below. n Baud rate by external clock To select a baud rate by the external clock, the following three settings are required: •...
Page 312: Operation Of Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.7 Operation of UART The UART provides master/slave mode connection communication function (operation mode 1) in addition to normal bidirectional serial communication function (operation modes 0 and 2). n Operation of UART •...
Page 313: Operation In Asynchronous Mode (Operation Mode 0 Or 1)
UART 12.7.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) When the UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. n Operation in asynchronous mode • Format of transfer data Data transfer always starts with the start bit (L level) the specified data bits length is transfered on an LSB- first and the data transfer ends with the stop bit (H level).
Page 314: Fig. 12.15 Transmit Data When Parity Enabled
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Error detection – In operation mode 0, parity, overrun, and frame errors can be detected. – In operation mode 1, overrun and frame errors can be detected, but parity errors cannot be detected.
Page 315: Operation In Synchronous Mode (Operation Mode 2)
UART 12.7.2 Operation in Synchronous Mode (Operation Mode 2) When the UART is used in operation mode 2 (normal mode), the transfer mode is clock synchronous. n Operation in synchronous mode (operation mode 2) • Format of transfer data In the synchronous mode, 8-bit data is transferred on an LSB-first, and the start and stop bits are not attached.
Page 316 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL [Control register (SCR0/1)] P, SBL, A/D : These bits have no meaning. : 1 (8-bit data) : 0 (The error flags are cleared for initialization.) RXE, TXE : At least one of these bits is 1.
Page 317: Bidirectional Communication Function (Normal Mode)
UART 12.7.3 Bidirectional Communication Function (Normal Mode) In operation modes 0 and 2, normal serial bidirectional communications using 1-to-1 connection can be performed. For operation mode 0, the asynchronous mode is used; for operation mode 2, the synchronous mode is used. n Bidirectional communication function To operate the UART in the normal mode (operation mode 0 or 2), the setting of operation mode1 of UART1 shown in Figure 12.17 is required.
Page 318: Fig. 12.19 Example Of Bidirectional Communication Flow
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Communication procedure When the transmit data is ready, communications start on the transmit side at any timing. When the receive side receives the transmit data, it returns ANS periodically (every byte in this example). Figure 12.19 shows an example of the bidirectional communication flow.
Page 319: Master/Slave Mode Communication Function (Multiprocessor Mode)
UART 12.7.4 Master/Slave Mode Communication Function (Multiprocessor Mode) The UART can perform communications using multi-CPU master/slave moe connection and use operation mode 1. However, it can only be used as the master. n Master/slave moe communication function To operate the UART in multiprocessor mode (operation mode 1), the setting in Figure 12.20 is required. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7...
Page 320: Table 12-16 Selection Of Master/Slave Mode Communication Function
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Selection of function For master/slave mode communication, select the operation mode and the data transfer mode, as shown in Table 12-16. Table 12-16 Selection of Master/Slave Mode Communication Function...
Page 321: Fig. 12.22 Flowchart Of Master/Slave Mode Communications
UART (Master CPU) Start Set operation mode to 1 Set the SIN pin to serial data input Set 1-byte data (address data) that selects the slave CPU to D0 to D7 to transmit (A/D = 1) Set 0 to A/D Reception enabled Communicate with slave CPU Communication...
Page 322: Precautions At Using Uart
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 12.8 Precautions at Using UART Precautions at using the UART are shown below. n Precautions at using UART • Operation enable The control register (SCR0/1) of the UART has the operation enable bits, TXE and RXE to transmit and receive, respectively.
Page 323: Program Example Of Uart
UART 12.9 Program Example of UART Program example of UART is given below. n Program Example of UART • Processing specification Serial transmission/reception is performed using the UART bidirectional communication function (normal mode). – The following settings are made: Operation mode: 0, Data length: 8 bits, Stop-bit length: 2 bits, Parity: –...
Page 324 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ;---------Interrupt program --------------------------------------------- WARI: ; Receive data read A, SIDR ; Receive interrupt request flag cleared CLRB Processing by user ; Return from interrupt RETI CODE ENDS ;---------Vecter setting ----------------------------------------------------------------------...
Page 325: Chapter 13 Ppg Timer
13. PPG TIMER 13.1 Overview of PPG Timer............ 13-3 13.2 Block Diagram of PPG Timer..........13-4 13.3 Registers for PPG Timer ..........13-5 13.4 Operation of PPG Timer ..........13-10...
Page 326 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 13-2...
Page 327: Overview Of Ppg Timer
PPG TIMER This chapter explains the operation of the PPG timer. 13.1 Overview of PPG Timer The PPG timer is composed of prescaler, one 16-bit decrement counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty setting buffer, and pin controller. The PPG timer can output pulses synchronized with an external trigger or software trigger.
Page 328: Block Diagram Of Ppg Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 13.2 Block Diagram of PPG Timer The block diagram of PPG timer is given below. n Block diagram PCSR PDUT Prescaler Load PCNT 1/16 16-bit decrement counter 1/32 Start Borrow...
Page 329: Registers For Ppg Timer
PPG TIMER 13.3 Registers for PPG Timer 13.3.1 List of PPG Timer Registers The PPG timer registers are listed below: n PPG timer register list PPG control status register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 (upper)
Page 330: Detailed Explanation Of Registers For Ppg Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 13.3.2 Detailed Explanation of Registers for PPG Timer The PPG timer has following four registers: • PPG control status register (PCNT0 to PCNT2) • PPG decrement counter register (PDCR0 to PDCR2) •...
Page 331 PPG TIMER [bits 11, 10] CKS1, CKS0: Counter clock select bits These bits select the count clock for the 16-bit decrement counter. They cannot be rewritten during operation. CKS1 CKS0 Cycle φ (Initial value) φ/4 φ/16 φ/64 φ: Machine clock [bit 9] PGMS: PPG output mask select bit When 1 is written to this bit, the PPG output can be masked to 0 or 1 irrespective of the mode setting, cycle setting value, and duty setting.
Page 332 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL [bits 3, 2] IRS1, IRS0: Interrupt factor select bits These bits select the factor for setting bit 4 (IRQF). IRS1 IRS0 Edge Selection Software trigger input or valid trigger input...
Page 333 PPG TIMER n PPG decrement counter register (PDCR) This register can read the values of the 16-bit decrement counter. Access this register using 16-bit data. PPG decrement counter register (upper) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8...
Page 334: Operation Of Ppg Timer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 13.4 Operation of PPG Timer The operation of the PPG timer is explained. 13.4.1 PWM Operation At PWM operation, a continuous pulse can be output from detection of the start trigger. The cycle of the output pulse is controlled by changing the PCSR value and the duty ratio is controlled by changing the PDUT value.
Page 335: One-Shot Operation
PPG TIMER Note: After writing data to PCSR, always write to PDUT. Note: When the external TRG input is selected as the start trigger, input a pulse with the minimum or lager pulse width shown below. Minimum pulse width: 2 machine cycles However, a pulse with a smaller width may still be recognized as a valid pulse.
Page 336: Interrupt Factors And Timing
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 13.4.3 Interrupt Factors and Timing The time from the start trigger is caused to the count value is loaded must be 2.5T at the maximum (T: count clock cycle). Start trigger →...
Page 337: Chapter 14 Lcd Controller/Driver
14. LCD CONTROLLER/DRIVER 14.1 Overview of LCD Controller/Driver........14-3 14.2 Configuration of LCD Controller/Driver ......14-4 14.3 LCD Controller/Driver Pins ..........14-10 14.4 LCD Controller/Driver Registers ........14-12 14.5 LCD Controller/Driver Display RAM........ 14-16 14.6 Explanation of Operation of LCD Controller/Driver ..14-18...
Page 338 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14-2...
Page 339: Overview Of Lcd Controller/Driver
LCD CONTROLLER/DRIVER This chapter explains the function and operation of the LCD controller/driver. 14.1 Overview of LCD Controller/Driver The LCD controller/driver has a 16 × 8-bit display data memory and controls the LCD display using four common outputs and 24 segment outputs. Three different duty outputs can be selected and the LCD panel can be driven directly.
Page 340: Configuration Of Lcd Controller/Driver
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.2 Configuration of LCD Controller/Driver The LCD controller/driver consists of the 8 blocks shown below, and is divided functionally into 2 units: the controller unit that generates segment signals and common signals according to display RAM data, and the driver unit that drives the LCD.
Page 341 LCD CONTROLLER/DRIVER • LCDC control register lower (LCRL) This register controls the LCD drive power, selects display or display blanking, selects the display mode, and selects the LCD clock cycle. • LCDC control register higher (LCRH) This register switches between segment output and the general-purpose port. •...
Page 342: Internal Split Resistors Of Lcd Controller/Driver
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.2.1 Internal Split Resistors of LCD Controller/Driver The power supply voltage for the LCD driver is generated by using external split resistors connected to the V0 to V3 pins or by using internal split resistors.
Page 343: Fig. 14.3 State When Internal Split Resistors Used
LCD CONTROLLER/DRIVER Use of internal split resistors Even when internal split resistors are used, connect an external resistor between Vcc and V . Figure 14.3 gives the state when internal split resistors are used. When setting 1/2 bias, short-circuit the V2 pin and V1 pin. Short- circuited LCD controller...
Page 344: External Split Resistors For Lcd Controller/Driver
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.2.2 External Split Resistors for LCD Controller/Driver The LCD driving voltage is generated by using external split resistors or internal split resistors. Brightness can be adjusted by connecting a variable resistor between Vcc and V3 pins.
Page 345: Fig. 14.6 State When External Split Resistors Used
LCD CONTROLLER/DRIVER Using external split resistors The V0 pin is connected to Vss (GND) via an internal transistor. Consequently, when using external split resistors, the current passing through the resistors at stopping the LCD controller can be cut by connecting the Vss side of the external split resistors to only the V0 pin.
Page 346: Lcd Controller/Driver Pins
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.3 LCD Controller/Driver Pins Pins related to the LCD controller/driver are explained, and the block diagram of the pins is given. Pins related to LCD controller/driver The following pins are related to the LCD controller/driver: four common output pins (COM0 to COM3), 24 segment output pins (SEG0 to SEG23), and four LCD driving power pins (V0 to V3).
Page 347: Fig. 14.7 Block Diagram Of Pins Related To Lcd Controller/Driver
LCD CONTROLLER/DRIVER Block diagram of pins related to LCD controller/driver For pins that can also serve as segment output pins: Common/segment control signal LCD driving voltage (V or V LCRH Setting Reset/operation stop signal LCD driving voltage (V or V Common/segment control signal Stop mode (SPL = 1) or...
Page 348: Lcd Controller/Driver Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.4 LCD Controller/Driver Registers Registers related to the LCD controller/driver are shown. Registers related to LCD controller/driver LCRL (LCDC control register lower) Address Initial value bit 7 bit 6...
Page 349: Lcdc Control Register Lower (Lcrl)
LCD CONTROLLER/DRIVER 14.4.1 LCDC Control Register Lower (LCRL) The LCDC control register lower (LCRL) controls the driving power, selects display or display blanking, and selects the display mode. LCDC control register lower (LCRL) Address Initial value bit 7 bit 6 bit 5 bit 4 bit 3...
Page 350: Table 14-3 Function Of Each Bit Of Lcdc Control Register Lower (Lcrl)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 14-3 Function of Each Bit of LCDC Control Register Lower (LCRL) Bit Name Function This bit selects a frame cycle generation clock. bit 7 CSS: Clock select bit When this bit is 0, the main clock is selected. When this bit is 1, the sub-clock is selected.
Page 351: Lcdc Control Register Higher (Lcrh)
LCD CONTROLLER/DRIVER 14.4.2 LCDC Control Register Higher (LCRH) This register switches between segment output and the general-purpose port. LCDC control register higher (LCRH) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value 006D X00X0000...
Page 352: Lcd Controller/Driver Display Ram
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.5 LCD Controller/Driver Display RAM The display RAM is “16 × 8-bit” display data memory for generating segment output signals. Display RAM and output pins Data in this RAM is read automatically in synchronization with timing for selecting the common signal, and output from the segment output pin.
Page 353 LCD CONTROLLER/DRIVER 14-17...
Page 354: Table 14-5 Relationship Between Common/Segment Output Pins And Display Ram, And Pins Also Serving As General-Purpose Ports
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 14-5 Relationship between Common/Segment Output Pins and Display RAM, and Pins also Serving as General-purpose Ports Value of SEG5 to RAM Area Used Pins Used as General-Purpose SEG0 Bits of LCRH...
Page 355: Explanation Of Operation Of Lcd Controller/Driver
LCD CONTROLLER/DRIVER 14.6 Explanation of Operation of LCD Controller/Driver The LCD controller/driver performs control and driving for LCD display. Explanation of LCD controller/driver operation The following setting is needed for LCD display: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1...
Page 356: Output Waveform (1/2 Duty) During Operation Of Lcd Controller/Driver
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.6.1 Output Waveform (1/2 duty) during Operation of LCD Controller/Driver The display driving output is 2-frame AC waveform selected in the multiplex driving type. Only the COM0 and COM1 pins are used for LCD display when 1/2 duty is used; the COM2 and COM3 pins are not used.
Page 357: Fig. 14.13 Example Of Output Waveform On 1/2 Bias And 1/2 Duty
LCD CONTROLLER/DRIVER COM0 COM1 COM2 COM3 SEGn SEGn + 1 (ON) Potential difference between COM0 and (ON) SEGn (ON) Potential difference between COM1 and SEGn (ON) (ON) Potential difference between COM0 and SEGn + 1 (ON) (ON) Potential difference between COM1 and (ON) SEGn + 1 1 frame...
Page 358: Fig. 14.14 Example Of Lcd Panel Display Data
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Example of LCD panel connecting and display data (1/2 duty driving type) Example: When displaying 5 Address Address *0 to *7: Indicates bits that correspond to display RAM, bit 2, bit 3, bit 6, and bit 7 not used...
Page 359: Output Waveform (1/3 Duty) During Operation Of Lcd Controller/Driver
LCD CONTROLLER/DRIVER 14.6.2 Output Waveform (1/3 duty) during Operation of LCD Controller/Driver Only the COM0,COM1and COM2 pins are used for LCD display when 1/3 duty is used; the COM3 pin are not used. Output waves on 1/3 bias and 1/3 duty An LCD in which the potential difference between the common output pin and the segment output pin becomes the maximum is set to ON.
Page 360: Fig. 14.15 Example Of Output Waveform On 1/3 Bias And 1/3 Duty
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL COM0 COM1 COM2 COM3 SEGn SEGn + 1 (ON) Potential difference between COM0 and SEGn (ON) (ON) Potential difference between COM1 and SEGn (ON) (ON) Potential difference between COM2 and...
Page 361: Fig. 14.16 Example Of Lcd Panel Display Data
LCD CONTROLLER/DRIVER Example of LCD panel connecting and display data (1/3 duty driving type) Example: When displaying 5 Address When data Address starts at bit When data starts at bit *0 to *8: Indicates bits that correspond to display RAM, bit 3, bit 7 and *2 not used Display data examples for 0 to 9 Display...
Page 362: Output Waveform (1/4 Duty) During Operation Of Lcd Controller/Driver
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 14.6.3 Output Waveform (1/4 duty) during Operation of LCD Controller/Driver All the COM0, COM1, COM2 and COM 3 pins are used for LCD display 1/4 duty. Output waveform on 1/3 bias and 1/4 duty An LCD in which the potential difference between the common output pin and the segment output pin becomes the maximum is set to ON.
Page 363: Fig. 14.17 Example Of Output Waveform On 1/3 Bias And 1/4 Duty
LCD CONTROLLER/DRIVER COM0 COM1 COM2 COM3 SEGn SEGn + 1 (ON) Potential difference between COM0 and SEGn (ON) (ON) Potential difference between COM1 and SEGn (ON) (ON) Potential difference between COM2 and SEGn (ON) (ON) Potential difference between COM3 and SEGn (ON) (ON)
Page 364: Fig. 14.18 Example Of Lcd Panel Display Data
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Example of LCD panel connecting and display data (1/4 duty driving type) Example: When displaying 5 Address Address *0 to *7: Indicates bits that correspond to display RAM. Display data examples for 0 to 9 Display Fig.
Page 365 LCD CONTROLLER/DRIVER 14-29...
Page 366: Chapter 15 Stepping Motor Controller
15. STEPPING MOTOR CONTROLLER 15.1 Overview of Stepping Motor Controller ......15-3 15.2 Stepping Motor Controller Registers......... 15-4 15.3 Explanation of Operation of Stepping Motor Controller ..15-8 15.4 Precautions at Using Stepping Motor Controller ..... 15-10...
Page 367 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 15-2...
Page 368: Fig. 15.1 Block Diagram Of Stepping Motor Controller
STEPPING MOTOR CONTROLLER This chapter describes the functions and operation of the stepping motor controller. 15.1 Overview of Stepping Motor Controller The stepping motor controller consists of two PWM pulse generators, four motor drivers, and selector logic. The four motor drivers have high output drive capabilities and they can be directly connected to the four ends of two motor coils.
Page 369: Stepping Motor Controller Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 15.2 Stepping Motor Controller Registers The stepping motor controller has the following five types of registers: • PWM control register • PWM1 compare register • PWM2 compare register • PWM1 select register •...
Page 370: Pwm Control Register
STEPPING MOTOR CONTROLLER 15.2.1 PWM Control Register The PWM control register starts and stops the stepping motor controller, controls interrupts, and sets the external output pins. n PWM control register PWM control register — — — [bit 7] OE2: Output enable bit When this bit is set to "1", the external pins are assigned as PWM2P0 and PWM2M0 outputs.
Page 371: Pwm1&2 Compare Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 15.2.2 PWM1&2 Compare Registers The contents of the two 8-/10-bit PWM1&2 compare registers determine the widths of PWM pulses. The stored value of "00 " (“000 ”) represents the PWM duty of 0% and "FF "...
Page 372: Pwm 1&2 Select Registers
STEPPING MOTOR CONTROLLER 15.2.3 PWM 1&2 Select Registers The PWM1 and PWM2 select registers select 0, 1, the PWM pulse, or high impedance for the external pin output of the stepping motor controller. n PWM 1&2 select registers PWM1 select register —...
Page 373: Explanation Of Operation Of Stepping Motor Controller
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 15.3 Explanation of Operation of Stepping Motor Controller This section explains the operation of the stepping motor controller. n Setting of operation of stepping motor controller Operating the stepping motor controller requires the setting shown in Figure 15.2.
Page 374: Fig. 15.3 Example Of Pwm 1, 2 Waveform Output
STEPPING MOTOR CONTROLLER Figure 15.3 shows the PWM waveforms generated by the PWM wave-generating circuit. When the compare register value is 00 /000 (duty ratio: 0%): Counter value 00 PWM waveform When the compare register value is 80 /200 (duty ratio: 50%): Counter value 00 PWM waveform When the compare register value is FF...
Page 375: Precautions At Using Stepping Motor Controller
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 15.4 Precautions at Using Stepping Motor Controller This section gives the precautions at using the stepping motor controller. n Precautions for changing PWM settings The PWM compare registers 1 and 2 (PWC1n and PWC2n) and the PWM select registers 1 and 2 (PWS1n and PWS2n) can always be accessed.
Page 376: Chapter 16 Dtp/External Interrupt Circuit
16. DTP/EXTERNAL INTERRUPT CIRCUIT 16.1 Overview of DTP/External Interrupt Circuit ...... 16-3 16.2 Configuration of DTP/External Interrupt Circuit ....16-5 16.3 Pins of DTP/External Interrupt Circuit ......16-7 16.4 Registers for DTP/External Interrupt Circuit ..... 16-8 16.5 Explanation of DTP/External Interrupt Circuit Operation 16-12 16.6 Precautions at Using DTP/External Interrupt Circuit..
Page 377 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16-2...
Page 378: Overview Of Dtp/External Interrupt Circuit
DTP/EXTERNAL INTERRUPT CIRCUIT This chapter explains the functions and operation of DTP/external interrupt circuit. 16.1 Overview of DTP/External Interrupt Circuit A DTP (Data Transfer Peripheral)/external interrupt circuit is existed between externally connected peripheral unit and the CPU of F MC-16LX. DTP/external interrupt circuit communicates the interrupt request or data transfer request generated by the peripheral unit to the CPU to issue the external interrupt request or start the expansion intelligent I/O service (EI...
Page 379 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n DTP/external interrupt circuit and EI Table 16-2 DTP/External Interrupt Circuit and EI Interrupt Control Register Vector Table Address Interrupt Channel Number Register Name Address Lower Upper Bank INT0 #16 (10...
Page 380: Configuration Of Dtp/External Interrupt Circuit
DTP/EXTERNAL INTERRUPT CIRCUIT 16.2 Configuration of DTP/External Interrupt Circuit The DTP/external interrupt circuit consists of the following four blocks: • DTP/Interrupt input detector • Interrupt request level setting register (ELVR) • DTP/Interrupt factor register (EIRR) • DTP/Interrupt enable register (ENIR) n Block diagram of DTP/external interrupt circuit Interrupt request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0...
Page 381 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • DTP/External interrupt input detector When the level or edge selected from the pin input signal for each pin by using the interrupt request level setting register (ELVR) is detected and that level or edge is effective, the DTP/external interrupt factor register (EIRR) IR bit corresponding to the pin is set to 1.
Page 382: Pins Of Dtp/External Interrupt Circuit
DTP/EXTERNAL INTERRUPT CIRCUIT 16.3 Pins of DTP/External Interrupt Circuit The pins of the DTP/external interrupt circuit and the block diagram of pin are explained, and a block diagram is given. n Pins of DTP/external interrupt circuit The pins of the DTP/external interrupt circuit also serve as general-purpose port pins. Table 16-3 shows the function of the pins, I/O type, settings required for using the DTP/external interrupt circuit, etc.
Page 383: Registers For Dtp/External Interrupt Circuit
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16.4 Registers for DTP/External Interrupt Circuit The registers for the DTP/external interrupt circuit are shown. n Registers for DTP/external interrupt circuit Address bit 15 bit 8 bit 7 bit 0...
Page 384: Dtp/Interrupt Enable Register (Enir)
DTP/EXTERNAL INTERRUPT CIRCUIT 16.4.2 DTP/Interrupt Enable Register (ENIR) The DTP/Interrupt enable register (ENIR) enables/disables the output of interrupt request to CPU. n DTP/Interrupt enable register (ENIR) Address bit 15 bit 8 bit 7 bit 6 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 000030...
Page 385: Request Level Setting Register (Elvr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16.4.3 Request Level Setting Register (ELVR) The request level setting register (ELVR) selects (for each pin) the level or edge type of the signal for detecting that the signal that is input to the DTP/external interrupt pin is a DTP/external interrupt factor.
Page 386: Table 16-8 Correspondence Between Dtp/Interrupt Control Registers (Eirr And Enir) And Each Channel
DTP/EXTERNAL INTERRUPT CIRCUIT Table 16-8 Correspondence between DTP/Interrupt Control Registers (EIRR and ENIR) and Each Channel DTP/External Interrupt Bit Number Interrupt Pin Number P03/INT7 #26 (1A LB7, LA7 P02/INT6 #26 (1A LB6, LA6 P01/INT5 #24 (18 LB5, LA5 P00/INT4 #24 (18 LB4, LA4 P53/INT3 #22 (16...
Page 387: Explanation Of Dtp/External Interrupt Circuit Operation
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16.5 Explanation of DTP/External Interrupt Circuit Operation The DTP/external interrupt circuit has an external interrupt function and a DTP function. The setting and operation of each function are explained. n Setting DTP/external interrupt circuit To operate the DTP/external interrupt circuit, the setting shown in Figure 16.7 must be performed.
Page 388: Fig. 16.8 Operation Of Dtp/External Interrupt Circuit
DTP/EXTERNAL INTERRUPT CIRCUIT n DTP/external interrupt operation The control bits and the interrupt factors for the DTP/external interrupt circuit are shown in Table 16-7. Table 16-9 Control Bits and Interrupt Factors for DTP/External Interrupt Circuit DTP/External Interrupt Circuit Interrupt request flag bit EIRR: ER7 to ER0 Interrupt request enable bit ENIR: EN7 to EN0...
Page 389: External Interrupt Function
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16.5.1 External Interrupt Function The DTP/external interrupt circuit has the external interrupt function that issues an interrupt request by the input of the selected signal level to the DTP/external interrupt pin.
Page 390: Dtp Function
DTP/EXTERNAL INTERRUPT CIRCUIT 16.5.2 DTP Function The DTP/external interrupt circuit has the DTP function that detects the signal of the external peripheral unit via the DTP/external interrupt pin to start the EI n Operation of DTP function The DTP function detects the data transfer request signal sent from the external peripheral unit and transfers data automatically between memory and the resource.
Page 391: Precautions At Using Dtp/External Interrupt Circuit
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16.6 Precautions at Using DTP/External Interrupt Circuit The precautions regarding the input signal of the DTP/external interrupt circuit, cancellation of the standby mode, and interrupts are given. n Precautions at using DTP/external interrupt circuit •...
Page 392 DTP/EXTERNAL INTERRUPT CIRCUIT • Precautions for interrupts Control cannot be return from the interrupt processing when the external interrupt request flag bit is 1 and the interrupt request output is still enabled when the external interrupt function is used. Consequently, always clear the external interrupt request flag bit inside the interrupt-processing routine (The bit is cleared automatically by the EI OS when the DTP function is used).
Page 393: Sample Programs For Dtp/External Interrupt Circuit
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 16.7 Sample Programs for DTP/External Interrupt Circuit Sample programs for the external interrupt function and DTP function are given. n Sample program for external interrupt function • Processing specification – An external interrupt is generated by detecting the rising edge of the pulse input to the INT0 pin.
Page 394 DTP/EXTERNAL INTERRUPT CIRCUIT n Sample program for DTP function • Processing specification – Channel 0 of the EI OS is started by detecting the H level of the signal input to the INT0 pin. – RAM data is output to port 0 by performing DTP processing (EI OS).
Page 395 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ;---------- Interruption program -------------------------------------------- ---------------- WARI: ; Interrupt request flag cleared CLRB I:ER0 ; Channel switched and transfer destination address changed as needed Processing by user ; Resetting such as ending EI2OS performed ;...
Page 396: Chapter 17 Delayed Interrupt Generate Module
17. DELAYED INTERRUPT GENERATE MODULE 17.1 Overview of Delayed Interrupt Generate Module ....17-3 17.2 Operation of Delayed Interrupt Generate Module ..... 17-4...
Page 397 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 17-2...
Page 398: Overview Of Delayed Interrupt Generate Module
DELAYED INTERRUPT GENERATE MODULE This chapter explains function and operation of the delayed interrupt generate module. 17.1 Overview of Delayed Interrupt Generate Module The delayed interrupt generate module generates the interrupt for task switching. The interrupt request to the CPU of the F MC-16LX can be issued/cancelled by software using this module.
Page 399: Operation Of Delayed Interrupt Generate Module
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 17.2 Operation of Delayed Interrupt Generate Module When the CPU writes 1 to the corresponding bit of DIRR using software, the request latch in the delayed interrupt generate module is set to issue the interrupt request to the interrupt controller.
Page 400: Chapter 18 Timepiece Timer
18. TIMEPIECE TIMER 18.1 Overview of Timepiece Timer .......... 18-3 18.2 Timepiece Timer Registers ..........18-4...
Page 401 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 18-2...
Page 402: Overview Of Timepiece Timer
TIMEPIECE TIMER This chapter explains the function and operation of the timepiece timer. 18.1 Overview of Timepiece Timer The timepiece timer consists of timepiece timer control register, sub-second data register, second/minute/hour data register, 1/2 clock divider, 21-bit prescaler, and second/minute/hour counter. The specified timepiece timer operates on the precondition that the MCU oscillation frequency is 4 MHz.
Page 403: Timepiece Timer Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 18.2 Timepiece Timer Registers There are five types of registers for the timepiece timer: • Timepiece timer control register (WTCR) • Sub-second data register (WTBR) • Second data register (WTSR) •...
Page 404 TIMEPIECE TIMER n Timepiece timer registers Timepiece timer control Bit No. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 register higer Address: 000059 INTE3 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0 WTCRH Read/write (R/W) (R/W)
Page 405: Timepiece Timer Control Register
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 18.2.1 Timepiece timer Control Register The timepiece timer control register performs starting/stopping of the timepiece timer, control of interrupts, and setting of the external output pins. n Timer control register Timepiece timer control Bit No.
Page 406: Sub-Second Data Register
TIMEPIECE TIMER 18.2.2 Sub-second Data Register The sub-second data register stores reload values for the 21-bit prescaler that divides the oscillation clock. The reload value is usually set so that the output cycle of the 21-bit prescaler becomes precisely 1 second. n Sub-second data register Bit No.
Page 407: Second/Minute/Hour Data Register
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 18.2.3 Second/Minute/Hour Data Register The second/minute/hour data register stores time information. Seconds, minutes, and hours are expressed in binary. When these registers are read, the counter is simply restored to its original value. However, these registers involve writes;...
Page 408: Chapter 19 8-/10- Bit A/D Converter
19. 8-/10-BIT A/D CONVERTER 19.1 Overview of 8-/10-bit A/D Converter ....... 19-3 19.2 Configuration of 8-/10-bit A/D Converter......19-4 19.3 Pins of 8-/10-bit A/D Converter........19-6 19.4 Registers for 8-/10-bit A/D Converter......19-8 19.5 Interrupt of 8-/10-bit A/D Converter....... 19-15 19.6 Explanation of 8-/10-bit A/D Converter Operation..
Page 409 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19-2...
Page 410: Overview Of 8-/10-Bit A/D Converter
8-/10-BIT A/D CONVERTER This chapter explains the 8-/10-bit A/D converter functions and operation. 19.1 Overview of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts the analog input voltage to a 10- or 8-bit digital value by using the RC sequential-comparison converter system. An input signal can be selected from the input signals of the analog input pins for 8 channels, and a conversion start can be selected from the trigger input starts made by the software, 16-bit reload timer 1, and external pins.
Page 411: Configuration Of 8-/10-Bit A/D Converter
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19.2 Configuration of 8-/10-bit A/D Converter The 8-/10-bit A/D converter consists of following nine blocks. • A/D control status register (ADCS) • A/D data register (ADCR) • Decoder • Analog channel selector •...
Page 412 8-/10-BIT A/D CONVERTER • A/D control status registers (ADCS) These registers perform the following operations: start A/D conversion by using software, select start trigger, select conversion mode, select channel subjected to A/D conversion, enable/disable interrupt request, check state of interrupt request, and display states during suspension and conversion. •...
Page 413: Pins Of 8-/10-Bit A/D Converter
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19.3 Pins of 8-/10-bit A/D Converter The pins of the 8-/10-bit AD/converter and block diagram of pin are shown. n Pins of 8-/10-bit A/D converter The pins of the A/D converter also serve as general-purpose port pins. Table 19-3 shows the function of the pins, I/O form, settings required for using the 8-/10-bit A/D converter, etc.
Page 414: Fig. 19.2 Block Diagram Of P60/An0 To P67/An7 Pins
8-/10-BIT A/D CONVERTER n Block diagram of pins of port 8-/10-bit A/D Converter ADER Analog input PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read Standby control (SPL = 1) Fig.
Page 415: Registers For 8-/10-Bit A/D Converter
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19.4 Registers for 8-/10-bit A/D Converter The registers for the 8-/10-bit A/D converter are shown. n Registers for 8-/10-bit A/D converter Figure 19.3 shows the registers for the 8-/10-bit A/D converter.
Page 416: A/D Control Status Register Upper (Adcsh)
8-/10-BIT A/D CONVERTER 19.4.1 A/D Control Status Register Upper (ADCSH) The A/D control status register higher (ADCSH) defines starting by using software, selects the start trigger, enables/disables interrupt request, checks state of interrupt request, and checks during pause and conversion. n A/D control status register higher (ADCSH) Address bit 15 bit 14 bit 13 bit1 2 bit 11 bit 10 bit 9 bit 8 bit 7...
Page 417: Table 19-4 Function Of Each Bit Of A/D Control Status Register Higher (Adcsh)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 19-4 Function of Each Bit of A/D Control Status Register Higher (ADCSH) Bit Name Function • This bit indicates the A/D converter operation. bit 15 BUSY: • When this bit is 0 at read, it indicates that A/D conversion is stopped. When this bit is...
Page 418: A/D Control Status Register Lower (Adcsl)
8-/10-BIT A/D CONVERTER 19.4.2 A/D Control Status Register Lower (ADCSL) The A/D control status register lower (ADCSL) selects the conversion mode and A/D conversion channel. n A/D control status register lower (ADCS lower) bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 000020...
Page 419: Table 19-5 Function Of Each Bit Of A/D Control Status Register Lower (Adcsl)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 19-5 Function of Each Bit of A/D Control Status Register Lower (ADCSL) Bit Name Function • These bits select the conversion mode used when the A/D conversion function is used.
Page 420: A/D Data Register (Adcrh/ Adcrl)
8-/10-BIT A/D CONVERTER 19.4.3 A/D Data Register (ADCRH/ ADCRL) The A/D data registers (ADCRH/ ADCRL) store the results of A/D conversion and also select the A/D conversion resolution. n A/D data register (ADCRH/ ADCRL) bit 15 bit 14bit 13bit1 2 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 000023 S10 ST1 ST0 CT1 CT0...
Page 421: Table 19-6 Function Of Each Bit Of A/D Data Register (Adcr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 19-6 Function of Each Bit of A/D Data Register (ADCR) Bit Name Function • This bit selects the A/D conversion resolution. bit 15 S10: • When 0 is written to this bit, 10-bit resolution is selected; when 1 is written, 8-bit...
Page 422: Interrupt Of 8-/10-Bit A/D Converter
8-/10-BIT A/D CONVERTER 19.5 Interrupt of 8-/10-bit A/D Converter The 8-/10-bit A/D converter can issue an interrupt request when data is set to the A/D data register by A/D conversion. This also corresponds to the EI n Interrupt of 8-/10-bit A/D converter The interrupt control bits and interrupt factors of the 8-/10-bit A/D converter are shown in Table 19-7.
Page 423: Explanation Of 8-/10-Bit A/D Converter Operation
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19.6 Explanation of 8-/10-bit A/D Converter Operation The 8-/10-bit A/D converter has three modes: single-shot conversion, continuous conversion, and pause- conversion. The operation of each mode is explained. n Operation of single-shot conversion mode...
Page 424: Fig. 19.8 Setting In Continuous Conversion Mode
8-/10-BIT A/D CONVERTER n Operation of continuous conversion mode In the continuous conversion mode, the analog input specified for the ANS bits and ANE bits is converted sequentially, and when the conversion for up to the end channel specified by the ANE bit ends, a return is made to the analog input specified by the ANS bit to continue the A/D conversion.
Page 425: Fig. 19.9 Setting In Pause-Conversion Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n Operation of pause-conversion mode In the pause-conversion mode, the analog input specified for the ANS bits and ANE bits pauses by one channel and are converted sequentially, and when conversion for up to the ending channel that was set for the ANE bit is completed, control is returned to the analog input set for the ANS bit to continue A/D conversion and pause.
Page 426: Conversion Using Ei2Os
8-/10-BIT A/D CONVERTER 19.6.1 Conversion Using EI The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using the EI n Conversion using EI The operation flow when the EI OS is used is shown in Figure 19.10. Start of A/D converter Starting EI Sample Hold...
Page 427: A/D-Converted Data Protection Function
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19.6.2 A/D-converted Data Protection Function During A/D conversion with the interrupt enabled, the function to protect A/D-converted data operates. n A/D-converted data protection function This A/D converter has only one data register for storing converted data, so during A/D conversion, data stored in the data register is rewritten at completion of conversion.
Page 428 8-/10-BIT A/D CONVERTER OS set Start of A/D continuous conversion End of first conversion Data stored in data register Start of EI End of second conversion OS completion Pause of A/D Data stored in data register End of third conversion Start of EI Continued End of entire conversion...
Page 429: Precautions At Using 8-/10-Bit A/D Converter
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 19.7 Precautions at Using 8-/10-bit A/D Converter Precautions at using the 8-/10-bit A/D converter are given below: n Precautions at using 8-/10-bit A/D converter • Analog input pin The A/D input pin also serves as the I/O pin of port 6; these two functions are used by switching with the port 6 direction register (DDR6) and the analog input enable register (ADER).
Page 430: Sample Program 1 For 8-/10-Bit A/D Converter (Ei Os Start In Single-Shot Mode)
8-/10-BIT A/D CONVERTER 19.8 Sample Program 1 for 8-/10-bit A/D Converter (EI OS Start in Single-shot Mode) Sample program for A/D conversion by starting EI OS in the single-shot mode is shown below: n Sample program for starting EI OS in single-shot mode •...
Page 431 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ; Conversion data store destination address set BAPL, #00 ; (Addresses 200 to 205 BAPM, #02 BAPH, #00 ; Word data transferred and then address incremented by ISCS, #18 Transfer from I/O to memory ;...
Page 432: Sample Program 2 For 8-/10-Bit A/D Converter (Ei Os Start In Continuous Mode)
8-/10-BIT A/D CONVERTER 19.9 Sample Program 2 for 8-/10-bit A/D Converter (EI OS Start in Continuous Mode) Sample program for A/D conversion by starting EI OS in the continuous mode is shown below: n Sample program for starting EI OS in continuous mode •...
Page 433 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ; Stack pointer (SP), etc., already initialized START ; Interrupts disabled CCR, #0BF ; Interrupt level = 0 (highest level), interrupt enable ICR10, #08 ; Converted data store destination address set BAPL, #00 ;...
Page 434: Sample Program 3 For 8-/10-Bit A/D Converter (Ei Os Start In Stop Mode)
8-/10-BIT A/D CONVERTER 19.10 Sample Program 3 for 8-/10-Bit A/D Converter (EI OS Start in Stop Mode) A stop mode program that performs A/D conversion by starting EI OS is shown below: n Stop mode sample program to start EI •...
Page 435 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ; Stack pointer (SP), etc., already initialized START ; Interrupts disabled CCR, #0BF ; Interrupt level = 0 (highest) ICR10, #08 ; Converted data store destination address set BAPL, #00 ;...
Page 436: Chapter 20 Sound Generator
20. SOUND GENERATOR 20.1 Overview of Sound Generator .......... 20-3 20.2 Sound Generator Registers..........20-4...
Page 437 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 20-2...
Page 438: Overview Of Sound Generator
SOUND GENERATOR This chapter explains the functions and operations of the sound generator. 20.1 Overview of Sound Generator The sound generator consists of the sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter and tone pulse counter.
Page 439: Sound Generator Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 20.2 Sound Generator Registers The sound generator has the following types of registers: • Sound control register (SGCR) • Frequency data register (SGFR) • Amplitude data register (SGAR) • Decrement grade register (SGDR) •...
Page 440: Sound Control Register
SOUND GENERATOR 20.2.1 Sound Control Register The sound control register controls the operation status of the sound generator by controlling interrupts and setting the external output pins. n Sound Control Register ← Bit No. Sound control register (upper) Address: 00005B —...
Page 441 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL [bit 3] OE1 : Amplitude output enable bit When this bit is set to "1", the external pin is assigned as the SGA output. Otherwise the pin can be used as a general purpose I/O.
Page 442: Frequency Data Register
SOUND GENERATOR 20.2.2 Frequency Data Register The frequency data register stores the reload value for the frequency counter. The stored value represents the frequency of the sound (or the tone signal from the toggle flip-flop). The register value is reloaded into the counter at every transition of the toggle signal.
Page 443: Amplitude Data Register
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 20.2.3 Amplitude Data Register The Amplitude Data register stores the reload value for the PWM pulse generator. The register value represents the amplitude of the sound. The register value is reloaded into the PWM pulse generator at the end of every tone cycle.
Page 444: Decrement Grade Register
SOUND GENERATOR 20.2.4 Decrement Grade Register The decrement grade register stores the reload value for the decrement counter. They are prepared to automatically decrement the stored value in the amplitude data register. n Decrement Grade Register ← Bit No. Decrement grade register Address: 00005E SGDR Read/write →...
Page 445 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 20-10...
Page 446: Chapter 21 Rom Correction
21. ROM CORRECTION 21.1 Overview of ROM Correction..........21-3 21.2 Application Example of ROM Correction ......21-6...
Page 447 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 21-2...
Page 448: Overview Of Rom Correction
ROM CORRECTION This chapter explains the functions and operations of ROM correction. 21.1 Overview of ROM Correction When the setting of the address is the same as the ROM correction address registers, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved.
Page 449 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n ROM correction address register (PADR0/PADR1) These registers hold the addresses for the comparison with program counter. If there is a match and the corresponding ADCSR compare enable bit is '1', this module demands the CPU to execute the INT9 instruction.
Page 450 ROM CORRECTION n Operations of ROM correction When the program counter indicates the same address as the ROM correction address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing a compare enable bit.
Page 451: Application Example Of Rom Correction
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 21.2 Application Example of ROM Correction The ROM correction function is enabled by externally providing an EEPROM and by storing information on corrections and a patch program in the EEPROM.
Page 452: Correction Example Of Program Errors
ROM CORRECTION 21.2.1 Correction Example of Program Errors The body of the patch program and the program address are transferred to the MCU through the connector (UART). MCU then writes that information to the EEPROM. n When a program error occurs Figure 21.3 shows an example of ROM correction processing when a program error occurs.
Page 453: Example Of Correction Processing
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 21.2.2 Example of Correction Processing After resetting, the MCU reads the contents of the EEPROM. If the byte count of the patch program is not '0', the body of the patch program is read from the EEPROM and written to the RAM. Then the MCU sets the program address either on PADR0 or on PADR1 and enables the operation.
Page 454: Fig. 21.5 Rom Correction Processing Flow Diagram
ROM CORRECTION MB90427 FFFFFF FF0050 Erroneous program FF0000 PROM FFFF FE0000 0090 Patch program 0010 001100 Stack area Program address lower: 00 RAM area 0003 000480 Program address middle: 00 Patch program 0002 000400 Program address higher: 00 RAM/register area 0001 000100 Byte count of patch program: 80...
Page 455 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 21-10...
Page 456: Chapter 22 Rom Mirror Function Select Module
22. ROM MIRROR FUNCTION SELECT MODULE 22.1 Overview of ROM Mirror Function Select Module ..... 22-3 22.2 ROM Mirror Function Select Register (ROMM)....22-4...
Page 457 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 22-2...
Page 458: Overview Of Rom Mirror Function Select Module
ROM MIRROR FUNCTION SELECT MODULE This chapter explains the ROM Mirror Function Select Module. 22.1 Overview of ROM Mirror Function Select Module Mirroring the ROM by the 00 bank in the ROM mirror function select module can be set by the register. n ROM mirror function select module ←...
Page 459: Rom Mirror Function Select Register (Romm)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 22.2 ROM Mirror Function Select Register (ROMM) Do not access the ROM mirror function select register (ROMM) when addresses 004000 to 00FFFF being accessed. n ROM mirror function select register (ROMM) ←...
Page 460: Chapter 23 Can Controller
23. CAN CONTROLLER 23.1 Features of CAN Controller ..........23-3 23.2 Block Diagram of CAN Controller ........23-4 23.3 List of Overall Control Registers ........23-5 23.4 List of Message Buffers (ID Registers) ......23-7 23.5 List of Message Buffers (DLC Registers and Data Registers) ......
Page 461 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23-2...
Page 462: Features Of Can Controller
CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. 23.1 Features of CAN Controller The CAN controller is a module built into a 16-bit microcompluter (F MC-16LX). The CAN (controller area network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications.
Page 463: Block Diagram Of Can Controller
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.2 Block Diagram of CAN Controller Figure 23.1 shows a block diagram of the CAN controller. n Block diagram of CAN controller TQ (Operating clock) MC-16LX bus Prescaler 1 to 64...
Page 464: List Of Overall Control Registers
CAN CONTROLLER 23.3 List of Overall Control Registers Table 23-1 lists overall control registers and CAN WAKE UP control registers. n List of overall control registers Table 23-1 List of Overall Control Registers Address Register Abbreviation Access Initial Value CAN0 CAN1 000040 000070...
Page 465: Table 23-2 List Of Can Wake Up Control Registers
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL (Continued) Address Register Abbreviation Access Initial Value CAN0 CAN1 003C0E 003D0E Transmit interrupt enable TIER (R/W) 00000000 00000000 register 003C0F 003D0F 003C10 003D10 XXXXXXXX XXXXXXXX 003C11 003D11 Acceptance mask select...
Page 466: List Of Message Buffers (Id Registers)
CAN CONTROLLER 23.4 List of Message Buffers (ID Registers) Table 23-3 lists message buffers (ID registers). n List of message buffers (ID registers) Table 23-3 List of Message Buffers (ID Registers) Address Register Abbreviation Access Initial Value CAN0 CAN1 003A00 003B00 General-purpose RAM —...
Page 467 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL (Continued) Address Register Abbreviation Access Initial Value CAN0 CAN1 003A3C 003B3C XXXXXXXX XXXXXXXX 003A3D 003B3D ID register 7 IDR7 (R/W) 003A3E 003B3E XXXXX--- XXXXXXXX 003A3F 003B3F 003A40 003B40 XXXXXXXX XXXXXXXX...
Page 468: List Of Message Buffers (Dlc Registers And Data Registers)
CAN CONTROLLER 23.5 List of Message Buffers (DLC Registers and Data Registers) Table 23-4 lists message buffers (DLC registers), and Table 23-5 lists message buffers (data registers). n List of message buffers (DLC registers) Table 23-4 List of Message Buffers (DLC Registers) Address Register Abbreviation...
Page 469: Table 23-5 List Of Message Buffers (Data Registers)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL n List of message buffers (data registers) Table 23-5 List of Message Buffers (Data Registers) Address Register Abbreviation Access Initial Value CAN0 CAN1 003A80 003B80 Data register 0 (8 bytes)
Page 470: Classifying Can Controller Registers
CAN CONTROLLER 23.6 Classifying CAN Controller Registers There are three types of CAN controller registers: • Overall control registers • Message buffer control registers • Message buffers n Overall control registers The overall control registers are the following four registers: •...
Page 471: Control Status Register (Csr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.1 Control Status Register (CSR) Control status register (CSR) is prohibited from executing any bit manipulation instructions (read-modify- write instructions). n Control status register (CSR) ← Bit No. Address: 003C01...
Page 472: Fig. 23.2 Node Status Transition Diagram
CAN CONTROLLER [bits 9 to 8] NS1 and NS0: Node status bits 1 and 0 These bits indicate the current node status. Table 23-6 Correspondence between NS1 and NS0 and Node Status Node Status Error active Warning (error active) Error passive Bus off Note: Warning (error active) is included in the error active in CAN Specifications 2.0 B for the node...
Page 473: Bus Operation Stop Bit (Halt = 1)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.2 Bus Operation Stop Bit (HALT = 1) The bus operation stop bit sets or cancels stopping of bus operation, or indicates its status n Conditions for setting bus operation stop (HALT=1) There are three conditions for setting bus operation stop (HALT = 1): •...
Page 474: Last Event Indicate Register (Leir)
CAN CONTROLLER 23.6.3 Last Event Indicate Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other bits are set to 0s. n Last event indicate register (LEIR) ←...
Page 475: Receive And Transmit Error Counters (Rtec)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.4 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read.
Page 476: Bit Timing Register (Btr)
CAN CONTROLLER 23.6.5 Bit Timing Register (BTR) Bit timing register (BTR) sets the prescaler and bit timing setting. n Bit timing register (BTR) ← Bit No. Address: 003C07 (CAN0) Address: 003D07 (CAN1) — TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0 Read/write →...
Page 477 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ = RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division is shown below.
Page 478: Message Buffer Valid Register (Bvalr)
CAN CONTROLLER 23.6.6 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers (x) or displays their state. n Message buffer valid register (BVALR) ← Bit No. Address: 000041 (CAN0) Address: 000071 (CAN1) BVAL15 BVAL14 BVAL13...
Page 479: Transmission Request Register (Treqr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.8 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. n Transmission request register (TREQR) ← Bit No. Address: 000043...
Page 480: Remote Frame Receiving Wait Register (Rfwtr)
CAN CONTROLLER 23.6.10 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) stores the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0).
Page 481: Transmission Complete Register (Tcr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.12 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs.
Page 482: Reception Complete Register (Rcr)
CAN CONTROLLER 23.6.14 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register is 1, an interrupt occurs. n Reception complete register (RCR) ←...
Page 483: Receive Overrun Register (Rovrr)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.16 Receive Overrun Register (ROVRR) If the reception completion register (RCR) is already 1 when storing of the received message in the message buffer (x) is completed, ROVRx is set to 1, meaning that reception overruns.
Page 484: Acceptance Mask Select Register (Amsr)
CAN CONTROLLER 23.6.18 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the receive message ID and the message buffer (x) ID. n Acceptance Mask Select Register (AMSR) BYTE0 ← Bit No. Address: 003C10 (CAN0) Address: 003D10 (CAN1) AMS3.1...
Page 485: Acceptance Mask Registers 0 And 1 (Amr0 And Amr1)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format.
Page 486: Message Buffers
CAN CONTROLLER • 0: Compare Compare the bit of the acceptance code (ID register IDRx for comparing with the receive message ID) corresponding to this bit with the bit of the received message ID. If there is no match, no message is received.
Page 487: Id Register X (X = 0 To 15) (Idrx)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.21 ID Register x (x = 0 to 15) (IDRx) ID register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x). n ID register x (x = 0 to 15) (IDRx) BYTE0 ←...
Page 488: Dlc Register X (X = 0 To 15) (Dlcrx)
CAN CONTROLLER 23.6.22 DLC Register x (x = 0 to 15) (DLCRx) DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x. n DLC register x (x = 0 to 15) (DLCRx) ← Bit No. Address: 003A60 +2x (CAN0) Address: 003B60...
Page 489: Data Register X (X = 0 To 15) (Dtrx)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.6.23 Data Register x (x = 0 to 15) (DTRx) Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x). This register is used only at transmission and reception of a data frame but not at transmission and reception of a remote frame.
Page 490: Can Wake Up Control Register (Cwucr)
CAN CONTROLLER 23.6.24 CAN WAKE UP Control Register (CWUCR) The CAN WAKE UP control register (CWUCR) controls the internal connection of the RX pin to the INT pin. n CAN WAKE UP control register (CWUCR) CWUCR ← Bit No. Address: 003E —...
Page 491: Transmission Of Can Controller
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.7 Transmission of CAN Controller When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0.
Page 492: Fig. 23.5 Transmission Flowchart Of The Can Controller
CAN CONTROLLER n Transmission flowchart of the CAN controller Figure 23.5 shows a transmission flowchart of the CAN controller. Transmission request = 1) TREQx : TCx : TREQx RFW T x RRTRx If there are any other message buffers meeting the above conditions, select the lowest-numbered message buffer Is the bus idke? TRTRx...
Page 493: Reception Of Can Controller
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.8 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. n Acceptance filtering The receive message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is 0).
Page 494: Fig. 23.6 Flowchart Determining Message Buffer (X) Where Receive Messages Stored
CAN CONTROLLER Figure 23.6 shows a flowchart for determining the message buffer (x) where receive messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to all bits mask.
Page 495: Reception Flowchart For Can Controller
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.9 Reception Flowchart for CAN Controller Figure 23.7 shows a reception flowchar.t of the CAN controller. n Reception flowchart of the CAN controller Data frame or remote frame starting (SOF) detected...
Page 496: How To Use Can Controller
CAN CONTROLLER 23.10 How to Use CAN Controller The following settings are required to use the CAN controller: • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode n Setting bit timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1).
Page 497: Procedure For Transmission By Message Buffer (X)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.11 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to validate the message buffer (x). n Procedure for transmission by message buffer (x) •...
Page 498 CAN CONTROLLER • Processing for completion of transmission If transmission is successful, TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. After checking the transmission completion, write 0 to TCx to set it to 0.
Page 499: Procedure For Reception By Message Buffer (X)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23.12 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. n Procedure for reception by message buffer (x) •...
Page 500: Setting Configuration Of Multi-Level Message Buffer
CAN CONTROLLER 23.13 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID's of messages are received, in other words, if there is insufficient time for processing messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the receive message by CPU.
Page 501: Fig. 23.9 Examples Of Operation Of Multi-Level Message Buffer
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Initialization AMS15, AMS14, AMS13 • • • AMSR 10 10 10 AM28 to AM18 Select AMR0. AMS0 0000 1111 111 • • • ID28 to ID18 RC15, RC14, RC13 • • •...
Page 502: Can Wake Up Function
CAN CONTROLLER 23.14 CAN WAKE UP Function When a connection is made between the CAN RX pin and the external interrupt pin, it is possible to use the WAKE UP function for CAN reception. n Pins used by CAN WAKE UP function Connecting the RX0 and INT0 pins internally provides the WAKE UP function.
Page 503 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 23-44...
Page 504: Chapter 24 Low Voltage And Cpu Operation Detection Reset Circuit
24. LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT 24.1 Overview of Low Voltage and CPU Operation Detection Reset Circuit..............24-3 24.2 Configuration of Low Voltage and CPU Operation Detection Reset Circuit..............24-4 24.3 Register for Low Voltage and CPU Operation Detection Reset Circuit..............
Page 505 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 24-2...
Page 506: Overview Of Low Voltage And Cpu Operation Detection Reset Circuit
LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT This chapter explains the function and operation of the detection reset circuit for low voltage and CPU operation. 24.1 Overview of Low Voltage and CPU Operation Detection Reset Circuit The low-voltage detection reset circuit monitors the power supply voltage and detects falls below the detection voltage value.
Page 507: Configuration Of Low Voltage And Cpu Operation Detection Reset Circuit
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 24.2 Configuration of Low Voltage and CPU Operation Detection Reset Circuit The detection reset circuit for low voltage and CPU operation consists of the following 3 blocks: • CPU operation detection circuit •...
Page 508: Register For Low Voltage And Cpu Operation Detection Reset Circuit
LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT 24.3 Register for Low Voltage and CPU Operation Detection Reset Circuit The detection reset control register for low voltage and CPU operation (LVRC) clears the detection reset flags for low voltage and CPU operation, the CPU operation detection circuit counter, etc. n Detection reset control register for low voltage and CPU operation (LVRC) bit 7 bit 6...
Page 509: Table 24-3 Explanation Of Function Of Each Bit Of Low Voltage And Cpu Operation Detection Reset Control Register
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Table 24-3 Explanation of Function of Each Bit of Low Voltage and CPU Operation Detection Reset Control Register Bit Name Function bit 7 RESV0: Note: Always write 0 to this bit.
Page 510: Operation Of Low Voltage And Cpu Operation Detection Reset Circuit
LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT 24.4 Operation of Low Voltage and CPU Operation Detection Reset Circuit The low-voltage detection function causes an internal reset when it detects that the power supply voltage has fallen below the set point. The CPU operation detection function causes an internal reset when the counter is not cleared at regular intervals.
Page 511: Cautions When Using Low Voltage And Cpu Operation Detection Reset Circuit
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 24.5 Cautions when Using Low Voltage and CPU Operation Detection Reset Circuit The cautions when using the low voltage & CPU operation detection reset circuit are given below: n Cautions when using low-voltage detection reset circuit •...
Page 512: Sample Program For Low Voltage And Cpu Operation Detection Reset Circuit
LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT 24.6 Sample Program for Low Voltage and CPU Operation Detection Reset Circuit A sample program for the low voltage and CPU operation detection reset circuit is given below: n Sample program for low voltage and CPU operation detection reset circuit •...
Page 513 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 24-10...
Page 514: Chapter 25 1-Mbit Flash Memory
25. 1-MBIT FLASH MEMORY 25.1 Overview of 1-Mbit Flash Memory ........25-3 25.2 Block Diagram for Entire Flash Memory and Flash Memory Sector Configuration ....... 25-4 25.3 Program/Erase Mode ............. 25-6 25.4 Flash Memory Control Status Register (FMCS) ....25-8 25.5 Start Automatic Algorithm of Flash Memory....
Page 515 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25-2...
Page 516: Overview Of 1-Mbit Flash Memory
1-MBIT FLASH MEMORY This chapter gives a general description of 1-Mbit flash memory. There are three ways of programming and erasing to and from flash memory as follows: 1. Programming and erasing using parallel writer (Minato Electronics MODEL1890A) 2. Programming and erasing using serial writer (Yokogawa Digital Computer AF-200) 3.
Page 517: Block Diagram For Entire Flash Memory And Flash Memory Sector Configuration
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.2 Block Diagram for Entire Flash Memory and Flash Memory Sector Configuration Figure 25.1 gives the block diagram for the entire flash memory with the flash memory interface circuit, and Figure 25.2 gives the flash memory sector configuration.
Page 518: Fig. 25.2 Sector Configuration Of 1-Mbit Flash Memory
1-MBIT FLASH MEMORY n Sector configuration of 1-Mbit flash memory Figure 25.2 shows the sector configuration of 1-Mbit flash memory. The upper and lower addresses of each sector are given in the figure. Sector Configuration For access from the CPU, the FF bank register has SA0 and the FE bank register has SA1 to SA6. Flash memory CPU address Writer address*...
Page 519: Program/Erase Mode
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.3 Program/Erase Mode The flash memory is accessed in two different ways: flash memory mode, and other mode. In the flash memory mode, programming/erasing can be performed directly from external pins. In the other mode, programming/erasing can be performed from the CPU via the internal bus.
Page 520: Table 25-1 Flash Memorr Control Signals
1-MBIT FLASH MEMORY Table 25-1 Flash Memorr Control Signals MB90F428/A MBM29F400TA Pin No. Normal Function Flash Memory Mode COM2, COM3, 1 to 8 AQ0 to AQ7 A-1, A0 to A6 SEG0 to SEG5 SEG6 AQ16 –– –– SEG7 –– –– SEG8 ––...
Page 521: Flash Memory Control Status Register (Fmcs)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.4 Flash Memory Control Status Register (FMCS) The control status register (FMCS) with the flash memory interface circuit, is used at programming to/erasing from flash memory. n Control status register (FMCS) Bit No.
Page 522 1-MBIT FLASH MEMORY [bit 2, 0] LPM1, LPM0 (Low Power Mode) These bits control the current consumption of the flash memory when the flash memory is accessed. However, since the period of time during which flash memory is accessed from the CPU depends greatly on the setting, select a setting in accordance with the CPU operating frequency.
Page 523: Start Automatic Algorithm Of Flash Memory
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.5 Start Automatic Algorithm of Flash Memory There are four commands for starting the automatic algorithm of flash memory: read/reset, write, chip erase. The sector erase command controls suspension and resumption of sector erase.
Page 524: Check Execution State Of Automatic Algorithm
1-MBIT FLASH MEMORY 25.6 Check the Execution State of Automatic Algorithm Since the Programming/erasing flow is controlled by the automatic algorithm, 1-Mbit flash memory has a hardware sequence flag and Ready/Busy signal to inform units outside flash memory of its internal operation and operation completion.
Page 525: Data Polling Flag (Dq7)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is mainly used to notify that the automatic algorithm is executing or has been completed using the data polling function.
Page 526: Toggle Bit Flag (Dq6)
1-MBIT FLASH MEMORY 25.6.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ6), the toggle bit flag is mainly used to notify that the automatic algorithm is executing or has been completed using the toggle bit function. n Toggle bit flag (DQ6) Tables 25-7 and 25-8 gives the state transition of the toggle bit flag.
Page 527: Timing Limit Exceeding Flag (Dq5)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.6.3 Timing Limit Exceeding Flag (DQ5) The timing limit exceeding flag (DQ5) is used to notify that the automatic algorithm has executed beyond the time (internal pulse count) specified in flash memory.
Page 528: Sector Erase Timer Flag (Dq3)
1-MBIT FLASH MEMORY 25.6.4 Sector Erase Timer Flag (DQ3) The sector erase time flag is used to notify during the period of waiting for sector erasing after the sector erase command has started. n Sector erase timer flag (DQ3) Tables 25-11 and 25-12 gives the state transition of the sector erase timer flag. Table 25-11 State Transition of Sector Erase Timer Flag (State change at normal operation) Sector Erasing Sector Erasing...
Page 529: Details Of Programming To And Erasing From Flash Memory
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.7 Details of Programming to and Erasing from Flash Memory This section explains the procedure for issuing commands starting the aoutomatic algorithm, and for read from/reset of flash memory, programming, chip erasing, sector erasing, sector erasing suspention and sector erasing resumption.
Page 530: Data Programming To Flash Memory
1-MBIT FLASH MEMORY 25.7.2 Data Programming to Flash Memory This section explains the procedure for issuing the program command to program data to flash memory. n Data programming to flash memory Data can be programmed to flash memory by continuously sending the program command in the command sequence table (see Table 25-2 of Section 25.5) to a target sector in flash memory.
Page 531: Fig. 25.3 Example Of Data Programming Procedure
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Start FMCS: WE (bit 5) Programming enabled Program command sequence 1. FxAAAA ← XXAA 2. Fx5554 ← XX55 3. FxAAAA ← XXA0 Program address ← Program data Internal address read...
Page 532: All Data Erasing From Flash Memory (Chip Erase)
1-MBIT FLASH MEMORY 25.7.3 All Data Erasing from Flash Memory (Chip Erasing) This section explains the procedure for issuing the chip erase command to erase all data from flash memory. n All data erasing from flash memory (Chip Erase) All data can be erased from flash memory by continuously sending the chip erase command in the command sequence table (see Table 25-2 of Section 25.5) to a target sector in flash memory.
Page 533: Fig. 25.4 Example Of Sector Erasing Procedure
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Start FMCS: WE (bit 5) Erasing enabled Erase command sequence 1. FxAAAA ← XXAA 2. Fx5554 ← XX55 3. FxAAAA ← XX80 4. FxAAAA ← XXAA 5. Fx5554 ← XX55...
Page 534: Sector Erasing Suspention
1-MBIT FLASH MEMORY 25.7.5 Sector Erasing Suspention This section explains the procedure for issuing the sector erasing suspend command to suspend sector erasing. Data can be read from the sector not being erased. n Sector erasing suspention Sector erasing can be suspended by continuously sending the sector erasing suspend command in the command sequence table (see Table 25-2 of Section 25.5) to flash memory.
Page 535: Cautions When Using Flash Memory
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 25.8 Cautions when Using Flash Memory The cautions when using the MB90F428/A flash memory are given below. n Cautions in using the flash memory —— • Input of hardware reset (...
Page 536: Sample Program For 1-Mbit Flash Memory
1-MBIT FLASH MEMORY 25.9 Sample Program for 1-Mbit Flash Memory A sample program for the 1-Mbit flash memory is given below. n Sample program for 1-Mbit flash memory NAME FLASHWE TITLE FLASHWE ;--------------------------------------------------------------------------- ; 1 Mbit-FLASH Sample Program ; 1: Transfer program in flash (address FFBC00 , sector SA4) to RAM (address 000700 ;...
Page 537 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ; FLASH command address DATA DSEG ABS = 0FF 5554 COMADR2 0AAAA COMADR1 DATA ENDS ;/////////////////////////////////////////////////////////////// ; Main program (FFA000 ;/////////////////////////////////////////////////////////////// CODE CSEG START: ;////////////////////////////////////////////////////// ; Initialize ;////////////////////////////////////////////////////// ; 3-multiplying count...
Page 538 1-MBIT FLASH MEMORY Initialize //////////////////////////////////////////// ; RW0: RAM space for storage of input data MOVW RW0, #0500 00:0500~ ; RW2: Flash programming address FD:0000~ MOVW RW2, #0000 ; DTB change A, #00 ; Specify bank for @RW0. DTB, A ; ADB change 1 A, #0FE ;...
Page 539 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ; PDR3:1 With High, start sector erasing. WAIT2 PDR3:1, WAIT2 ;///////////////////////////////////////////// ; Sector erasing (SA0) ;///////////////////////////////////////////// ; Initialize address. @RW2+00, #0000 ; Set erase mode. FMCS, #20 ; Erase command 1...
Page 540 26. EXAMPLES OF MB90F428/A SERIAL WRITE CONNECTION 26.1 Basic Configuration of MB90F428/A Serial Write Connection ..............26-3 26.2 Example of Serial Write Connection (User Power Supply Used) ..........26-5 26.3 Example of Serial Write Connection (Power Supplied from the Writer)........26-7 26.4 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) 26-9 26.5 Example of Minimum Connection to the Flash...
Page 541 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL 26-2...
Page 542: Chapter 26 Examples Of Mb90F428/A Serial Write Connection
EXAMPLES OF MB90F428/A SERIAL WRITE CONNECTION This chapter gives examples of MB90F428/A serial write connection. 26.1 Basic Configuration of MB90F428/A Serial Write Connection The MB90F428/A supports flash ROM serial onboard writing (Fujitsu standard). This section describes the specifications. n Basic configuration The flash microcontroller programmer from Yokogawa Digital Computer Ltd.
Page 543: Table 26-2 Flash Microcontroller Programmer System Configuration (Manufactured By Yokogawa Digital Computer Ltd.)
MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing.
Page 544: Example Of Serial Write Connection (User Power Supply Used)
EXAMPLES OF MB90F428/A SERIAL WRITE CONNECTION 26.2 Example of Serial Write Connection (User Power Supply Used) Figure 26.1 is an example of a serial write connection for internal vector modes (single-chip mode and internal ROM external bus mode) when the user power supply is used. The mode pins MD2, MD1, and MD0 are set to 011.
Page 545 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same as P00. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing.
Page 546: Example Of Serial Write Connection (Power Supplied From The Writer)
EXAMPLES OF MB90F428/A SERIAL WRITE CONNECTION 26.3 Example of Serial Write Connection (Power Supplied from the Writer) Figure 26.2 is an example of a serial write connection for internal vector modes (single-chip mode and internal ROM external bus mode) when power is supplied from the writer power. The mode pins MD2, MD1, and MD0 are set to 011.
Page 547 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same as P00. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing.
Page 548: Example Of Minimum Connection To The Flash Microcontroller Programmer (User Power Supply Used)
EXAMPLES OF MB90F428/A SERIAL WRITE CONNECTION 26.4 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) Figure 26.3 is an example of the minimum connection to the flash microcontroller programmer when the user power supply is used for the supply voltage of microcontroller. n Example of minimum connection to the flash microcontroller programmer (user power supply used) When each pin is set as shown below at programming to flash memory, there is no need for connections...
Page 549 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing.
Page 550: Example Of Minimum Connection To The Flash Microcontroller Programmer (Power Supplied From The Writer)
EXAMPLES OF MB90F428/A SERIAL WRITE CONNECTION 26.5 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Writer) Figure 26.4 is an example of the minimum connection to the flash microcontroller programmer when power is supplied from the writer. n Example of minimum connection to the flash microcontroller programmer (power supplied from the writer) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need not...
Page 551 MB90420/5 (A) SERIES F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing.

This manual is also suitable for:

Mb90f428a Mb90427a Mb90f428 Mb90428 Mb90428a Mb90v420 ... Show all

Fujitsu MB90420/5 (A) Series Hardware Manual

Chapter 1 General

Chapter 2 CPU

Chapter 3 Reset

Chapter 4 Clock

Chapter 5 Low-Power Consumption Mode

Chapter 6 Interrupt

Chapter 7 Mode Setting

Chapter 8 I/O Port

Chapter 9 Watchdog Timer/Time-Base Timer/Watch Timer (Sub-Clock)

Chapter 10 16-Bit Reload Timer

Quick Links

Related Manuals for Fujitsu MB90420/5 (A) Series

Summary of Contents for Fujitsu MB90420/5 (A) Series