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19.4.2 A/D Control Status Register Lower (ADCSL)
The A/D control status register lower (ADCSL) selects the conversion mode and A/D conversion channel.
n A/D control status register lower (ADCS lower)
bit 15
000020
(ADCSH)
H
R/W : Both read and write
: Initial value
8-/10-BIT A/D CONVERTER
bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
MD1
MD0
R/W R/W R/W R/W R/W R/W R/W R/W
ANE2
0
0
0
0
1
1
1
1
ANS2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
Fig. 19.5 A/D Control Status Register Lower (ADCSL)
bit 1 bit 0
ANE1
ANE0
A/D Conversion End Channel Select Bits
0
0
AN0 pin
0
1
AN1 pin
1
0
AN2 pin
1
1
AN3 pin
0
0
AN4 pin
0
1
AN5 pin
1
0
AN6 pin
1
1
AN7 pin
A/D Conversion Start Channel Select Bits
ANS1
ANS0
During
Stop
0
0
AN0 pin
0
1
AN1 pin
1
0
AN2 pin
1
1
AN3 pin
0
0
AN4 pin
0
1
AN5 pin
1
0
AN6 pin
1
1
AN7 pin
MD0
A/D Conversion Mode Select Bits
Single-shot conversion mode 1 (conversion can be
0
restarted during operation)
Single-shot conversion mode 2 (conversion cannot be
1
restarted during operation)
Continuous conversion mode (conversion cannot be
0
restarted during operation)
Pause-conversion mode (conversion cannot be restarted
1
during operation)
19-11
Initial value
00000000
B
Reading at
Reading at
Conversion in
Conversion
Pause-conversion
Mode
Channel
number of
Channel number of
channel
channel converted
currently
just previously
being
converted
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