Table of Contents
CHAPTER 14 UART0
14.3.6
Serial edge select register 0 (SES0)
Serial edge select register 0 (SES0) inverts the clock signal of the UART0 using an
inverter.The register logically inverts the shift clock signal input to the UART0 from Low
level to High level and from falling edge to rising edge, or from High level to Low level
and from rising edge to falling edge.The inversion acts on the serial clock output, too.
I serial edge select register 0 (SES0)
15
14
13
: Unused
R/W
: Read/Write
: Reset value
Table 14.3-6 Functions of serial edge select register 0 (SES0)
bit name
bit8
NT:
Clock reverse bit
bit9
Unused bits
to
bit15
398
Figure 14.3-8 serial edge select register 0 (SES0)
12
11
10
9
8
R/W
bit8
NT
0
1
The bit inverts the clock signal input to the UART0.
• Signals are inverted from Low level to High level or from High level to Low
level.
• The inversion acts on the serial clock output, too.
Read: The value is undefined.
Write: No effect
Reset value
XXXXXXX0
B
Clock inversion bit
Normal
Convert shift clock signal
Function
Table of Contents
