Operation; Sti Subroutine Content; Interrupt Latency And Interrupt Occurrences - Allen-Bradley SLC 500 Series Reference Manual
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Operation
After you download your program and enter the REM Run mode, the STI
begins operation as follows.
1. The STI timer begins timing.
2. When the STI interval expires, the STI timer is reset, the processor scan
is interrupted and the STI subroutine file is scanned.
3. If while executing the STI subroutine, another STI interrupt occurs, the
STI Pending bit (S:2/0) is set.
4. If while an STI is pending, the STI timer expires, the STI Lost bit
(S:36/9) is set. (For SLC 5/02 processors, the Overflow (S:5/10) bit is
set.)
5. When the STI subroutine scan is completed, scanning of the main
program file resumes at the point where it left off, unless an STI is
pending. In this case, the subroutine is immediately scanned again.
6. The cycle repeats.
For identification of your STI subroutine, include an INT instruction as the
first instruction on the first rung of the file.
STI Subroutine Content
The STI subroutine contains the rungs of your application logic. You can
program any instruction inside the STI subroutine except a TND, REF, or
SVC instruction. IIM or IOM instructions are needed in an STI subroutine if
your application requires immediate update of input or output points. End the
STI subroutine with an RET instruction.
JSR stack depth is limited to 3. You may call other subroutines to a level 3
deep from an STI subroutine.
Interrupt Latency and Interrupt Occurrences
Interrupt latency is the interval between the STI time-out and the start of the
interrupt subroutine. STI interrupts can occur at any point in your program,
but not necessarily at the same point on successive interrupts. The tables
below show the interaction between an interrupt and the processor operating
cycle.
Understanding Interrupt Routines
Publication 1747-RM001G-EN-P - November 2008
11-9
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