Honeywell DDP-416 Instruction Manual page 30

General purpose i/c digital computer
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Note that the enable levels for selecting the M- and Y-registers are divided into a
high and low order part to facilitate split word operations.
The high order part of the input
includes bits 1 through 7 and the low order part includes bits 8 through 16.
Since summand H is complemented relative to summand G (note polarities of inputs
from registers on LBDs 101 through 116), the absence of any input to summand H renders
it 177777
8
rather than zero.
In some algorithms, more than one register can be simulta-
neously selected for the same bits of summand H.
When this occurs, summand H becomes
the logical product (AND) of the selected registers.
If M and Mare both selected, summand
H becomes zero.
This feature is used when data is merely transferred through the sum net-
work with no arithmetic operations performed, as is the case in the interchange instructions
and others.
Intermediate Functions. - - The intermediate functions comprise three high-speed gates per
stage to produce the functions shown on Figure 2-12.
These intermediate functions are used
in the carry network and in the sum formation to be described.
Rn is also used as a source
of the assertion form of Gn, when summand His equal to 177777
8
, for the data path con-
trolled by signal ESMTS+.
Carry Network. -- This network (see Figure 2-13 and LBD 117) is a succession of stages
alternately forming the assertion and negation of the carry.
The carry network implements
the functions C
and
C
1
,
n
n-
where:
C
n
c
n-1
(G
+
H ) (G
H
+
C
+
1
) ,
and
n
n
n
n
n
Note that the ripple carry propagation and the new carry generation signals are not com-
bined, but are made available on two and sometimes three wires.
The carry signal is
required in negation form from every stage and in assertion form from at least one of any
two adjacent stages.
The inverters at the right of Figure 2-13 complete this requirement
without adding to the ripple delay.
To achieve even faster settling in the carry network it is necessary to anticipate the
ripple carry at selected stages.
This process is described with the following equations:
C7
(G7 + H7) (G7
H7
+
C8)
C 6
(G 6
+
H 6) (G 6
H 6 + C 7)
C5
(G5
+
H5) (G5
H5
+
C6)
= (G
5
+H
5
)[G
5
· H
5
+G
6
·
H
6
+(G
6
+H
6
)G
7
· H
7
+(G
6
+H
6
)(G
7
+H
7
)C
8
]
A similar anticipation is applied in the generation of the carry from stages 12, 8, and 3, as
shown on Figure 2 -14.
2-14
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