Table of Contents
U)
0
z
0
0
w
U)
o~
z
U)
er
~
w
z
...J
t-
_. w ~
we
(!)
tt:
er
...J
w
t-
er m
U)
....
~
' 0 ::>
>-
t-
z
er~
...J
w
0
laJ
(!)
er
tt:
36
34
32
30
28
26
24
22
~
20
er
18
16
547
0
10
20
30
TYPICAL
CIRCUIT DELAY OF NANO GATES
SYSTEM
OPERATING AMBIENT : +25°C
8 LOADS
I ACTIVE
40
50
Vee:
+6
VOLTS
5 LOADS
3 LOADS
I ACTIVE
I ACTIVE
/
/
60
70
80
BACK PLANE WI RING CAPACITANCE (pf)
Figure A-2.
Typical NAND Gate Circuit Delays (Sheet 2 of 3)
A-7
Table of Contents
