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fetched instruction is executed and the next instruction is fetched.
The Programmers
Reference Manual, 3C Doc. No. 130071628, contains a discussion which treats this opera-
tion in greater detail.
When the operator desires to read and/or alter the content of any memory location,
a memory access mode is initiated.
Front panel controls and indicators permit the operator
to display and alter the locations.
Consecutive locations can also be displayed and/or
altered with the proper selection of front panel controls.
CENTRAL PROCESSOR DA TA FLOW
Figure 2-9 is a simplified diagram illustrating the flow of data to and through the
central processor.
The control logic is omitted for simplicity but is discussed in later text.
Note that the D-register is the central register through which most data flow occurs,
hence its designation as the D {distribution) register.
Entry into memory, buffered by the
M-register, is possible either through the sum network to the D-register, or from the sum
network directly to the M-register.
The reader should become familiar with the mnemonics
at the inputs to the registers.
All signals with an E for the first letter are enable signals to
route data from one functional area to another.
For instance, EAS {an abbreviated form of
EASTL) means "enable the A-register to the sum network."
Other signals seen on Figure 2-9 are the SR/SL and the ENS signals.
SRA, for
instance, means "shift right to A-register." ENS means "enable the negation of the M-
register to the sum network. "
The input bus has access to the central processor through the D-register.
Control
signal EID {enable input bus to D-register) gates the input bus information into the D-
register.
The output bus requires no such control signals to gain access to the contents of
the A-register since it is always connected to the A-register.
FUNCTIONAL AREA DESCRIPTIONS
The following paragraphs contain descriptions of the column registers, the sum
network {with examples of addition and subtraction), the clock system, the P-register, the
shift counter, data transfers and operation decoding.
2-9
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