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TIMING DISTRIBUTOR PAC, MODEL CM-003
GENERAL DESCRIPTION
The timing Distributor PAC, Model CM-003 (Figure A-63 and A-64), provides
accurately timed pulse sequences for use in timing and control applications.
The CM-003
contains one control flip-flop, a 300-ns long delay line with 12 ns taps, a 50-ns long vernier
delay line with 6 ns taps, and nine inverting power amplifier output circuits.
Test points
are shown in Figure A-65.
The PAC consists of two double-sided printed circuit boards sandwiched together
for ease of mounting in a µ-BLOC.
Board A, which plugs into the connector, contains the
four delay lines (DLl through DL4) and five F-03 microcircuit power amplifiers.
The delay
lines are positioned between the two circuit boards to expose the etched side of board A for
timing jumper adjustment.
Board B contains an F-04 microcircuit flip-flop, discrete drivers, and termination
loads.
CIRCUIT FUNCTION
NOTE
The CM-003 PAC occupies two slots in a taper-
pin BLOC and three slots in a solderless-wrap
BLOC, or the end slot (position 1) in either.
Delay lines DLl through DL3 can be tapped and jumpered to the output power
amplifiers and the vernier delay line, DL4, to provide accurately timed output pulses.
Input connection points for each amplifier are located on the PAC to facilitate timing
flexibility.
Refer to Table A-1.
The de reset of the flip-flop may also be tapped from any point along DLl through
DL3 to allow recirculation of the opposite driving edge, thereby establishing fixed pulse
widths.
An ac set, a de reset, and the two outputs of the flip-flop are brought to the PAC
connector.
Delay line DL4 and its associated output power amplifiers may be interconnected
to provide pulses with a 6-ns delay resolution.
SPECIFICATIONS
Input Loading
Flip-flop de reset:
2/3 unit load
Flip-flop ac set:
1 unit load
Power amplifiers:
2 unit loads each
Delay Line (DLl through DL3)
Length:
300 ns ±5%, 24 taps, each
12. 5 ±1 ns
Minimum pulse width:
85 ns
Maximum pulse width:
330 ns
A-105
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