Table of Contents
GE M
S
EDICAL
YSTEMS
D
FC091194, R
IRECTION
5-4-4
BEP-1 Block Diagram
02
EVISION
F ro nt P anel
HD L ed
INTERNAL DRIVE BAY
HA R D DR IV E
TOP DRIVE BAY
E C G
MIDDLE DRIVE BAY
O P T IO NA L MO D
BOTTOM DRIVE BAY
C D R W
UP S B attery
Figure 5-6 CPU/Backend Processor Block Diagram (BEP-1)
Chapter 5 - Components and Functions (Theory)
P C MO T HE R B O A R D
E T HE R NE T
P CI Slo t #5
RS232 #3
RS232 #4
I2C
RS422
P C 2IP
P CI Slo t #4
UNUS E D S L O T
P CI Slo t #3
O P T IO NA L S C S I C A R D
P CI Slo t #2
UNU S E D S L O T
P CI Slo t #1
A G P V IDE O
CP U #1
JFP1
CP U #2
JW OL1
V
7 / V
7 PRO S
IVID
IVID
SLOT 7
SLOT 6
PC2IP
SLOT 5
SLOT 4
SLOT 3
SLOT 2
AG P Slot
SLOT 1
10/100bT
PARALLEL
USB1
USB2
COM1
COM2 (EXT)
P C IO MO DUL E
POW ER
S/C VIDEO OUT
SVGA OUT 2
P C IO B oa rd
Control
SVGA IN
SVGA OUT 1
RGB OUT
P C V IC B oa rd
M
ERVICE
ANUAL
5 - 15
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