Table of Contents
(Continued from preceding page)
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Data
Address Register
Bus
(low)
Name
Width
H'B0
SMR
8
H'B1
BRR
8
H'B2
SCR
8
H'B3
TDR
8
H'B4
SSR
8
H'B5
RDR
8
H'B6
SCMR
8
H'B7
H'B8
SMR
8
H'B9
BRR
8
H'BA
SCR
8
H'BB
TDR
8
H'BC
SSR
8
H'BD
RDR
8
H'BE
—
H'BF
H'C0
P1DDR
8
H'C1
P2DDR
8
H'C2
P1DR
8
H'C3
P2DR
8
H'C4
P3DDR
8
H'C5
P4DDR
8
H'C6
P3DR
8
H'C7
P4DR
8
H'C8
P5DDR
8
H'C9
P6DDR
8
H'CA
P5DR
8
H'CB
P6DR
8
H'CC
—
H'CD
P8DDR
8
H'CE
P7DR
8
H'CF
P8DR
8
H'D0
P9DDR
8
H'D1
PADDR
8
H'D2
P9DR
8
H'D3
PADR
8
Legend
SCI:
Serial communication interface
Bit 7
Bit 6
Bit 5
Bit 4
C/A/GM CHR
PE
O/E
TIE
RIE
TE
RE
TDRE
RDRF
ORER
FER/ERS PER
—
—
—
—
C/A
CHR
PE
O/E
TIE
RIE
TE
RE
TDRE
RDRF
ORER
FER
—
—
—
—
P1
DDR P1
DDR P1
DDR P1
7
6
5
P2
DDR P2
DDR P2
DDR P2
7
6
5
P1
P1
P1
P1
7
6
5
P2
P2
P2
P2
7
6
5
P3
DDR P3
DDR P3
DDR P3
7
6
5
P4
DDR P4
DDR P4
DDR P4
7
6
5
P3
P3
P3
P3
7
6
5
P4
P4
P4
P4
7
6
5
—
—
—
—
—
P6
DDR P6
DDR P6
6
5
—
—
—
—
—
P6
P6
P6
6
5
—
—
—
—
—
—
—
P8
P7
P7
P7
P7
7
6
5
—
—
—
P8
—
—
P9
DDR P9
5
PA
DDR PA
DDR PA
DDR PA
7
6
5
—
—
P9
P9
5
PA
PA
PA
PA
7
6
5
741
Bit Names
Bit 3
Bit 2
Bit 1
STOP
MP
CKS1
MPIE
TEIE
CKE1
TEND
MPB
SDIR
SINV
—
STOP
MP
CKS1
MPIE
TEIE
CKE1
PER
TEND
MPB
—
—
—
DDR P1
DDR P1
DDR P1
DDR P1
4
3
2
1
DDR P2
DDR P2
DDR P2
DDR P2
4
3
2
1
P1
P1
P1
4
3
2
1
P2
P2
P2
4
3
2
1
DDR P3
DDR P3
DDR P3
DDR P3
4
3
2
1
DDR P4
DDR P4
DDR P4
DDR P4
4
3
2
1
P3
P3
P3
4
3
2
1
P4
P4
P4
4
3
2
1
P5
DDR P5
DDR P5
DDR P5
3
2
1
DDR P6
DDR P6
DDR P6
DDR P6
4
3
2
1
P5
P5
P5
3
2
1
P6
P6
P6
4
3
2
1
—
—
—
DDR P8
DDR P8
DDR P8
DDR P8
4
3
2
1
P7
P7
P7
4
3
2
1
P8
P8
P8
4
3
2
1
DDR P9
DDR P9
DDR P9
DDR P9
4
3
2
1
DDR PA
DDR PA
DDR PA
DDR PA
4
3
2
1
P9
P9
P9
4
3
2
1
PA
PA
PA
4
3
2
1
(Continued on next page)
Bit 0
Module Name
CKS0
SCI channel 0
CKE0
MPBT
SMIF
CKS0
SCI channel 1
CKE0
MPBT
—
DDR
Port 1
0
DDR
Port 2
0
P1
Port 1
0
P2
Port 2
0
DDR
Port 3
0
DDR
Port 4
0
P3
Port 3
0
P4
Port 4
0
DDR
Port 5
0
DDR
Port 6
0
P5
Port 5
0
P6
Port 6
0
—
DDR
Port 8
0
P7
Port 7
0
P8
Port 8
0
DDR
Port 9
0
DDR
Port A
0
P9
Port 9
0
PA
Port A
0
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