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7.2 Register Descriptions
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7.2.1 Refresh Control Register (RFSHCR)
RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh
controller.
Bit
7
SRFMD
Initial value
0
Read/Write
R/W
PSRAM enable and DRAM enable
These bits enable or disable connection of pseudo-static RAM and DRAM
Self-refresh mode
Selects self-refresh mode
RFSHCR is initialized to H'02 by a reset and in hardware standby mode.
6
5
4
PSRAME
DRAME
CAS/WE
0
0
0
R/W
R/W
R/W
Strobe mode select
Selects 2CAS or 2WE strobing of DRAM
150
3
2
M9/M8
RFSHE
0
0
R/W
R/W
Reserved bit
Refresh pin enable
Enables refresh signal output
from the refresh pin
Address multiplex mode select
Selects the number of column address bits
1
0
—
RCYCE
1
0
—
R/W
Refresh cycle
enable
Enables or
disables
insertion of
refresh cycles
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