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14.3.4 Register Settings
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Table 14-3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 should always be set to the indicated value. The settings of the other bits will be described in
this section.
Table 14-3 Register Settings in Smart Card Interface
1
Register
Address*
SMR
H'FFB0
BRR
H'FFB1
SCR
H'FFB2
TDR
H'FFB3
SSR
H'FFB4
RDR
H'FFB5
SCMR
H'FFB6
Notes: — Unused bit.
1. Lower 16 bits of the address.
2. When the GM of the SMR is set at 0, be sure the CKE1 bit is 0.
Serial Mode Register (SMR) Settings: In regular smart card interface mode, set the GM bit at 0.
In regular smart card mode, clear the GM bit to 0. In GSM mode, set the GM bit to 1. Clear the
O/E bit to 0 if the smart card uses the direct convention. Set the O/E bit to 1 if the smart card uses
the inverse convention. Bits CKS1 and CKS0 select the clock source of the built-in baud rate
generator. See section 14.3.5, Clock.
Bit Rate Register (BRR) Settings: This register sets the bit rate. Equations for calculating the
setting are given in section 14.3.5, Clock.
Serial Control Register (SCR): The TIE, RIE, TE, and RE bits have their normal serial
communication functions. For details, see section 13, Serial Communication Interface. The CKE1
and CKE0 bits select clock output. When the GM bit of the SMR is cleared to 0, to disable clock
output, clear this bit to 00. To enable clock output, set this bit to 01. When the GM bit of the SMR
is set to 1, clock output is enabled. Clock output is fixed at high or low.
Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the
SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and
SINV bits to 1. To use the smart card interface, set the SMIF bit to 1.
Bit 7
Bit 6
Bit 5
GM
0
1
BRR7
BRR6
BRR5
TIE
RIE
TE
TDR7
TDR6
TDR5
TDRE
RDRF
ORER
RDR7
RDR6
RDR5
—
—
—
508
Bit 4
Bit 3
Bit 2
O/E
1
0
BRR4
BRR3
BRR2
RE
0
0
TDR4
TDR3
TDR2
ERS
PER
TEND
RDR4
RDR3
RDR2
—
SDIR
SINV
Bit 1
Bit 0
CKS1
CKS0
BRR1
BRR0
2
CKE1*
CKE0
TDR1
TDR0
0
0
RDR1
RDR0
—
SMIF
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