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SHIFT RIGHT ONE (SRl) BR,B CYCLE.
This instruction performs the Shift Right One (SRl)
function in one word time (Figure 11):
1.
At the very start of the instruction cycle (actually
~lightly
before) the address of the
next instruction is transferred from P to L. After this takes place, P is incremented
by plus 1.
2.
The L.:.register is transferred to the memory address lines.
3.
When the instruction is read out, it is transferred from
M
to
N
where, in this example,
a general instruction (SRl BR,B) is decoded.
4.
After the instruction is decoded, the contents of B are transferred to Y.
5.
Simultaneously with step 3, the contents of R are transferred to Y.
6.
The logical OR of B and R is done in Y and transferred to the arithmetic unit.
7.
The
ari~hmeti~
unit performs a SRl function on Y and transfers the result to Z.
· . 8.
The result in Z is transferred to B.
9.
Simultaneously with steps 3, 4, 5, 6, and 7, the contents of M are being regenerated
by the memory drivers.
10.
The branch flip-flops store the plus, zero, and even conditions of the new contents
of B.
BllAllCB n.IP-FLOPS
PLUS
Zl!IO
EVIN
A
REGISTER
B
REGISTER
8
I
_J
REGISTER
COUNTER
COUNTER
ADDRESS
10
z
DllVDS
-1
c
I
Q
p
HEK>RY
~~-1~8 ~~~ts~ ~~~---~1 ~-.---14~ ·-~~~ ~'--~~--"'T"l~--L---s~1s--+-_._~
I
I
I
7
REcPV!
DATA
L-S
21
I
4
,--
- -
-
---,
I
EXTERNAL
STATUS
L-S
10
I
!n~~s
~
Dl!COD!
128
I
I
II
REGISTER
llAGNITIC
cou:
MllllJ.Y
REGISTER
l8
Ml!li)RY
I
DRIVDJ
18
I
I
I
I
9
I
3 - - - - - - - '
IllSDT
SWITCBIS
11
ilITllHETIC
Y
REGISTER
Figure 11. Detailed Block Diagram DATANET-30 Shift Right 1 Receive Lines
to B-register (SRl BR, B)
l8
6
11
rID&u&I~[Euc:J ~®------------
I-21
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