Receive
and Xmit.
Data Lines
t
GJ···~
Channels
Buffer Selector
Upper Data Bus
Working
Registers
Memory
Lower Data Bus
Data
Register
• • •
.[J
Channels
Controller Selector
Tape
High-Speed Peripherals
Figure 5. Basic Block Diagram
Z Drivers
Arithmetic
Unit
Y-Register
lID&u&~~uc:J ~@------------
1-9
