Table of Contents
Test Code
Target Device(s)
T056
CPU D-Cache
Burst RAM Wrap
Test
T057
CPU D-Cache
Integrity Test
Hardware Status Register and System Control Diagnostics
T060
WDT Pending Test
T061
DC_FAIL Pending
Test
T062
Struck IRQ0 Test
T063
Stuck ICP Timer
Interrupt Test
T064
Stuck ICP Comm
Interrupt Test
T065
SYS_FAIL Assert
Test
T068
Stuck IRQ7
R400
Experion PKS Series A Fieldbus Interface Module User's Guide
July 2010
8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
Failure Modes
correctly. Only uses the memory
test area, so just shows that the
data cache is enabled and at least
partially functional.
CPU, RAM, UPMB
Verify that the RAM burst wraps
on address modulus 4. Perform on
both RAM chips. Only uses the
memory test area.
CPU
The checksum of the boot code is
repeated with Data Cache
enabled. The test is timed. If the
data cache is not working
properly, the checksum will fail or
the test will take too long.
CPU, PLD
Verifies that the watch dog timer
timeout pending signal is not
asserted.
CPU, PLD
Verifies that the backplane
DC_FAIL pending signal is not
asserted.
CPU, PLD, pullup
Verifies the IRQ0 is not asserted.
If it is asserted, fails in this test, if
WDT Pending and DC_FAIL
Pending are not asserted.
CPU, PLD, pullup,
Verifies that the ICP timer interrupt
ICP ASIC
IRQ2 is not asserted.
CPU, PLD, pullup,
Verifies that the ICP comm.
ICP ASIC
Interrupt IRQ3 is not asserted.
CPU, PLD,
Verifies that SYS_FAIL status is
Backplane, other
not stuck . This means it is not
modules
asserted for longer than a to be
determined period necessary to
accommodate other modules'
tests.
CPU, PLD
Verifies that interrupt from
Honeywell
Function
353
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