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Asus AAEON BOXER-6616 User Manual

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BOXER-6616
Fanless Embedded Box PC
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User's Manual 8
Ed
Last Updated: June 1, 2023
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Summary of Contents for Asus AAEON BOXER-6616

  • Page 1 BOXER-6616 Fanless Embedded Box PC User’s Manual 8 Last Updated: June 1, 2023...
  • Page 2 Copyright Notice This document is copyrighted, 2023. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel®, Pentium®, and Celeron® are registered trademarks of Intel ⚫ Corporation All other product names or trademarks are properties of their respective owners. Preface...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity BOXER-6616 Wallmount Bracket Screw Package 3 Pin DC-In Power Connector If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 外壳 ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ..................1 Specifications ......................2 Block Diagram ......................4 Chapter 2 – Hardware Information ..................5 Dimensions ......................6 Jumpers and Connectors ..................7 List of Jumpers ......................8 2.4.1 Clear CMOS Jumper (JP1) ..............8 2.4.2 LVDS Power &...
  • Page 12 Hard Disk Drive Installation ................27 RAM Installation ....................29 Mini Card Installation .................... 31 Wallmount Installation ..................33 Chapter 3 - AMI BIOS Setup ....................34 System Test and Initialization ................35 AMI BIOS Setup ....................36 Setup Submenu: Main ..................37 Setup Submenu: Advanced ................
  • Page 13 Chapter 4 – Drivers Installation ................... 59 Drivers Download and Installation..............60 Appendix A - Watchdog Timer Programming..............62 Watchdog Timer Initial Program ............... 63 Appendix B - I/O Information ....................68 I/O Address Map ....................69 Memory Address Map ..................72 IRQ Mapping Chart .....................

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Intel® Pentium® Processor N4200, 2.5 GHz Intel® Celeron® Processor N3350, 2.4 GHz Chipset Intel® System on Chip System Memory DDR3L 1866MHz SODIMM x 1 (Max. 8GB, up to 1600MHz) (Note: Memory with frequency greater than 1600MHz will automatically fix to 1600MHz) Display Interface HDMI x 1, up to 2048 x 1152 VGA x 1, up to 2048 x 1152...
  • Page 16 System Indicator Power LED HDD active LED OS Support Windows® 10 IoT Ent LTSC 2019 64-bit Ubuntu 16.04 and later Note: To avoid random non-booting issue caused by the incompatibility of Intel® Pentium® Processor N Series with certain unstable 1866MHz memories, memory with frequency greater than 1600MHz will automatically fix to 1600MHz, while memory that runs at a speed lower than 1600MHz will maintain its original speed.

  • Page 17: Block Diagram

    Power Supply DC Input 9V ~ 24V with 3-pin Terminal Block Block Diagram Chapter 1 – Product Specifications...

  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 19: Dimensions

    Dimensions Chapter 2 – Hardware Information...

  • Page 20: Jumpers And Connectors

    Jumpers and Connectors Chapter 2 – Hardware Information...

  • Page 21: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the system’s jumpers that you can configure for your application. Label Function Clear CMOS Jumper LVDS Power & Backlight Power Selection LVDS Backlight Control Selection Touch Screen Lines 4, 5, 8 Wire Selection COM 5 RI Voltage Selection COM 6 RI Voltage Selection JP11...

  • Page 22: Lvds Backlight Control Selection (Jp4)

    2.4.3 LVDS Backlight Control Selection (JP4) 2.4.4 Touch Screen Lines 4, 5, 8 Wire Selection (JP5) 2.4.5 COM 5 RI Voltage Selection (JP7) 2.4.6 COM 6 RI Voltage Selection (JP8) Chapter 2 – Hardware Information...

  • Page 23: Front Panel (Jp11)

    2.4.7 Front Panel (JP11) Function EXT_PWRBTN# FP_HDLED- FP_HDLED+ FP_SPKR- +V5S PWRLED+ HWRST# Chapter 2 – Hardware Information...

  • Page 24: List Of Connectors

    List of Connectors Please refer to the table below for all of the system’s connectors that you can configure for your application Label Function RTC Battery External Power Input LVDS Backlight LVDS CN13 UIM Card Push-Push (Optional) CN14 SATA HDD CN15 +5V/+12V Output for SATA HDD CN16...

  • Page 25: Rtc Battery (Cn1)

    2.5.1 RTC Battery (CN1) Signal Level Pin Name Signal Type +V3.3A_RTC +3.3V 2.5.2 External Power Input (CN2) Pin Name Signal Type Signal Level PWR_IN +9V~+24V Chapter 2 – Hardware Information...

  • Page 26: Uim Card Socket (Push-Push Type) (Cn13)

    2.5.3 UIM Card Socket (Push-Push Type) (CN13) Pin Name Signal Type Signal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA Chapter 2 – Hardware Information...

  • Page 27: Sata Port (Cn14)

    2.5.4 SATA Port (CN14) Pin Name Signal Type Signal Level SATA_TXP0 DIFF SATA_TXN0 DIFF SATA_RXN0 DIFF SATA_RXP0 DIFF 2.5.5 SATA Power Connector (CN15) Signal Signal +3.3VDC +3.3VDC +3.3VDC +5VDC +5VDC Chapter 2 – Hardware Information...

  • Page 28: Half Size Mini Card Slot (Cn37)

    Signal Signal +5VDC +12VDC +12VDC +12VDC 2.5.6 Half Size Mini Card Slot (CN37) Pin Name Signal Type Signal Level PCIE_WAKE3_MP2_N_3 +V3.3_MINICARD_MSA +3.3V +V1.5S +1.5V MPCIE2_CLKREQ# CLK_PCIE_MPCIE2_N DIFF Chapter 2 – Hardware Information...
  • Page 29 Pin Name Signal Type Signal Level CLK_PCIE_MPCIE2_P DIFF W_DISABLE1# +3.3V BUF_PLT_RST# +3.3V PCIE_RXN3_R DIFF +V3.3_MINICARD_MSA +3.3V PCIE_RXP3_R DIFF +V1.5S +1.5V SMB_CLK_A +3.3V PCIE_TXN3_R DIFF SMB_DATA_A +3.3V PCIE_TXP3_R DIFF USB_DN7_MPCIE DIFF Chapter 2 – Hardware Information...
  • Page 30 Pin Name Signal Type Signal Level USB_DP7_MPCIE DIFF +V3.3_MINICARD_MSA +3.3V +V3.3_MINICARD_MSA +3.3V +V1.5S +1.5V +V3.3_MINICARD_MSA +3.3V Chapter 2 – Hardware Information...

  • Page 31: Full Size Mini Card Slot (Cn16)

    2.5.7 Full Size Mini Card Slot (CN16) Pin name Signal Type Signal Level PCIE_WAKE2_MP1_N_ +V3.3A +3.3V +V1.5S +1.5V MPCIE1_CLKREQ# UIM_PWR UIM_DAT CLK_PCIE_MPCIE1_N DIFF UIM_CLK CLK_PCIE_MPCIE1_P DIFF UIM_RST UIM_VPP Chapter 2 – Hardware Information...
  • Page 32 Pin name Signal Type Signal Level W_DISABLE0# +3.3V BUF_PLT_RST# +3.3V PCIE_RXN2 DIFF +V3.3A +3.3V PCIE_RXP2 DIFF +V1.5S +1.5V SMB_CLK_A +3.3V PCIE_TXN2 DIFF SMB_DATA_A +3.3V PCIE_TXP2 DIFF USB_DN6 DIFF USB_DP6 DIFF +V3.3A +3.3V +V3.3A +3.3V Chapter 2 – Hardware Information...

  • Page 33: Lan 1 + Usb 3.0 X 2 (Cn40)

    Pin name Signal Type Signal Level +V1.5S +1.5V +V3.3A +3.3V 2.5.8 LAN 1 + USB 3.0 x 2 (CN40) Pin name Signal Type Signal Level LAN1_MDI0P DIFF LAN1_MDI0N DIFF LAN1_MDI1P DIFF LAN1_MDI1N DIFF LAN1_MDI2P DIFF LAN1_MDI2N DIFF Chapter 2 – Hardware Information...
  • Page 34 Pin name Signal Type Signal Level LAN1_MDI3P DIFF LAN1_MDI3N DIFF +V5A_USB_0 USBD0- DIFF USBD0+ DIFF USB3_RX0_CON_N DIFF USB3_RX0_CON_P DIFF USB3_TX0_CON_N DIFF USB3_TX0_CON_P DIFF +V5A_USB_1 USBD1- DIFF USBD1+ DIFF USB3_RX1_CON_N DIFF USB3_RX1_CON_P DIFF USB3_TX1_CON_N DIFF USB3_TX1_CON_P DIFF Chapter 2 – Hardware Information...

  • Page 35: Lan 2 + Usb 3.0 X 2 (Cn41)

    2.5.9 LAN 2 + USB 3.0 x 2 (CN41) Pin name Signal Type Signal Level LAN2_MDI0P DIFF LAN2_MDI0N DIFF LAN2_MDI1P DIFF LAN2_MDI1N DIFF LAN2_MDI2P DIFF LAN2_MDI2N DIFF LAN2_MDI3P DIFF LAN2_MDI3N DIFF +V5A_USB_2 USBD2- DIFF USBD2+ DIFF USB3_RX2_CON_N DIFF USB3_RX2_CON_P DIFF USB3_TX2_CON_N DIFF Chapter 2 –...

  • Page 36: Vga + Hdmi Port (Cn53)

    Pin name Signal Type Signal Level USB3_TX2_CON_P DIFF +V5A_USB_3 USBD3- DIFF USBD3+ DIFF USB3_RX3_CON_N DIFF USB3_RX3_CON_P DIFF USB3_TX3_CON_N DIFF USB3_TX3_CON_P DIFF 2.5.10 VGA + HDMI Port (CN53) Pin name Signal Type Signal Level GREEN BLUE Chapter 2 – Hardware Information...
  • Page 37 Pin name Signal Type Signal Level +V5S_DISP CRT_PLUG VGA_DDCDATA HSYNC VSYNC VGA_DDCCLK HDMI_DATA2_P DIFF HDMI_DATA2_N DIFF HDMI_DATA1_P DIFF HDMI_DATA1_N DIFF HDMI_DATA0_P DIFF HDMI_DATA0_N DIFF HDMI_CLK_C_P DIFF HDMI_CLK_C_N DIFF HDMI_SCL HDMI_SDA +V5S_HDMI_CON HDMI_HPD Chapter 2 – Hardware Information...

  • Page 38: Com Port 1 ~ 6 (Com)

    2.5.11 COM Port 1 ~ 6 (COM) Pin name Signal Type Signal Level ±9V ±9V ±9V RS-485 (COM 5/COM 6 Only) Pin name Signal Type Signal Level RS485- ±5V RS485+ ±5V NC/5V/12V Chapter 2 – Hardware Information...
  • Page 39 RS-422 (COM 5/COM 6 Only) Pin name Signal Type Signal Level RS422- ±5V RS422+ ±5V RS422+ RS422- NC/5V/12V Chapter 2 – Hardware Information...

  • Page 40: Hard Disk Drive Installation

    Hard Disk Drive Installation Step 1: Remove the baseplate as instructed below. Step 2: Place the HDD on the bracket plate. Chapter 2 – Hardware Information...
  • Page 41 Step 3: Tighten the screws at the back to secure the HDD. Step 4: Connect the SATA and power cables to the HDD, attach the HDD assembly to the baseplate. Chapter 2 – Hardware Information...

  • Page 42: Ram Installation

    RAM Installation Step 1: Remove the baseplate as instructed below. Step 2: Insert the RAM into the RAM slot. Chapter 2 – Hardware Information...
  • Page 43 Step 3: Push down to secure the RAM. Chapter 2 – Hardware Information...

  • Page 44: Mini Card Installation

    Mini Card Installation Step 1: Remove the baseplate as instructed below. Step 2: Insert the Mini-Card into the Mini-Card slot. Chapter 2 – Hardware Information...
  • Page 45 Step 3: Push down to secure the Mini-Card. Chapter 2 – Hardware Information...

  • Page 46: Wallmount Installation

    Wallmount Installation We suggest using this screw. Chapter 2 – Hardware Information...

  • Page 47: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 48: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 49: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press ...

  • Page 50: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 51: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 52: Trusted Computing

    3.4.1 Trusted Computing Options Summary Security Device Support Disable Optimal Default, Failsafe Default Enable Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. Chapter 3 – AMI BIOS Setup...

  • Page 53: Cpu Configuration

    3.4.2 CPU Configuration Options Summary Active Processor Cores Disabled Optimal Default, Failsafe Default Enabled Number of cores to enable in each processor package. Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.
  • Page 54 Options Summary Turbo Mode. Boot performance mode Max performance Optimal Default, Failsafe Default Max battery Select the performance state that the BIOS will set before OS handoff. Power Limit 1 Enable Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Power Limit 1. C-states Disabled Optimal Default, Failsafe Default...

  • Page 55: Sata Drives

    3.4.3 SATA Drives Options Summary Chipset SATA Enable Optimal Default, Failsafe Default Disable Enable or Disable the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). Port Enable Optimal Default, Failsafe Default Disable Enable or Disable SATA Port.

  • Page 56: Hardware Monitor

    3.4.4 Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 57: Sio Configuration

    3.4.5 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 58: Serial Port 1 Configuration

    3.4.5.1 Serial Port 1 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8; IRQ=4; IO=2F8; IRQ=3; Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 59: Serial Port 2 Configuration

    3.4.5.2 Serial Port 2 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8; IRQ=3; IO=3F8; IRQ=4; Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 60: Serial Port 3 Configuration

    3.4.5.3 Serial Port 3 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3E8; IRQ=11; IO=2E8; IRQ=11; Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 61: Serial Port 4 Configuration

    3.4.5.4 Serial Port 4 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2E8; IRQ=11; IO=3E8; IRQ=11; Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 62: Serial Port 5 Configuration

    3.4.5.5 Serial Port 5 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2D0; IRQ=11; IO=2C0; IRQ=11; Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 63: Serial Port 6 Configuration

    3.4.5.6 Serial Port 6 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2C0; IRQ=11; IO=2D0; IRQ=11; Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 64: Power Management

    3.4.6 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode. Restore AC Power Loss Last State Optimal Default, Failsafe Default Power On Power Loss RTC wake system from S5 Disabled Optimal Default, Failsafe Default Fixed Time Dynamic Time Enable or disable System wake on alarm event.

  • Page 65: Dynamic Digital Io Configuration

    3.4.7 Dynamic Digital IO Configuration Options Summary DIO[1:4] Input Output Optimal Default, Failsafe Default Set DIO as Input or Output. DIO[1:4] Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is Output. DIO[5:8] Input Optimal Default, Failsafe Default Output Set DIO as Input or Output.

  • Page 66: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 67: North Bridge

    3.5.1 North Bridge Options Summary DCMT Total Gfx Mem 128M 256M Optimal Default, Failsafe Default Select DVMT5.0 Total Graphics Memory size used by the Internal Graphics Device. Chapter 3 – AMI BIOS Setup...

  • Page 68: South Bridge

    3.5.2 South Bridge Options Summary HD-Audio Support Disable Enable Optimal Default, Failsafe Default Enable/Disable HD-Audio Support. Mini-Card 1 Speed Auto Optimal Default, Failsafe Default Gen 1 Gen 2 Configure PCIe Speed. Mini-Card 2 Speed Auto Optimal Default, Failsafe Default Gen 1 Gen 2 Configure PCIe Speed.

  • Page 69: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 70: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Quiet Boot option. Network Stack Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. Chapter 3 – AMI BIOS Setup...

  • Page 71: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 72: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 73: Drivers Download And Installation

    Drivers Download and Installation Drivers for the BOXER-6616 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/fanless-embedded-computers-boxer-6616 Download the driver(s) you need and follow the steps below to install them. Step 1 – Install Chipset Driver Open the Step1 - Chipset folder and followed by SetupChipset.exe file Follow the instructions Drivers will be installed automatically...
  • Page 74 Step 4 – Install LAN Driver Open the Step4 - LAN folder and select your OS Open the .exe file in the folder Follow the instructions Drivers will be installed automatically Step 5 – Install Audio Driver Open the Step5 - Audio folder and followed by .exe file Follow the instructions Drivers will be installed automatically Step 6 –...

  • Page 75: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 76: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1: Super I/O Relative Register Table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2: Watchdog Relative Register Table Register BitNum Value...
  • Page 77 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 78 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 79 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 80 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...

  • Page 81: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 82: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 83 Appendix B – I/O Information...
  • Page 84 Appendix B – I/O Information...

  • Page 85: Memory Address Map

    Memory Address Map Appendix B – I/O Information...
  • Page 86 Appendix B – I/O Information...

  • Page 87: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 88 Appendix B – I/O Information...
  • Page 89 Appendix B – I/O Information...
  • Page 90 Appendix B – I/O Information...
  • Page 91 Appendix B – I/O Information...
  • Page 92 Appendix B – I/O Information...
  • Page 93 Appendix B – I/O Information...
  • Page 94 Appendix B – I/O Information...
  • Page 95 Appendix B – I/O Information...

  • Page 96: Appendix C - Digital I/O Ports

    Appendix C Appendix C – Digital I/O Ports...

  • Page 97: Electrical Specifications For Digital I/O Ports

    Electrical Specifications for Digital I/O Ports GPIO80 DIO_0 GPIO81 DIO_1 GPIO82 DIO_2 GPIO83 DIO_3 GPIO84 DIO_4 GPIO85 DIO_5 GPIO86 DIO_6 GPIO87 DIO_7 Appendix C – Digital I/O Information...

  • Page 98: Dio Programming

    DIO Programming The BOXER-6616 utilizes FINTEK F81966 chipset as its Digital I/O controller. Below are the procedures to complete its configuration. AAEON initial DI/O program is also attached for developing customized program for your application. There are three steps to complete the configuration setup: (1) Enter the MB PnP Mode (2) Modify the data of configuration registers (3) Exit the MB PnP Mode.

  • Page 99: Digital I/O Register

    Digital I/O Register Table 1: Super I/O Relative Register Table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2: Digital Input Relative Register Table Register BitNum Value...

  • Page 100: C.4 Digital I/O Sample Program

    C.4 Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 101 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 102 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 103 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Information...
  • Page 104 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 105 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

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