Table of Contents
ADC/Interface Section
A16 Assembly Fast ADC Circuits (8560E with Option 007)
Table 7-12
LP/Q Truth Table
Mode
12MHz
SAMPLE
POS
PEAK
NEG
PEAK
(Pit)
Clocking
Peak/Pit
Sample
32 K-Byte Static RAM
Refer to function block K of the A16 fast ADC assembly schematic
diagram in the HP 8560 E-Series Component Level Information.
The static RAM stores the flash ADC samples that are taken when the
fast ADC circuitry is in the "write" mode. When not in the "write" mode,
the static RAM is read by the CPU on the A2 controller assembly to
retrieve the fast ADC data.
The 8-bit Q bus connects the outputs of latch U30 to the data port of
static RAM U32.
392
LP/Q
12M_SEL SCLK-1
L
H
X
L
X
X
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
H
L
L
L
L
H
LSAMPLE LPEAK
P_LO
X
X
X
L
X
X
H
L
L
H
L
H
H
L
L
H
H
L
X
H
H
H
H
L
H
X
X
P_HI
X
X
H
L
L
H
L
L
X
Chapter 7
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Table of Contents
Troubleshooting
