Table of Contents
5. I/O Ports
5.6 Port P7 (P77 to P70)
5.6 Port P7 (P77 to P70)
Port P7 is an 8-bit input/output port which is also used as a segment pins of LCD.
When used as input port, the respective output latch (P7DR) should be set to "1".
During reset, the P7DR is initialized to "1".
When used as a segment pins of LCD, the respective bit of P7LCR should be set to "1". When used as an output
port, the respective P7LCR bit should be set to "0".
P7 port output latch (P7DR) and P7 port terminal input (P7PRD) are located on their respective address.
When read the output latch data, the P7DR should be read and when read the terminal input data, the P7PRD reg-
ister should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is
read.
Port P7 control register
P7DR
P77
(0007H)
SEG8
R/W
P7LCR
(002BH)
P7LCR
P7PRD
(000DH)
P77
Read only
ST P
UTEN
P7LCRi
P7LCRi input
Data input (P7PRD)
Data input (P7DR)
Data output (P7DR)
LCD data output
7
6
5
4
P76
P75
P74
SEG9
SEG10
SEG11
7
6
5
4
Port P7/segment output control
(set for each bit individually)
7
6
5
4
P76
P75
P74
D
Q
D
Q
utput latch
Figure 5-7 Port P7
3
2
1
P73
P72
P71
SEG12
SEG13
SEG14
3
2
1
0: P7 input/output port
1: Segment output
3
2
1
P73
P72
P71
Page 58
TMP86PM29BUG
P7i
to
Note: i = 7
0
0
P70
(Initial value: 1111 1111)
SEG15
0
(Initial value: 0000 0000)
0
P70
R/W
Table of Contents
