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10. 8-Bit TimerCounter (TC5, TC6)
10.1 Configuration
10.3.8 Warm-Up Counter Mode
In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a
16-bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency to
low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR to 0. If not fixed, the
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG6 and 5 are used for match
Note 3: i = 5, 6
10.3.8.1 Low-Frequency Warm-up Counter Mode
is obtained. Before starting the timer, set SYSCR2 to 1 to oscillate the low-frequency clock.
When a match between the up-counter and the timer register (TTREG6, 5) value is detected after the timer
is started by setting TC6CR to 1, the counter is cleared by generating the INTTC6 interrupt
request. After stopping the timer in the INTTC6 interrupt service routine, set SYSCR2 to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2 to
0 to stop the high-frequency clock.
Table 10-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Example :After checking low-frequency clock oscillation stability with TC6 and 5, switching to the SLOW1 mode
PINTTC6:
VINTTC6:
pulses.
detection and lower 8 bits are not used.
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
Minimum Time Setting
(TTREG6, 5 = 0100H)
7.81 ms
SET
(SYSCR2).6
LD
(TC5CR), 43H
LD
(TC6CR), 05H
LD
(TTREG5), 8000H
DI
SET
(EIRH). 4
EI
SET
(TC6CR).3
:
CLR
(TC6CR).3
SET
(SYSCR2).5
CLR
(SYSCR2).7
RETI
:
DW
PINTTC6
: SYSCR2
: Sets TFF5=0, source clock fs, and 16-bit mode.
: Sets TFF6=0, and warm-up counter mode.
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
←
: IMF
0
: Enables the INTTC6.
←
: IMF
1
: Starts TC6 and 5.
:
: Stops TC6 and 5.
: SYSCR2
(Switches the system clock to the low-frequency clock.)
: SYSCR2
:
: INTTC6 vector table
Page 118
,
and
pins may output
PDOi
PWMi
PPGi
Maximum Time Setting
(TTREG6, 5 = FF00H)
1.99 s
←
1
←
1
←
0 (Stops the high-frequency clock.)
TMP86PM29BUG
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