Table of Contents
3. Interrupt Control Circuit
The TMP86PM29BUG has a total of 19 interrupt sources excluding reset, of which 3 source levels are multi-
plexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest
are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Factors
Internal/External
(Reset)
Internal
INTSWI (Software interrupt)
INTUNDEF (Executed the undefined instruction
Internal
interrupt)
Internal
INTATRAP (Address trap interrupt)
Internal
INTWDT (Watchdog timer interrupt)
External
INT0
External
INT1
Internal
INTTBT
External
INT2
Internal
INTTC
Internal
INTRXD
Internal
INTSIO
Internal
INTTXD
Internal
INTTC4
Internal
INTTC6
Internal
INTADC
External
INT3
Internal
INTTC3
External
INT5
Internal
INTTC5
Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Inter-
rupt Source Selector (INTSEL)).
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 to "0" (It is set for the "reset request" after reset is
cancelled). For details, see "Address Trap".
Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1 to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
3.1 Interrupt latches (IL15 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
fined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to "0" during reset.
The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" indi-
vidually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt
latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions
such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if inter-
rupt is requested while such instructions are executed.
Enable Condition
Non-maskable
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF• EF4 = 1, INT0EN = 1
IMF• EF5 = 1
IMF• EF6 = 1
IMF• EF7 = 1
IMF• EF8 = 1
IMF• EF9 = 1, IL9ER = 0
IMF• EF9 = 1, IL9ER = 1
IMF• EF10 = 1
IMF• EF11 = 1
IMF• EF12 = 1
IMF• EF13 = 1
IMF• EF14 = 1, IL14ER = 0
IMF• EF14 = 1, IL14ER = 1
IMF• EF15 = 1, IL15ER = 0
IMF• EF15 = 1, IL15ER = 1
Page 35
TMP86PM29BUG
Interrupt
Vector
Priority
Latch
Address
–
FFFE
1
–
FFFC
2
–
FFFC
2
IL2
FFFA
2
IL3
FFF8
2
IL4
FFF6
5
IL5
FFF4
6
IL6
FFF2
7
IL7
FFF0
8
IL8
FFEE
9
IL9
FFEC
10
IL10
FFEA
11
IL11
FFE8
12
IL12
FFE6
13
IL13
FFE4
14
IL14
FFE2
15
IL15
FFE0
16
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