Toshiba TLCS-870/C1 Series Manual
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Toshiba TLCS-870/C1 Series Manual

Toshiba TLCS-870/C1 Series Manual

8 bit microcontroller
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查询TMP89FM42供应商
捷多邦，专业PCB打样工厂，24小时加急出货
8 Bit Microcontroller
TLCS-870/C1 Series
TMP89FM42
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Summary of Contents for Toshiba TLCS-870/C1 Series

  • Page 1 查询TMP89FM42供应商 捷多邦，专业PCB打样工厂，24小时加急出货 8 Bit Microcontroller TLCS-870/C1 Series TMP89FM42...
  • Page 2 It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
  • Page 3 Revision History Date Revision 2007/10/25 First Release 2007/11/3 Contents Revised...

  • Page 5: Table Of Contents

    Table of Contents TMP89FM42 Features ............1 Pin Assignment .
  • Page 6 3. Interrupt Control Circuit Configuration ........... . . 49 Interrupt Latches (IL25 to IL3) .
  • Page 7 Function............79 7.
  • Page 8 12. Time Base Timer (TBT) 12.1 Time Base Timer ..........137 12.1.1 Configuration ............................
  • Page 9 14.4.2.2 Operation 14.4.2.3 Double buffer 14.4.3 8-bit pulse width modulation (PWM) output mode ................180 14.4.3.1 Setting 14.4.3.2 Operations 14.4.3.3 Double buffer 14.4.4 8-bit programmable pulse generate (PPG) output mode ..............185 14.4.4.1 Setting 14.4.4.2 Operation 14.4.4.3 Double buffer 14.4.5 16-bit timer mode ..........................
  • Page 10 16.12.1 Parity error ............................225 16.12.2 Framing Error............................ 226 16.12.3 Overrun error ............................ 227 16.12.4 Receive Data Buffer Full........................230 16.12.5 Transmit busy flag ........................... 231 16.12.6 Transmit Buffer Full .......................... 231 16.13 Receiving Process ..........232 16.14 AC Properties .
  • Page 11 18.4.8 Interrupt service request and release ....................274 18.4.9 Setting of serial bus interface mode ....................274 18.4.10 Software reset........................... 274 18.4.11 Arbitration lost detection monitor ...................... 275 18.4.12 Slave address match detection monitor.................... 276 18.4.13 GENERAL CALL detection monitor ....................277 18.4.14 Last received bit monitor........................
  • Page 12 21.3.4 Product ID entry ..........................314 21.3.5 Product ID exit ............................ 314 21.3.6 Security program ..........................314 21.4 Toggle Bit (D6) ..........314 21.5 Access to the Flash Memory Area.
  • Page 13 22.14.7 Product ID code output command (0xC0) ..................367 22.14.8 Flash memory status output command (0xC3) ................. 368 22.14.9 Mask ROM emulation setting command (0xD0) ................368 22.14.10 Flash memory security setting command (0xFA)................368 22.15 Revision History..........369 23.

  • Page 15: Tmp89Fm42

    • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patents or other rights of TOSHIBA or the third parties.
  • Page 16 1.1 Features TMP89FM42 10. 8-bit timer counter: 4 ch - Timer, Event Counter, PWM, PPG OUTPUT modes - Usable as a 16-bit timer, 12-bit PWM output and 16-bit PPG output by the cascade connection of two channels. 11. Real time clock 12.

  • Page 17: Pin Assignment

    TMP89FM42 1.2 Pin Assignment (TXD1/RXD1) P91 P41(AIN1/KWI1) P40(AIN0/KWI0) /TC02) P80 PWM02 PPG02 VAREF/AVDD /TC03) P81 PWM03 PPG03 /TC00) P70 PWM00 PPG00 /TC01) P71 PWM01 PPG01 P25(SCLK0) /TCA0) P72 PPGA0 /TCA1) P73 P24(SCL0/SI0) PPGA1 (SO0/RXD0/TXD0) PB4 P23(SDA0/SO0) (SI0/TXD0/RXD0) PB5 P22(SCLK0) (SCLK0) PB6 P21(RXD0/TXD0/SI0/OCDIO) P20(TXD0/RXD0/SO0/OCDCK) Figure 1-1 Pin Assignment...

  • Page 18: Block Diagram

    1.3 Block Diagram TMP89FM42 1.3 Block Diagram Figure 1-2 Block Diagram...

  • Page 19: Pin Names And Functions

    TMP89FM42 1.4 Pin Names and Functions The TMP89FM42 has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin func- tions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name Input/Output Functions...
  • Page 20 1.4 Pin Names and Functions TMP89FM42 Table 1-1 Pin Names and Functions(2/3) Pin Name Input/Output Functions PORT45 AIN5 Analog input 5 KWI5 Key-on wake-up input 5 PORT44 AIN4 Analog input 4 KWI4 Key-on wake-up input 4 PORT43 AIN3 Analog input 3 KWI3 Key-on wake-up input 3 PORT42...
  • Page 21 TMP89FM42 Table 1-1 Pin Names and Functions(3/3) Pin Name Input/Output Functions PORT90 TXD1 UART data output 1 RXD1 UART data input 1 PORTB7 PORTB6 SCLK0 Serial clock input/output 0 PORTB5 RXD0 UART data input 0 TXD0 UART data output 0 Serial data input 0 PORTB4 TXD0...
  • Page 22 1.4 Pin Names and Functions TMP89FM42...

  • Page 23: Cpu Core

    TMP89FM42 2. CPU Core 2.1 Configuration The CPU core consists of a CPU, a system clock controller and a reset circuit. This chapter describes the CPU core address space, the system clock controller and the reset circuit. 2.2 Memory space The 870/C1 CPU memory space consists of a code area to be accessed as instruction operation codes and operands and a data area to be accessed as sources and destinations of transfer and calculation instructions.

  • Page 24: Ram

    2. CPU Core 2.2 Memory space TMP89FM42 2.2.1.1 The RAM is mapped in the data area immediately after reset release. By setting SYSCR3 to "1" and writing 0xD4 to SYSCR4, RAM can be mapped to 0x0040to 0x083F in the code area to execute the program. At this time, by setting SYSCR...

  • Page 25: Bootrom

    TMP89FM42 System control status register 4 SYSSR4 (0x0FDF) Bit Symbol RVCTRS RAREAS (RSTDIS) Read/Write After reset Status of mapping of the RAM in the The enabled SYSCR3 data is "0". RAREAS code area The enabled SYSCR3 data is "1". Status of mapping of the vector The enabled SYSCR3...

  • Page 26: Data Area

    2. CPU Core 2.2 Memory space TMP89FM42 Flash memory control register 2 FLSCR2 (0x0FD1) Bit Symbol CR1EN Read/Write After reset FLSCR1 register 0xD5 Enable a change in the FLSCR1 setting CR1EN enable/disable control Others Reserved 2.2.1.3 Flash The Flash is mapped to 0x8000 to 0xFFFF in the code area after reset release. 2.2.2 Data area The data area stores the data to be accessed as sources and destinations of transfer and calculation instruc- tions.

  • Page 27: Sfr

    TMP89FM42 2.2.2.1 The SFR is mapped to 0x0000 to 0x003F (SFR1), 0x0F00 to 0x0FFF (SFR2) and 0x0E40 to 0x0EFF (SFR3) in the data area after reset release. Note: Don't access the reserved SFR. 2.2.2.2 The RAM is mapped to 0x0040 to 0x083F in the data area after reset release. Note: The contents of the RAM become unstable when the power is turned on and immediately after a reset is released.
  • Page 28 2. CPU Core 2.2 Memory space TMP89FM42 FLSCR1 register 0xD5 Enable a change in the FLSCR1 setting CR1EN enable/disable control Others Reserved 2.2.2.4 Flash The Flash is mapped to 0x8000 to 0xFFFF in the data area after reset release.

  • Page 29: System Clock Controller

    TMP89FM42 2.3 System clock controller 2.3.1 Configuration The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. WUCCR WUCDR Warm-up counter INTWUC interrupt XEN/XTEN STOP TBTCR SYSCR1 SYSCR2 Clock generator...
  • Page 30 2. CPU Core 2.3 System clock controller TMP89FM42 Note 3: If the STOP mode is activated with SYSCR1 set at "0", the port internal input is fixed to "0". Therefore, an exter- nal interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated. Note 4: The P11 pin is also used as the STOP pin.

  • Page 31: Functions

    TMP89FM42 Warm-up counter data register WUCDR (0x0FCE) Bit Symbol WUCDR Read/Write After reset WUCDR Warm-up time setting Note 1: Don't start the warm-up counter operation with WUCDR set at "0x00". Clock gear control register CGCR (0x0FCF) Bit Symbol FCGCKSEL Read/Write After reset 00 : fcgck = fc / 4...
  • Page 32 2. CPU Core 2.3 System clock controller TMP89FM42 The hardware control is executed by reset release and the operation mode control circuit when the oper- ation is switched to the STOP mode as described in "2.3.5 Operation mode control circuit". Note: No hardware function is available for external direct monitoring of the basic clock.
  • Page 33 TMP89FM42 Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the high- frequency clock (fc). Table 2-2 Gear Clock (fcgck) CGCR fcgck fc / 4 fc / 2 Reserved Note: Don't change CGCR in the SLOW mode. This may stop the gear clock (fcgck) from being changed.

  • Page 34: Warm-Up Counter

    The minimum instruction execution unit is called a "machine cycle". One machine cycle corresponds to one main system clock. There are a total of 11 different types of instructions for the TLCS-870/C1 Series: 10 types ranging from 1-cycle instructions, which require one machine cycle for execution, to 10- cycle instructions, which require 10 machine cycles for execution, and 13-cycle instructions, which require 13 machine cycles for execution.

  • Page 35: Warm-Up Counter Operation When The Oscillation Is Enabled By The Hardware

    TMP89FM42 2.3.4.1 Warm-up counter operation when the oscillation is enabled by the hardware When a power-on reset is released or a reset is released The warm-up counter serves to secure the time after a power-on reset is released before the supply voltage becomes stable and the time after a reset is released before the oscillation by the high-fre- quency clock oscillation circuit becomes stable.

  • Page 36: Warm-Up Counter Operation When The Oscillation Is Enabled By The Software

    2. CPU Core 2.3 System clock controller TMP89FM42 Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for the oscillation start property of the oscillator.
  • Page 37 TMP89FM42 The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time is 1/fcgck [s]. The gear clock (fcgck) is generated from the high-frequency clock (fc). In the single-clock mode, the low-frequency clock generation circuit pins P03 (XTIN) and P04 (XTOUT) can be used as the I/O ports.
  • Page 38 I/O ports in the dual-clock mode.) The operation of the TLCS-870/C1 Series becomes the single-clock mode after reset release. To operate it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program.

  • Page 39: Stop Mode

    TMP89FM42 SLEEP1 mode In this mode, the high-frequency clock oscillation circuit stops operation, the CPU and the watch- dog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-fre- quency clock (fs). In the SLEEP1 mode, some peripheral circuits become the same as the states when a reset is released.

  • Page 40: Transition Of Operation Modes

    2. CPU Core 2.3 System clock controller TMP89FM42 2.3.5.4 Transition of operation modes RESET Reset release Warm-up that IDLE0 follows reset mode release Warm-up completed (Note 2) SYSCR2 = "1" SYSCR2 = "1" SYSCR1 = "1" IDLE0 NORMAL1 mode mode...

  • Page 41: Operation Mode Control

    TMP89FM42 Table 2-3 Operation Modes and Conditions Oscillation circuit Watchdog Time base Other periph- Operation mode CPU core Machine cycle time High-fre- Low-fre- timer timer eral circuits quency quency RESET Reset Reset Reset Reset NORMAL1 Operate Operate Oscillation Operate 1 / fcgck [s] Single clock IDLE1 Stop...
  • Page 42 2. CPU Core 2.3 System clock controller TMP89FM42 2. Release by key-on wakeup 3. Release by the voltage detection circuits Note: During the STOP period (from the start of the STOP mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1"...
  • Page 43 TMP89FM42 Even if the pin input returns to low after the warm-up starts, the STOP mode is not restarted. STOP Figure 2-8 Level-sensitive Release Mode (Example when the high-frequency clock oscillation circuit is selected) - Edge-sensitive release mode In this mode, the STOP mode is released at the rising edge of the pin input.
  • Page 44 2. CPU Core 2.3 System clock controller TMP89FM42 2. Release by the key-on wakeup The STOP mode is released by inputting the prescribed level to the key-on wakeup pin. The level to release the STOP mode can be selected from "H" and "L". For release by the key-on wakeup, refer to section "Key-on Wakeup".

  • Page 45: Idle1/2 And Sleep1 Modes

    TMP89FM42 Table 2-4 Oscillation Start Operation at Release of the STOP Mode Operation mode before the STOP High-frequency Low-frequency Oscillation start operation after release mode is started clock clock The high-frequency clock oscillation circuit starts High-frequency Single-clock oscillation. NORMAL1 clock oscillation mode The low-frequency clock oscillation circuit stops circuit...
  • Page 46 2. CPU Core 2.3 System clock controller TMP89FM42 Starting IDLE1/2 mode or SLEEP1 mode by an instruction CPU and WDT stop Reset Reset input Interrupt request IMF = "1" (Interrupt release mode) (Normal release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 mode or SLEEP1 mode start instruction...

  • Page 47: Idle0 And Sleep0 Modes

    TMP89FM42 Start the IDLE1/2 and SLEEP1 modes After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag (EF) to "1", which releases IDLE1/2 and SLEEP1 modes. To start the IDLE1/2 or SLEEP1 mode, set SYSCR2 to "1". If the release condition is satisfied when it is attempted to start the IDLE1/2 or SLEEP1 mode, SYSCR2...
  • Page 48 2. CPU Core 2.3 System clock controller TMP89FM42 Stopping peripherals by instructions Starting IDLE0 or SLEEP0 mode by an instruction CPU and WDT stop Reset input Reset TBT source clock falling edge "0" TBTCR "1" TBT interrupt enabled (Normal release mode) IMF = "1"...
  • Page 49 TMP89FM42 Normal release mode (IMF, EF5, TBTCR = "0") The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at TBTCR is detected. After the IDLE0 or SLEEP0 mode is released, the operation is restarted by the instruction that follows the IDLE0 or SLEEP0 mode start instruction.
  • Page 50 2. CPU Core 2.3 System clock controller TMP89FM42 Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the high-fre- quency clock) (SYSCR2).4 ; SYSCR2 = 1 ; (Switches the main system clock to the basic clock for the low-frequen- cy clock for the SLOW2 mode) ;...
  • Page 51 TMP89FM42 Quarter of the low-frequency clock (fs/4) Gear clock (fcgck) 2.5/fcgck(max.) SYSCR2 Main system clock When the rising edge of fs/4 is When the rising edge of fcgck is detected detected twice after SYSCR2 twice after fm is stopped, fm is switched to fcgck. is changed from 1 to 0, f is stopped for synchronization.

  • Page 52: Reset Control Circuit

    2. CPU Core 2.4 Reset Control Circuit TMP89FM42 2.4 Reset Control Circuit The reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 Configuration The reset control circuit consists of the following reset signal generation circuits: 1.
  • Page 53 TMP89FM42 Note 3: After SYSCR3 is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3) in NORMAL1 mode when fcgck is fc/4 (CGCR=00). Otherwise, SYSCR3 may be enabled at unex- pected timing. Note 4: Bits 7 to 3 of SYSCR3 are read as "0". System control register 4 SYSCR4 (0x0FDF)

  • Page 54: Functions

    2. CPU Core 2.4 Reset Control Circuit TMP89FM42 0 :- FCLR Flag initialization control 1 : Clears the internal factor reset flag to "0". 0 :- FLSRF Flash standby reset detection flag 1 : Detects the flash standby reset. 0 :- TRMDS Trimming data status 1 : Detect state of abnormal trimming data...

  • Page 55: Reset Signal Generating Factors

    TMP89FM42 Table 2-5 Initialization of Built-in Hardware by Reset Operation and Its Status after Release During the warm-up opera- Immediately after the Built-in hardware During reset tion that follows reset warm-up operation that fol- release lows reset release MCU mode: MCU mode: MCU mode: 0xFFFE...
  • Page 56 2. CPU Core 2.4 Reset Control Circuit TMP89FM42 Note: When the supply voltage is equal to or lower than the detection voltage of the power-on reset circuit, the power-on reset remains active, even if the pin is turned to "H". RESET Operating voltage Reset time...

  • Page 57: Power-On Reset

    TMP89FM42 2.4.4.2 Power-on reset The power-on reset is an internal factor reset that occurs when the power is turned on. When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the power-on reset circuit, a reset signal is generated and if it is higher than the releasing voltage of the power-on reset circuit, a reset signal is released.

  • Page 58: Internal Factor Reset Detection Status Register 2.5

    2. CPU Core 2.4 Reset Control Circuit TMP89FM42 2.4.4.8 Internal factor reset detection status register By reading the internal factor reset detection status register IRSTSR after the release of an internal fac- tor reset, except the power-on reset, the factor which causes a reset can be detected. The internal factor reset detection status register is initialized by an external reset input or power-on reset.

  • Page 59: Revision History

    TMP89FM42 2.5 Revision History Description "2.3.4.1 Warm-up counter operation when the oscillation is enabled by the hardware" Fixed specification from T.B.D. to 0x66. RA001 "Figure 2-15 External Reset Input (when the power is turned on)" and "Figure 2-16 External Reset Input (when the power is stabilized)" Deleted "Recommended".
  • Page 60 2. CPU Core 2.5 Revision History TMP89FM42...
  • Page 61 TMP89FM42 3. Interrupt Control Circuit The TMP89FM42 has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Three of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vec- tor addresses.
  • Page 62 3. Interrupt Control Circuit TMP89FM42 Note 4: Do not set SYSCR3 to "0" in the serial PROM mode. If an interrupt is generated with SYSCR3 ="0", the software refers to the vector area in the BOOTROM and the user cannot use it.
  • Page 63 TMP89FM42 3.1 Configuration Figure 3-1 Interrupt Control Circuit...
  • Page 64 3. Interrupt Control Circuit 3.2 Interrupt Latches (IL25 to IL3) TMP89FM42 3.2 Interrupt Latches (IL25 to IL3) An interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruc- tion execution interrupt. When an interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its acceptance is enabled.
  • Page 65 TMP89FM42 3.3 Interrupt Enable Register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). Non-maskable interrupts are accepted regardless of the contents of the EIR. The EIR consists of the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF).
  • Page 66 3. Interrupt Control Circuit 3.3 Interrupt Enable Register (EIR) TMP89FM42 Interrupt latch (ILL) (0x0FE0) Bit Symbol Read/Write After reset INTTXD0 INTRXD0 / INTTBT INTWUC INTWDT Function INTSIO0 Interrupt latch (ILH) (0x0FE1) Bit Symbol IL15 IL14 IL13 IL12 IL11 IL10 Read/Write After reset INTSBI0/ INTTCA0...
  • Page 67 TMP89FM42 Interrupt enable register (EIRL) EIRL (0x003A) Bit Symbol Read/Write After reset INTTXD0 INTRXD0 / INTTBT INTWUC Interrupt Function INTSIO0 master en- able flag Interrupt enable register (EIRH) EIRH (0x003B) Bit Symbol EF15 EF14 EF13 EF12 EF11 EF10 Read/Write After reset INTSBI0/ INTTCA0 INTTC01...
  • Page 68 3. Interrupt Control Circuit 3.4 Maskable Interrupt Priority Change Function TMP89FM42 3.4 Maskable Interrupt Priority Change Function The priority of maskable interrupts (IL4 to IL25) can be changed to four levels, Levels 0 to 3, regardless of the basic priorities 5 to 26. Interrupt priorities can be changed by the interrupt priority change control register (ILPRS1 to ILPRS6).
  • Page 69 TMP89FM42 Interrupt priority change control register 4 ILPRS4 (0x0FF3) Bit Symbol IL19P IL18P IL17P IL16P Read/Write After reset IL19P Sets the interrupt priority of IL19. Level 0 (lower priority) IL18P Sets the interrupt priority of IL18. Level 1 IL17P Sets the interrupt priority of IL17. Level 2 IL16P Sets the interrupt priority of IL16.
  • Page 70 3. Interrupt Control Circuit 3.5 Interrupt Sequence TMP89FM42 3.5 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion of “0”...
  • Page 71 TMP89FM42 A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt is requested in the interrupt service routine. In order to utilize nested interrupt service, the IMF must be set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
  • Page 72 3. Interrupt Control Circuit 3.5 Interrupt Sequence TMP89FM42 3.5.3.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: (GSAVA), A ; Save A register Interrupt processing A, (GSAVA) ;...
  • Page 73 TMP89FM42 Main task Interrupt Interrupt acceptance service task Switching occurs to The register bank LD (RBS),1 the register bank BANK1. BANK0 is in use. Interrupt return A return is made automatically to the register bank BANK0. Figure 3-5 Saving/Restoring General-purpose Registers under Interrupt Processing 3.5.4 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows.
  • Page 74 3. Interrupt Control Circuit 3.6 Software Interrupt (INTSW) TMP89FM42 3.6 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is the top-priority interrupt). Use the SWI instruction only for address error detection or for debugging described below. 3.6.1 Address error detection 0xFF is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address.
  • Page 75 TMP89FM42 3.8 Revision History Description Revised from WDTCR1 to WDCTR RA003 Added chapter "3.5 Interrupt Sequence" "Figure 3-3 Saving/restoring general-purpose registers" Revised SP position...
  • Page 76 3. Interrupt Control Circuit 3.8 Revision History TMP89FM42...
  • Page 77 TMP89FM42 4. External Interrupt control circuit External interrupts detects the change of the input signal and generates an interrupt request. Noise can be removed by the built-in digital noise canceller. 4.1 Configuration The external interrupt control circuit consists of a noise canceller, an edge detection circuit, a level detection cir- cuit and an interrupt signal generation circuit.
  • Page 78 4. External Interrupt control circuit 4.2 Control TMP89FM42 4.2 Control External interrupts are controlled by the following registers: Low power consumption register 3 POFFCR3 (0x0F77) Bit Symbol INT5EN INT4EN INT3EN INT2EN INT1EN INT0EN Read/Write After reset Disable INT5EN INT5 control Enable Disable INT4EN...
  • Page 79 TMP89FM42 clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. Note 3: Interrupt requests may be generated when EINTCR1 is changed. Before doing such operation, clear the corresponding interrupt enable register to "0"...
  • Page 80 4. External Interrupt control circuit 4.2 Control TMP89FM42 Noise canceller pass signal level Initial state or signal level "L" INI3LVL when the interrupt request signal is Signal level "H" generated for external interrupt 3 00 : An interrupt request is generated at the rising edge of the noise canceller pass signal Selects the interrupt request gener- 01 :...
  • Page 81 TMP89FM42 Note 4: The contents of EINTCRx are updated each time an interrupt request signal is generated. Note 5: Bits 7 to 5 of EINTCR4 are read as "0". 4.3 Function The condition for generating interrupt request signals and the noise cancel time can be set for external interrupts 1 to 4.
  • Page 82 4. External Interrupt control circuit 4.3 Function TMP89FM42 4.3.2 External interrupt 0 External interrupt 0 detects the falling edge of the pin and generates interrupt request signals. INT0 In NORMAL1/2 or IDLE1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals.
  • Page 83 TMP89FM42 Note: The contents of EINTCRx are updated each time an interrupt request signal is generated. Figure 4-4 Interrupt Request Generation and EINTCRx 4.3.3.3 Noise cancel time selection function In NORMAL1/2 or IDLE1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at EINTCRx.
  • Page 84 4. External Interrupt control circuit 4.3 Function TMP89FM42 Table 4-4 Selection of Interrupt Request Generation Edge EINTCR4 Detected at Rising edge Falling edge Both edges "H" level interrupt 4.3.4.2 A noise canceller pass signal monitoring function when interrupt request signals are generated The level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using EINTCR4.
  • Page 85 TMP89FM42 Table 4-5 Noise Canceller Sampling Lock EINTCR4 Sampling interval fcgck fcgck/2 fcgck/2 fcgck/2 Noise Signal INT4 pin Signal after noise removal Figure 4-7 Noise Cancel Operation In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided by 4. If the same level is detected twice consecutively, the signal is recognized as a signal.
  • Page 86 4. External Interrupt control circuit 4.3 Function TMP89FM42...
  • Page 87 TMP89FM42 5. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request sig- nals or watchdog timer reset signals.
  • Page 88 5. Watchdog Timer (WDT) 5.2 Control TMP89FM42 Enables/disables the watchdog Disable WDTEN timer operation. Enable 00 : The 8-bit up counter is cleared by writing the clear code at any point within the overflow time of the 8-bit up counter. 01 : A watchdog timer interrupt request is generated by writing the clear code at a point within the first quarter of the overflow time of the 8-bit up...
  • Page 89 TMP89FM42 Watchdog timer status WDST (0x0FD7) Bit Symbol WINTST2 WINTST1 WDTST Read/Write After reset No watchdog timer interrupt request signal has occurred. Watchdog timer interrupt request WINTST2 A watchdog timer interrupt request signal has occurred due to the over- signal factor status 2 flow of the 8-bit up counter.
  • Page 90 5. Watchdog Timer (WDT) 5.3 Functions TMP89FM42 Note:The 8-bit up counter source clock operates out of synchronization with WDCTR. Therefore, the first overflow time of the 8-bit up counter after WDCTR is set to "1" may get shorter by a maximum of 1 source clock.
  • Page 91 TMP89FM42 Note:The 8-bit up counter source clock operates out of synchronization with WDCTR. Therefore, the first overflow time of the 8-bit up counter after WDCTR is set to "1" may get shorter by a maximum of 1 source clock. The 8-bit up counter must be cleared within a period of the overflow time minus 1 source clock cycle.
  • Page 92 5. Watchdog Timer (WDT) 5.3 Functions TMP89FM42 5.3.6 Reading the 8-bit up counter The counter value of the 8-bit up counter can be read by reading WDCNT. The stoppage of the 8-bit up counter can be detected by reading WDCNT at random times and comparing the value to the last read value.
  • Page 93 TMP89FM42 6. Power-on Reset Circuit The power-on reset circuit generates a reset when the power is turned on. When the supply voltage is lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated. 6.1 Configuration The power-on reset circuit consists of a reference voltage generation circuit and a comparator.
  • Page 94 6. Power-on Reset Circuit 6.2 Function TMP89FM42 Supply voltage (VDD) Operating voltage VPROFF VPRON Power-on PRON PROFF reset signal Warm-up counter start Warm-up counter clock PWUP CPU/peripheral circuits reset signal Note 1: The power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer to the electrical characteristics and take them into consideration when designing equipment.
  • Page 95 TMP89FM42 7. Voltage Detection Circuit The voltage detection circuit detects any decrease in the supply voltage and generates voltage detection interrupt request signals and voltage detection reset signals. Note: The voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer to the electrical characteristics and take them into consideration when designing equipment.
  • Page 96 7. Voltage Detection Circuit 7.3 Function TMP89FM42 Voltage detection 2 flag (Retains 0 : VDD ≥ VD2LVL VD2F the state when VDD
  • Page 97 TMP89FM42 7.3.1 Enabling/disabling the voltage detection operation Setting VDCR2 to "1" enables the voltage detection operation. Setting it to "0" disables the oper- ation. VDCR2 is cleared to "0" immediately after a power-on reset or a reset by an external reset input is released.
  • Page 98 7. Voltage Detection Circuit 7.3 Function TMP89FM42 If VDCR2 is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL), VDCR1 is set to "1". When the supply voltage (VDD) becomes equal to or higher than the detection voltage (VDxLVL), VDCR1...
  • Page 99 TMP89FM42 VDD level Detection voltage level VDCR1 Voltage detection interrupt request signal NORMAL mode STOP mode Warm-up NORMAL mode STOP mode Warm-up NORMAL mode STOP mode is STOP mode is STOP mode is released at the falling STOP mode is released at the falling activated by activated by edge of VDCR1...
  • Page 100 7. Voltage Detection Circuit 7.4 Register Settings TMP89FM42 Note 2: The voltage detection reset signals are generated continuously as long as the supply voltage (VDD) is lower than the detection voltage (VDxLVL).
  • Page 101 TMP89FM42 7.5 Revision History Description RA001 " Voltage detection control register 1" Revised VD1LVL and VD2LVL. RA002 Revised from VDCR2 to VDCR1...
  • Page 102 7. Voltage Detection Circuit 7.5 Revision History TMP89FM42...
  • Page 103 TMP89FM42 8. I/O Ports Table 8-1 List of I/O Ports Port name Pin name Number of pins Input/output Secondary functions P03 to P00 Also used as the high-frequency oscillator connection pin and the Port P0 Input/output (Note) (Note) low-frequency oscillator connection pin Also used as the external reset input, the external interrupt input and Port P1 P13 to P10...
  • Page 104 8. I/O Ports 8.1 I/O Port Control Registers TMP89FM42 8.1 I/O Port Control Registers The following control registers are used for I/O ports. (The port number is indicated in place of x.) Registers that can be set vary depending on the port. For details, refer to the description of each port. •...
  • Page 105 TMP89FM42 8.2 List of I/O Port Settings For the setting methods for individual I/O ports, refer to the following table. Table 8-2 List of I/O Port Settings Register set value Port name Pin name Function PxCR PxOUTCR PxFC Other required settings Port P0 Port input P03 to P00...
  • Page 106 8. I/O Ports 8.2 List of I/O Port Settings TMP89FM42 Table 8-2 List of I/O Port Settings Register set value Port name Pin name Function PxCR PxOUTCR PxFC Other required settings SERSEL="0*" TXD0 output SERSEL="0" UATCNG="0" SERSEL="0*" RXD0 input SERSEL="0" UATCNG="1"...
  • Page 107 TMP89FM42 Table 8-2 List of I/O Port Settings Register set value Port name Pin name Function PxCR PxOUTCR PxFC Other required settings Port P8 Port input P81 to P80 Port output TC03 input Without register output PPG03 PWM03 TC02 input output PPG02 PWM02...
  • Page 108 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 8.3 I/O Port Registers 8.3.1 Port P0 (P03 to P00) Port P0 is a 4-bit input/output port that can be set to input or output for each bit individually, and it is also used as the high-frequency oscillation connection pin and the low-frequency oscillation connection pin.
  • Page 109 TMP89FM42 Pull-up control (for each bit) Programmable P0PU2 write pull-up resistor Input/output control (for each bit) P0CR2 write Function control (for each bit) P0FC2 write (XTIN) Output latch (for each bit) P0DR2 write P0PRD2 read Pull-up control (for each bit) Programmable P0PU3 write pull-up resistor...
  • Page 110 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Port P0 output latch P0DR (0x0000) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. Port P0 input/output control P0CR (0x0F1A) Bit Symbol...
  • Page 111 TMP89FM42 Table 8-4 P0PRD Read Value (P00 to P01) Set condition P0PRDi read value P0FC0 P0CRi "0" "0" Contents of port Note 1: * : Don’t care Note 2: i = 0, 1 Table 8-5 P0PRD Read Value (P02 to P03) Set condition P0PRDj read value P0FC2...
  • Page 112 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 8.3.2 Port P1 (P13 to P10) Port P1 is a 4-bit input/output port that can be set to input or output for each bit individually, and is also used as the external interrupt input, the STOP mode release signal input and the external reset input. Port P1 contains a programmable pull-up resistor on the VDD side.
  • Page 113 TMP89FM42 Reset Pull-up control pull-up resistor (for each bit) Programmable P1PU write pull-up resistor Input/output control (for each bit) P1CR write Output latch (for each bit) P1DR write P1PRD read Note1 : R = 100Ω (typ.) Note2 : R = 220kΩ (typ.) SYSCR3...
  • Page 114 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Port P1 output latch P1DR (0x0001) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. Port P1 input/output control P1CR (0x0F1B) Bit Symbol...
  • Page 115 TMP89FM42 8.3.3 Port P2 (P27 to P20) Port P2 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the serial bus interface input/output, the serial interface input/output, the UART input/output and the on-chip debug function.
  • Page 116 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Pull-up control (for each bit) Programmable pull-up resistor P2PU write Output control (for each bit) P2OUTCR write Input/output control (for each bit) P2CR write Function control (for each bit) P2FC write Output latch (for each bit) Peripheral Functions enclosed by the...
  • Page 117 TMP89FM42 Port P2 output latch P2DR (0x0002) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. (Serves as Hi-Z or pull-up depending on settings of P2OUTCR and P2PU.) Port P2 input/output control P2CR...
  • Page 118 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Port P2 built-in pull-up resistor control P2PU (0x0F29) Bit Symbol P2PU7 P2PU6 P2PU5 P2PU2 P2PU1 P2PU0 Read/Write After reset The built-in pull-up resistor is not con- The built-in pull-up resistor is not con- nected.
  • Page 119 TMP89FM42 8.3.4 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the analog input and the key-on wakeup input. Port P4 contains a programmable pull-up resistor on the VDD side.
  • Page 120 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Port P4 output latch P4DR (0x0004) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. Port P4 input/output control P4CR (0x0F1E) Bit Symbol...
  • Page 121 TMP89FM42 Table 8-11 P4PRD Read Value Set condition P4PRDi read value P4CRi P4FCi Contents of port "0" "0" Note 1: * : Don’t care Note 2: i = 0 to 7...
  • Page 122 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 8.3.5 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the external interrupt input, the divider output and the timer counter input/output. Table 8-12 Port P7 INT4 INT3...
  • Page 123 TMP89FM42 Port P7 output latch P7DR (0x0007) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected Function Outputs H level when the output mode is selected Port P7 input/output control P7CR (0x0F21) Bit Symbol P7CR7 P7CR6 P7CR5 P7CR4...
  • Page 124 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 8.3.6 Port P8 (P81 to P80) Port P8 is a 2-bit input/output port that can be set to input or output for each bit individually, and it is also used as the timer counter input/output. Table 8-14 Port P8 PPG03 PPG02...
  • Page 125 TMP89FM42 Port P8 output latch P8DR (0x0008) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. Port P8 input/output control P8CR (0x0F22) Bit Symbol P8CR1 P8CR0 Read/Write After reset...
  • Page 126 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Note 2: i = 0 to 1...
  • Page 127 TMP89FM42 8.3.7 Port P9 (P91 to P90) Port P9 is a 2-bit input/output port that can be set to input or output for each bit individually, and it is also used as the UART. The output circuit has the P-channel output control function and either the sink open drain output or the C- MOS output can be selected.
  • Page 128 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Port P9 output latch P9DR (0x0009) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Outputs H level when the Function output mode is selected. (Serves as Hi-Z or pull-up depending on settings of P9OUTCR and P9PU.) Port P9 input/output control...
  • Page 129 TMP89FM42 Port P9 input data P9PRD (0x0016) Bit Symbol P9PRD1 P9PRD0 Read/Write After reset If the port is used in the input mode or as the sink Function open drain output, the contents of the port are read. If not, "0" is read. Table 8-17 P9PRD Read Value Set condition P9PRDi read value...
  • Page 130 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 8.3.8 Port PB (PB7 to PB4) Port PB is an 4-bit input/output port that can be set to input or output for each bit individually, and it is also used as the serial interface input/output and the UART input/output. The output circuit has the P-channel output control function and either the sink open drain output or the C- MOS output can be selected.
  • Page 131 TMP89FM42 Port PB output latch PBDR (0x000B) Bit Symbol Read/Write After reset Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. Port PB input/output control PBCR (0x0F25) Bit Symbol PBCR7 PBCR6 PBCR5 PBCR4...
  • Page 132 8. I/O Ports 8.3 I/O Port Registers TMP89FM42 Table 8-19 PBPRD Read Value Set condition PBPRDi read value PBCRi PBOUTCRi Contents of port "0" Contents of port Note 1: * : Don’t care Note 2: i = 4 to 7...
  • Page 133 TMP89FM42 8.4 Serial Interface Selecting Function TMP89FM42 On the , the built-in serial interface (SIO, UART and I C) communication pins and interrupt source assignment can be changed. Two out of three functions, SIO0, UART0 and I C0, can be used at the same time by using this selecting function.
  • Page 134 8. I/O Ports 8.4 Serial Interface Selecting Function TMP89FM42 Note 2: It is recommended to clear the interrupt latch for the applicable serial interface immediately after changing SERSEL. Inter- rupt latches are common to INTRXD and INTSIO and to INTSBI and INTSIO. Therefore, if an interrupt occurs before or after SERSEL is switched, it is difficult to tell which function has caused the interrupt.
  • Page 135 TMP89FM42 8.5 Revision History Description "Table 8-1 List of I/O Ports" Added description to P9 Port. "Table 8-2 List of I/O Port Settings" Added description of UART setting to P90 and P91. " Port P2 input/output control" Added RXD0(I) to P20. Added TXD0(O) to P21. "8.3.10 Port P8 (P81 to P80)"...
  • Page 136 8. I/O Ports 8.5 Revision History TMP89FM42...
  • Page 137 TMP89FM42 9. Special Function Registers The TMP89FM42 adopts the memory mapped I/O system, and all peripheral hardware data control and transfer operations are performed through the special function registers (SFR). SFR1 is mapped on addresses 0x0000 to 0x003F, SFR2 is mapped on addresses 0x0F00 to 0x0FFF, and SFR3 is mapped on addresses 0x0E40 to 0x0EBF. 9.1 SFR1 (0x0000 to 0x003F) Table 9-1 SFR1 (0x0000 to 0x003F) Address...
  • Page 138 9. Special Function Registers 9.2 SFR2 (0x0F00 to 0x0FFF) TMP89FM42 9.2 SFR2 (0x0F00 to 0x0FFF) Table 9-2 SFR2 (0x0F00 to 0x0F7F) Address Register Name Address Register Name Address Register Name Address Register Name 0x0F00 Reserved 0x0F20 Reserved 0x0F40 Reserved 0x0F60 Reserved 0x0F01 Reserved...
  • Page 139 TMP89FM42 Table 9-3 SFR2 (0x0F80 to 0x0FFF) Address Register Name Address Register Name Address Register Name Address Register Name 0x0F80 Reserved 0x0FA0 Reserved 0x0FC0 Reserved 0x0FE0 0x0F81 Reserved 0x0FA1 Reserved 0x0FC1 Reserved 0x0FE1 0x0F82 Reserved 0x0FA2 Reserved 0x0FC2 Reserved 0x0FE2 0x0F83 Reserved 0x0FA3...
  • Page 140 9. Special Function Registers 9.3 SFR3 (0x0E40 to 0x0EFF) TMP89FM42 9.3 SFR3 (0x0E40 to 0x0EFF) Table 9-4 SFR3 (0x0E40 to 0x0EBF) Address Register Name Address Register Name Address Register Name Address Register Name 0x0E40 Reserved 0x0E60 Reserved 0x0E80 Reserved 0x0EA0 Reserved 0x0E41 Reserved...
  • Page 141 TMP89FM42 Table 9-5 SFR3 (0x0EC0 to 0x0EFF) Address Register Name Address Register Name Address Register Name Address Register Name 0x0EC0 Reserved 0x0ED0 Reserved 0x0EE0 Reserved 0x0EF0 Reserved 0x0EC1 Reserved 0x0ED1 Reserved 0x0EE1 Reserved 0x0EF1 Reserved 0x0EC2 Reserved 0x0ED2 Reserved 0x0EE2 Reserved 0x0EF2 Reserved...
  • Page 142 9. Special Function Registers 9.3 SFR3 (0x0E40 to 0x0EFF) TMP89FM42...
  • Page 143 TMP89FM42 10. Low Power Consumption Function for Peripherals The TMP89FM42 has low power consumption registers (POFFCRn) that save power when specific peripheral functions are unused. Each bit of the low power consumption registers can be set to enable or disable each peripheral function.
  • Page 144 10. Low Power Consumption Function for Peripherals TMP89FM42 10.1 Control The low power consumption function is controlled by the low power consumption registers (POFFCRn). (n = 0, 1, 2, 3) Low power consumption register 0 POFFCR0 (0x0F74) Bit Symbol TC023EN TC001EN TCA1EN TCA0EN...
  • Page 145 TMP89FM42 Disable INT5EN INT5 control Enable Disable INT4EN INT4 control Enable Disable INT3EN INT3 control Enable Disable INT2EN INT2 control Enable Disable INT1EN INT1 control Enable Disable INT0EN INT0 control Enable...
  • Page 146 10. Low Power Consumption Function for Peripherals TMP89FM42...
  • Page 147 TMP89FM42 11. Divider Output ( This function outputs approximately 50% duty pulses that can be used to drive the piezoelectric buzzer or other device. 11.1 Configuration fcgck/2 or fs/2 Selector fcgck/2 or fs/2 fcgck/2 or fs/2 fcgck/2 DVO pin DVOCK DVOEN DVOCR Figure 11-1 Divider Output...
  • Page 148 11. Divider Output (DVO) 11.2 Control TMP89FM42 The divider output is enabled by setting DVOCR to "1". Then, The rectangular waves selected by DVOCR is output from pin. It is disabled by clearing DVOVR to "0". And pin keeps "H" level. When the operation is changed to STOP or IDLE0/SLEEP0 mode, DVOCR...
  • Page 149 TMP89FM42 11.3 Revision History Description RA001 Deleted SLEEP2 description.
  • Page 150 11. Divider Output (DVO) 11.3 Revision History TMP89FM42...
  • Page 151 TMP89FM42 12. Time Base Timer (TBT) The time base timer generates the time base for key scanning, dynamic display and other processes. It also pro- vides a time base timer interrupt (INTTBT) in a certain cycle. 12.1 Time Base Timer 12.1.1 Configuration fcgck/2 or fs/2...
  • Page 152 12. Time Base Timer (TBT) 12.1 Time Base Timer TMP89FM42 Note 3: TBTCR should be set when TBTCR is "0". Note 4: When SYSCR1 is "1" in the NORMAL 1/2 or IDLE1/2 mode, the interrupt request is subject to some fluctuations to synchronize fs and fcgck.
  • Page 153 TMP89FM42 ; IMF ← 0 (EIRL). 5 ; Set the interrupt enable register ; IMF ← 1 (TBTCR), 0y00000010 ; Set the interrupt frequency (TBTCR), 0y00001010 ; Enable generation of interrupt request signals...
  • Page 154 12. Time Base Timer (TBT) 12.2 Revision History TMP89FM42 12.2 Revision History Description RA001 Deleted SLEEP2 description...
  • Page 155 TMP89FM42 13. 16-bit Timer Counter (TCA) The TMP89FM42 contains 2 channels of high-performance 16-bit timer counters (TCA). This chapter describes the 16-bit timer counter A0. For the 16-bit timer counter A1, replace the SFR addresses and pin names, as shown in Table 13-1 and Table 13-2. Table 13-1 SFR Address Assignment Low power TAxDRAL...
  • Page 156 13. 16-bit Timer Counter (TCA) 13.1 Configuration TMP89FM42 13.1 Configuration Figure 13-1 Timer Counter A0...
  • Page 157 TMP89FM42 13.2 Control Timer Counter A0 is controlled by the low power consumption register (POFFCR0), the timer counter A0 mode register (TA0MOD), the timer counter A0 control register (TA0CR) and two 16-bit timer A0 registers (TA0DRA and TA0DRB). Low power consumption register 0 POFFCR0 (0x0F74) Bit Symbol...
  • Page 158 13. 16-bit Timer Counter (TCA) 13.2 Control TMP89FM42 Timer counter A0 mode register TA0MOD TA0MCAP (0x0031) Bit Symbol TA0DBE TA0TED TA0CK TA0M TA0METT Read/Write After reset Disable the double buffer TA0DBE Double buffer control Enable the double buffer Rising edge/H level TA0TED External trigger input selection Falling edge/L level...
  • Page 159 TMP89FM42 Timer counter A0 control register TA0CR TA0CAP (0x0032) Bit Symbol TA0OVE TA0TFF TA0NC TA0S TA0MPPG Read/Write After reset Generate no INTTA0 interrupt request when the counter overflow occurs. TA0OVE Overflow interrupt control Generate an INTTA0 interrupt request when the counter overflow occurs.
  • Page 160 13. 16-bit Timer Counter (TCA) 13.2 Control TMP89FM42 Timer counter A0 status register TA0SR (0x0033) Bit Symbol TA0OVF TA0CPFA TA0CPFB Read/Write After reset No overflow has occurred. TA0OVF Overflow flag At least an overflow has occurred. No capture operation has been executed. TA0CPFA Capture completion flag A At least a pulse width capture has been executed in the double-edge...
  • Page 161 TMP89FM42 13.3 Low Power Consumption Function Timer counter A0 has the low power consumption register (POFFCR0) that saves power consumption when the timer is not used. Setting POFFCR0 to "0" disables the basic clock supply to timer counter A0 to save power. Note that this makes the timer unusable.
  • Page 162 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 13.4 Timer Function Timer counter A0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse width measurement and programmable pulse generate (PPG) output modes. 13.4.1 Timer mode In the timer mode, the up-counter counts up using the internal clock, and interrupts can be generated regu- larly at specified times.
  • Page 163 TMP89FM42 13.4.1.4 Register buffer configuration Temporary buffer The TMP89FM42 contains an 8-bit temporary buffer. When a write instruction is executed on TA0DRAL, the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. Subsequently, when a write instruction is executed on TA0DRAH, the set value is stored into the double buffer or TA0DRAH.
  • Page 164 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 Timer start Timer stop TA0CR TA0MOD Source clock Counter mn-1 rs-1 Counter clear Counter clear Write to TA0DRAL Write n Write s Write to TA0DRAH Write m Write r Temporary buffer (8 bits) TA0DRAL Match detection...
  • Page 165 TMP89FM42 Timer start Timer stop TA0CR TA0MOD Source clock Counter 0000 0001 0002 18FD 18FE 18FF 1900 1901 1902 1903 1904 1905 1906 0000 FE FF TA0DRBL TA0DRBH is updated when TA0DRBL is read TA0DRBH Read TA0DRBL Read TA0DRBH Read Read Read Read...
  • Page 166 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 13.4.2 External trigger timer mode In the external trigger timer mode, the up counter starts counting when it is triggered by the input to the TCA0 pin. 13.4.2.1 Setting Setting the operation mode selection TA0MOD to "100" activates the external trigger timer mode.
  • Page 167 TMP89FM42 Timer start Timer stop TA0CR TA0MOD Counting Edge is invalid Counting Edge is invalid start during counting start during counting TA0 pin input Source clock Counter mn-1 rs-1 Counter Counter clear clear Write to TA0DRAL Write n Write s Write to TA0DRAH Write m Write r...
  • Page 168 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 13.4.3 Event counter mode In the event counter mode, the up counter counts up at the edge of the input to the TCA0 pin. 13.4.3.1 Setting Setting the operation mode selection TA0MOD to "010" activates the event counter mode. Set the trigger edge at the external trigger input selection TA0MOD.
  • Page 169 TMP89FM42 Timer start Timer stop TA0CR TA0 pin input Counter mn-1 rs-1 Counter clear Counter clear Write to TA0DRAL Write n Write s Write to TA0DRAH Write m Write r TA0DRAL Match detection Match detection TA0DRAH INTTCA interrupt request Reflected by writing to TA0DRAH Reflected by writing to TA0DRAH When the rising edge is selected (TA0MOD=”0”) Figure 13-5 Event Count Mode Timing Chart...
  • Page 170 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 13.4.4 Window mode In the window mode, the up counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the TCA0 pin (window pulse) and the internal clock. 13.4.4.1 Setting Setting the operation mode selection TA0MOD...
  • Page 171 TMP89FM42 Timer start Timer stop TA0CR TA0MOD Count in the period of H level Count in the period of H level TA0 pin input Source clock Counter mn-1 Counter clear Write to TA0DRAL Write n Write to TA0DRAH Write m TA0DRAL Match detection TA0DRAH...
  • Page 172 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 13.4.5 Pulse width measurement mode In the pulse width measurement mode, the up counter starts counting at the rising/falling edge(s) of the input to the TCA0 pin and measures the input pulse width based on the internal clock. 13.4.5.1 Setting Setting the operation mode selection TA0MOD...
  • Page 173 TMP89FM42 The captured value must be read from TA0DRB (and also from TA0DRA for the double-edge capture) before the next trigger edge is detected. If the captured value is not read, it becomes undefined. TA0DRA and TA0DRB must be read by using a 16-bit access instruction. Setting TA0CR...
  • Page 174 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 13.4.6 Programmable pulse generate (PPG) mode In the PPG output mode, an arbitrary duty pulse is output by two timer registers. 13.4.6.1 Setting Setting the operation mode selection TA0MOD to "011" activates the PPG output mode. Select the source clock at TA0MOD.
  • Page 175 TMP89FM42 13.4.6.3 Register buffer configuration Temporary buffer The TMP89FM42 contains an 8-bit temporary buffer. When a write instruction is executed on TA0DRAL (TA0DRBL), the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. Subsequently, when a write instruction is executed on TA0DRAH (TA0DRBH), the set value is stored into the double buffer or TA0DRAH (TA0DRBH).
  • Page 176 13. 16-bit Timer Counter (TCA) 13.4 Timer Function TMP89FM42 Timer start Timer stop TA0CR TA0MOD Source clock Counter Counter Counter clear clear Write to TA0DRAL, H Write n Write s Write to TA0DRBL, H Write m Write r TA0DRAL, H Match detection Match detection TA0DRBL, H...
  • Page 177 TMP89FM42 13.5 Noise Canceller The digital noise canceller can be used in the operation modes that use the TCA0 pin. 13.5.1 Setting When the digital noise canceller is used, the input level is sampled at the sampling intervals set at TA0CR.
  • Page 178 13. 16-bit Timer Counter (TCA) 13.6 Revision History TMP89FM42 13.6 Revision History Description RA001 "Table 13-3 Timer Mode Resolution and Maximum Time Setting" Revised Resolution and Maximum time of TA0MOD=11.
  • Page 179 TMP89FM42 14. 8-bit Timer Counter (TC0) The TMP89FM42 contains 4 channels of high-performance 8-bit timer counters (TC0). Each timer can be used for time measurement and pulse output with a prescribed width. Two 8-bit timer counters are cascadable to form a 16-bit timer.
  • Page 180 14. 8-bit Timer Counter (TC0) TMP89FM42 14.1 Configuration Figure 14-1 8-bit Timer Counters 00 and 01...
  • Page 181 TMP89FM42 14.2 Control 14.2.1 Timer counter 00 The timer counter 00 is controlled by the timer counter 00 mode register (T00MOD) and two 8-bit timer reg- isters (T00REG and T00PWM). Timer register 00 T00REG (0x0026) Bit Symbol T00REG Read/Write After reset Timer register 00 T00PWM (0x0028)
  • Page 182 14. 8-bit Timer Counter (TC0) TMP89FM42 Timer counter 00 mode register T00MOD (0x002A) Bit Symbol TFF0 DBE0 TCK0 EIN0 TCM0 Read/Write After reset Clear TFF0 Timer F/F0 control Disable the double buffer DBE0 Double buffer control Enable the double buffer NORMAL1/2 or IDLE1/2 mode SLOW1/2 or SLEEP1 SYSCR1...
  • Page 183 TMP89FM42 14.2.2 Timer counter 01 Timer counter 01 is controlled by timer counter 01 mode register (T01MOD) and two 8-bit timer registers (T01REG and T01PWM). Timer register 01 T01REG (0x0027) Bit Symbol T01REG Read/Write After reset Timer register 01 T01PWM (0x0029) Bit Symbol T01PWM...
  • Page 184 14. 8-bit Timer Counter (TC0) TMP89FM42 Timer counter 01 mode register T01MOD (0x002B) Bit Symbol TFF1 DBE1 TCK1 EIN1 TCM1 Read/Write After reset Clear TFF1 Timer F/F1 control Disable the double buffer DBE1 Double buffer control Enable the double buffer NORMAL1/2 or IDLE1/2 mode SLOW1/2 or SLEEP1 SYSCR1...
  • Page 185 TMP89FM42 14.2.3 Common to timer counters 00 and 01 Timer counters 00 and 01 have the low power consumption register (POFFCR0) and timer 00 and 01 control registers in common. Low power consumption register 0 POFFCR0 (0x0F74) Bit Symbol TC023EN TC001EN TCA1EN TCA0EN...
  • Page 186 14. 8-bit Timer Counter (TC0) TMP89FM42 Timer counter 01 control register T001CR (0x002C) Bit Symbol OUTAND TCAS T01RUN T00RUN Read/Write After reset Output the timer 00 output from the pins and the timer PWM0 PPG0 01 output from the pins. PWM1 PPG1 OUTAND...
  • Page 187 TMP89FM42 14.2.4 Operation modes and usable source clocks The operations modes of the 8-bit timers and the usable source clocks are listed below. Table 14-3 Operation Modes and Usable Source Clocks (NORMAL1/2 and IDLE1/2 modes) TCK0 TC0i fcgck/2 fcgck/2 pin input Operation mode fcgck/2 fcgck...
  • Page 188 14. 8-bit Timer Counter (TC0) TMP89FM42 14.3 Low Power Consumption Function Timer counters 00 and 01 have the low power consumption registers (POFFCR0) that save power when the timers are not used. Setting POFFCR0 to "0" disables the basic clock supply to timer counters 00 and 01 to save power. Note that this renders the timers unusable.
  • Page 189 TMP89FM42 14.4 Functions Timer counters TC00 and TC01 have 8-bit modes in which they are used independently and 16-bit modes in which they are cascaded. The 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, the 8-bit pulse width modulation output (PWM) mode and the 8-bit programmable pulse generated output (PPG) mode.
  • Page 190 14. 8-bit Timer Counter (TC0) TMP89FM42 If the value set to T00REG is smaller than the up counter value, the match detection is exe- cuted using a new set value after the up counter overflows. Therefore, the interrupt request interval may be longer than the selected time. If the value set to T00REG is equal to the up counter value, the match detection is executed immediately after data is written into T00REG.
  • Page 191 TMP89FM42 Timer start Timer stop T001CR T00MOD Source clock Counter Counter clear Counter clear Write to T00REG Write m Write n Match detection Match detection T00REG INTT00 interrupt request Reflected by writing to T00REG Reflected by writing to T00REG When the double buffer is disabled (T00MOD=”0”) Timer start T001CR...
  • Page 192 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.2 8-bit event counter mode In the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 or TC01 pin. The operation of TC00 is described below, and the same applies to the operation of TC01. 14.4.2.1 Setting TC00 is put into the 8-bit event counter mode by setting T00MOD...
  • Page 193 TMP89FM42 Timer start Timer stop T001CR TC00 pin input Counter Counter clear Counter clear Write to T00REG Write m Write n Match detection Match detection T00REG INTT00 interrupt request Reflected by writing to T00REG Reflected by writing to T00REG When the double buffer is disabled (T00MOD=”0”) Figure 14-4 Event Counter Mode Timing Chart...
  • Page 194 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.3 8-bit pulse width modulation (PWM) output mode The pulse-width modulated pulses with a resolution of 7 bits are output in the 8-bit PWM mode. An addi- tional pulse can be added to the 2 × n-th duty pulse. This enables PWM output with a resolution nearly equiva- lent to 8 bits.
  • Page 195 TMP89FM42 Additional Additional Additional Timer start pulse pulse pulse (Duty pulse (Duty pulse width) width) T00PWM T00PWM PWM0 pin output (TFF0=“1”) PWM0 pin output (TFF0=“0”) 128 counts 128 counts (cycle width) (cycle width) INTT00 interrupt request Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5...
  • Page 196 14. 8-bit Timer Counter (TC0) TMP89FM42 Subsequently, the up counter continues counting up. When the up counter value reaches 128, an over- flow occurs and the up counter is cleared to "0x00". At the same time, the output of the pin is PWM0 reversed.
  • Page 197 TMP89FM42 14.4.3.3 Double buffer The double buffer can be used for T00PWM by setting T00MOD. The double buffer is dis- abled by setting T00MOD to "0" or enabled by setting T00MOD to "1". • When the double buffer is enabled When a write instruction is executed on T00PWM during the timer operation, the set value is first stored in the double buffer, and T00PWM is not updated immediately.
  • Page 198 14. 8-bit Timer Counter (TC0) TMP89FM42 Table 14-7 Resolutions and Cycles in the 8-bit PWM Mode 7-bit cycle Source clock [Hz] Resolution (period × 2) T00MOD NORMAL1/2 or IDLE1/2 mode SLOW1/2 or fcgck=10MHz fs=32.768KHz fcgck=10MHz fs=32.768KHz SYSCR1 SYSCR1 SLEEP1 mode = "0"...
  • Page 199 TMP89FM42 14.4.4 8-bit programmable pulse generate (PPG) output mode In the 8-bit PPG mode, the pulses with arbitrary duty and cycle are output by using the T00REG and T00PWM registers. By setting the T001CR register, a pulse that is a logical ANDed product of the TC00 and TC01 outputs can be output to the TC01 pin.
  • Page 200 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.4.2 Operation Setting T001CR to "1" allows the up counter to increment based on the selected source clock. When a match between the internal up counter value and the value set to T00PWM is detected, the output of the pin is reversed.
  • Page 201 TMP89FM42 (T00PWM),0x28 ; Sets the timer register (duty pulse) ; 8µs / (2/fcgck) = 0x28 (T001CR).0 ; Starts TC00 Timer start Timer stop T001CR T00MOD Source clock Counter Counter Counter Counter Counter clear clear clear clear Write to T00PWM Write m Write r Write t Double buffer...
  • Page 202 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.5 16-bit timer mode In the 16-bit timer mode, TC00 and TC01 are cascaded to form a 16-bit timer counter, which can measure a longer period than an 8-bit timer. 14.4.5.1 Setting Setting T001CR to "1" connects TC00 and TC01 and activates the 16-bit mode. All the set- tings of TC00 are ignored and those of TC01 are effective in the 16-bit mode.
  • Page 203 TMP89FM42 If the value set to T01+00REG is smaller than the up counter value, the match detection is executed using a new set value after the up counter overflows. Therefore, the interrupt request interval may be longer than the selected time. If the value set to T01+00REG is equal to the up counter value, the match detection is executed immediately after data is written into T01+00REG.
  • Page 204 14. 8-bit Timer Counter (TC0) TMP89FM42 Timer start Timer stop T001CR T01MOD Source clock Counter km-1 sr-1 Counter clear Counter clear Write to T00REG Write m Write r Write to T01REG Write k Write s Match detection Match detection T01+00REG INTT01 interrupt Reflected by writing to T01REG request...
  • Page 205 TMP89FM42 Table 14-9 16-bit Timer Mode Resolution and Maximum Time Setting Source clock [Hz] Resolution Maximum time setting T01MOD NORMAL1/2 or IDLE1/2 mode SLOW1/2 or fcgck=10MHz fs=32.768KHz fcgck=10MHz fs=32.768KHz SYSCR1 SYSCR1 SLEEP1 mode = "0" = "1" 204.8µs 488.2µs 13.4s fcgck/2 fs/2...
  • Page 206 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.6 16-bit event counter mode In the 16-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 pin. TC00 and TC01 are cascaded to form a 16-bit timer counter, which can measure a longer period than an 8-bit timer.
  • Page 207 TMP89FM42 Timer start Timer stop T001CR TC00 pin input Counter km-1 rs-1 Counter Counter Counter clear clear clear Write to T00REG Write m Write s Write to T01REG Write k Write r Match detection Match detection T01+00REG INTT00 interrupt Reflected by writing to T01REG request Reflected by writing to T01REG When the double buffer is disabled (T01MOD=”0”)
  • Page 208 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.7 12-bit pulse width modulation (PWM) output mode In the 12-bit PWM output mode, TC00 and TC01 are cascaded to output the pulse-width modulated pulses with a resolution of 8 bits. An additional pulse of 4 bits can be inserted, which enables PWM output with a res- olution nearly equivalent to 12 bits.
  • Page 209 TMP89FM42 Table 14-10 Cycles in Which Additional Pulses Are Inserted Cycles in which additional pulses are inserted among cycles 1 to 16 PWMAD0="1" PWMAD1="1" 5, 13 PWMAD2="1" 3, 7, 11, 15 PWMAD3="1" 2, 4, 6, 8, 10, 12, 14, 16 Set the initial state of the pin at T01MOD.
  • Page 210 14. 8-bit Timer Counter (TC0) TMP89FM42 Additional Additional Timer start pulse pulse Timer stop PWM1 pin output (TFF1=“1”) PWM1 pin output (TFF1=“0”) INTT00 interrupt request INTT01 interrupt request Cycle When PWMAD1=“1” Additional Additional Additional Additional Additional Timer start Timer stop pulse pulse pulse...
  • Page 211 TMP89FM42 rupt request is generated (an INTT00 interrupt request is generated each time an overflow occurs.) An INTT01 interrupt request is generated at the 16 × n-th overflow (n=1, 2, 3...). Subsequently, the up counter continues counting up. When T001CR is set to "0" during the timer operation, the up counter is stopped and cleared to "0x00".
  • Page 212 14. 8-bit Timer Counter (TC0) TMP89FM42 When write instructions are executed on T00PWM and T01PWM in this order while the timer is stopped, the set value is immediately stored in T01+00PWM. Operate TC00 and TC01 in the 12-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equiva- lent to 14.0625 µs in 51.2µs cycles (fcgck = 10 MHz) (Example) (Actually, output a duty pulse of 225 µs in total in 16 cycles (819.2 µs))
  • Page 213 TMP89FM42 Table 14-12 Resolutions and Cycles in the 12-bit PWM Mode 8-bit cycle Source clock [Hz] Resolution (period × 16) T01MOD NORMAL1/2 or IDLE1/2 mode SLOW1/2 or fcgck=10MHz fs=32.768KHz fcgck=10MHz fs=32.768KHz SYSCR1 SYSCR1 SLEEP1 mode = "0" = "1" 52.4ms 125ms 204.8µs...
  • Page 214 14. 8-bit Timer Counter (TC0) TMP89FM42 14.4.8 16-bit programmable pulse generate (PPG) output mode In the 16-bit PPG mode, TC00 and TC01 are cascaded to output the pulses that have a resolution of 16 bits and arbitrary pulse width and duty. Two 16-bit registers, T01+00REG and T01+00PWM, are used to output the pulses.
  • Page 215 TMP89FM42 When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to be supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/2 [Hz] (in SLOW1/2 or SLEEP1 mode), and a pulse width of two machine cycles or more is required at both the "H" and "L" levels. 14.4.8.3 Double buffer The double buffer can be used for T01+00PWM and T01+00REG by setting T01MOD.
  • Page 216 14. 8-bit Timer Counter (TC0) TMP89FM42 (T001CR),0x06 ; Starts TC00 and TC01 Timer start Timer stop T001CR T01MOD Source clock Counter Counter Counter Counter Counter clear clear clear clear Write to T00REG Write b Write d Write f Write to T01REG Write a Write c Write e...
  • Page 217 TMP89FM42 15. Real Time Clock (RTC) The real time clock is a function that generates interrupt requests at certain intervals using the low-frequency clock. The number of interrupts is counted by the software to realize the clock function. The real time clock can be used only in the operation modes where the low-frequency clock oscillates, except for SLEEP0.
  • Page 218 15. Real Time Clock (RTC) 15.3 Function TMP89FM42 000 : 2 /fs (1.000 [s] @fs=32.768kHz) 001 : 2 /fs (0.500 [s] @fs=32.768kHz) 010 : 2 /fs (0.250 [s] @fs=32.768kHz) 011 : 2 /fs (125.0 [ms] @fs=32.768kHz) RTCSEL Selects the interrupt generation interval 100 : 2 /fs (62.50 [ms] @fs=32.768kHz) 101 : 2...
  • Page 219 TMP89FM42 15.4 Real Time Clock Operation 15.4.1 Enabling the real time clock operation Set the interrupt generation interval to RTCCR, and at the same time, set RTCCR to "1". When RTCCR is set to "1", the binary counter for the real time clock starts counting of the low- frequency clock.
  • Page 220 15. Real Time Clock (RTC) 15.4 Real Time Clock Operation TMP89FM42...
  • Page 221 TMP89FM42 16. Asynchronous Serial Interface (UART) The TMP89FM42 contains 2 channels of asynchronous serial interfaces (UART). This chapter describes asynchronous serial interface 0 (UART0). For UART1, replace the SFR addresses and pin names as shown in Table 16-1 and Table 16-2. Table 16-1 SFR Address Assignment UARTxCR1 UARTxCR2...
  • Page 222 16. Asynchronous Serial Interface (UART) 16.1 Configuration TMP89FM42 16.1 Configuration UART0 control register 1 UART0 transmit data buffer UART0CR1 UART0CR1 UART0 receive data buffer RD0BUF Shift register Parity bit Shift register Stop bit INTTXD0 interrupt request RXD0 Noise rejection circuit TXD0 INTRXD0 IrDA control...
  • Page 223 TMP89FM42 16.2 Control UART0 is controlled by the low power consumption registers (POFFCR1), UART0 control registers 1 and 2 (UART0CR1 and UART0CR2) and the UART0 baud rate register (UART0DR). The operating status can be moni- tored using the UART status register (UART0SR). Low power consumption register 1 POFFCR1 (0x0F75)
  • Page 224 16. Asynchronous Serial Interface (UART) 16.2 Control TMP89FM42 UART0 control register 1 UART0CR1 (0x001A) Bit Symbol STOPBT EVEN IRDASEL Read/Write After reset Disable Transmit operation Enable Disable Receive operation Enable 1 bit STOPBT Transmit stop bit length 2 bits Odd-numbered parity EVEN Parity selection Even-numbered parity...
  • Page 225 TMP89FM42 UART0 control register 2 UART0CR2 (0x001B) Bit Symbol RTSEL RXDNC STOPBR Read/Write After reset Odd-numbered bits Even-numbered bits of transfer frame of transfer frame 000: 16 clocks 16 clocks 001: 16 clocks 17 clocks 010: 15 clocks 15 clocks RTSEL Selects the number of RT clocks 011:...
  • Page 226 16. Asynchronous Serial Interface (UART) 16.2 Control TMP89FM42 No parity error PERR Parity error flag Parity error No framing error FERR Framing error flag Framing error No overrrun error OERR Overrun error flag Overrun error Before receiving or end of receiving RBSY Receive busy flag On receiving...
  • Page 227 TMP89FM42 16.3 Low Power Consumption Function UART0 has a low power consumption register (POFFCR1) that saves power consumption when the UART func- tion is not used. Setting POFFCR1 to "0" disables the basic clock supply to UART0 to save power. Note that this ren- ders the UART unusable.
  • Page 228 16. Asynchronous Serial Interface (UART) 16.4 Protection to Prevent UART0CR1 and UART0CR2 Regis- TMP89FM42 ters from Being Changed 16.4 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed The TMP89FM42 has a function that protects the registers from being changed so that the UART communication settings (for example, stop bit and parity) are not changed accidentally during the UART operation.
  • Page 229 TMP89FM42 16.5 Activation of STOP, IDLE0 or SLEEP0 Mode 16.5.1 Transition of register status When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically and each register becomes the status as shown in Table 16-4. For the registers that do not hold their values, make settings again as needed after the operation mode is recovered.
  • Page 230 16. Asynchronous Serial Interface (UART) 16.6 Transfer Data Format TMP89FM42 16.6 Transfer Data Format The UART transfers data composed of the following four elements. The data from the start bit to the stop bit is col- lectively defined as a "transfer frame". The start bit consists of 1 bit (L level) and the data consists of 8 bits. Parity bits are determined by UART0CR1...
  • Page 231 TMP89FM42 16.8 Transfer Baud Rate The transfer baud rate of UART is set by UART0CR1, UART0DR and UART0CR2. Table 16-6 and Table 16-7 show the settings of UART0DR and UART0CR2 for general baud rates and operating fre- quencies. For independent calculation of transfer baud rates, refer to "16.8.1 Transfer baud rate calculation method". Table 16-6 Set Values of UART0DR and UART0CR2...
  • Page 232 16. Asynchronous Serial Interface (UART) 16.8 Transfer Baud Rate TMP89FM42 Table 16-7 Set Values of UART0DR and UART0CR2 for Transfer Baud Rates (fs=32.768 kHz, UART0CR2=0y00) Basic baud Operating frequency rate Register 32.768 kHz [baud] UART0DR 0x06 RTSEL 0y011 Error (+0.67%) UART0DR 0x0D RTSEL...
  • Page 233 TMP89FM42 Transfer frame STBT Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop 1 Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0...
  • Page 234 16. Asynchronous Serial Interface (UART) 16.8 Transfer Baud Rate TMP89FM42 RTSEL UARTDR calculation Generated baud rate 4000000 [Hz] 4000000 [Hz] ≈ UARTDR = 35714 [baud] ( 6.99%) 16 38400 [baud] 16 (6 + 1) 4000000 [Hz] 4000000 [Hz] UARTDR = ≈...
  • Page 235 TMP89FM42 16.9 Data Sampling Method The UART receive control circuit starts RT clock counting when it detects a falling edge of the input pulses to the RXD0 pin. 15 to 17 RT clocks are counted per bit and each clock is expressed as RTn (n=16 to 0). In a bit that has 17 RT clocks, RT16 to RT0 are counted.
  • Page 236 16. Asynchronous Serial Interface (UART) 16.9 Data Sampling Method TMP89FM42 If "1" is detected in sampling of the start bit, for example, due to the influence of noise, RT clock counting stops and the data receiving is suspended. Subsequently, when a falling edge is detected in the input pulses to the RXD0 pin, RT clock counting restarts and the data receiving restarts with the start bit.
  • Page 237 TMP89FM42 16.10Received Data Noise Rejection When noise rejection is enabled at UART0CR2, the time of pulses to be regarded as signals is as shown in Table 16-8. Table 16-8 Received Data Noise Rejection Time RXDNC Noise rejection time [s] Time of pulses to be regarded as signals No noise rejection 2 ×...
  • Page 238 16. Asynchronous Serial Interface (UART) 16.11 Transmit/Receive Operation TMP89FM42 16.11Transmit/Receive Operation 16.11.1Data transmit operation Set UART0CR1 to "1". Check UART0SR = "0", and then write data into TD0BUF (transmit data buffer). Writing data into TD0BUF sets UART0SR to "1", transfers the data to the transmit shift register, and outputs the data sequentially from the TXD0 pin.
  • Page 239 TMP89FM42 16.12Status Flag 16.12.1Parity error When the parity determined using the receive data bits differs from the received parity bit, the parity error flag UART0SR is set to "1". At this time, an INTRXD0 interrupt request is generated. If UART0SR is "1" when UART0SR is read, UART0SR will be cleared to "0" when RD0BUF is read subsequently.
  • Page 240 16. Asynchronous Serial Interface (UART) 16.12 Status Flag TMP89FM42 16.12.2Framing Error If the internal and external baud rates differ or "0" is sampled as the stop bit of received data due to the influ- ence of noise on the RXD0 pin, the framing error flag UART0SR is set to "1". At this time, an INTRXD0 interrupt request is generated.
  • Page 241 TMP89FM42 16.12.3Overrun error If receiving of all data bits is completed before the previous received data is read from RD0BUF, the overrun error flag UART0SR is set to "1" and an INTRXD0 interrupt request is generated. The data received at the occurrence of the overrun error is discarded and the previous received data is maintained. Subsequently, if data is received while UART0SR...
  • Page 242 16. Asynchronous Serial Interface (UART) 16.12 Status Flag TMP89FM42 Data A Data B Data C Data D Start Bit0 Parity Stop Start Bit0 Parity Stop Start Bit0 Parity Stop Start Bit0 Parity Stop RXD0 pin input A parity error occurs. The parity is OK.
  • Page 243 TMP89FM42 Data A Data B Start Bit0 Bit1 Bit7 Stop Start Bit0 Bit1 Bit7 Stop RXD0 pin input UART0SR RBFL is cleared to “0” when RD0BUF is read after reading UART0SR RBFL=“1”. OERR is cleared to “0” when RD0BUF is read after reading INTRXD0 interrupt request OERR=“1”.
  • Page 244 16. Asynchronous Serial Interface (UART) 16.12 Status Flag TMP89FM42 16.12.4Receive Data Buffer Full Loading the received data in RD0BUF sets UART0SR to "1". If UART0SR is "1" when UART0SR is read, UART0SR will be cleared to "0" when RD0BUF is read subsequently. If UART0SR...
  • Page 245 TMP89FM42 16.12.5 Transmit busy flag If transmission is completed with no waiting data in TD0BUF (when UART0SR="0"), UART0SR is cleared to "0". When transmission is restarted after data is written into TD0BUF, UART0SR is set to "1". At this time, an INTTXD0 interrupt request is generated. UART0CR1...
  • Page 246 16. Asynchronous Serial Interface (UART) 16.13 Receiving Process TMP89FM42 16.13Receiving Process Figure 16-18 shows an example of the receiving process. Details of flag judgments in the processing are shown in Table 16-10 and Table 16-11. If any framing error or parity error is detected, the received data has erroneous value(s). Execute the error han- dling, for example, by discarding the received data read from RD0BUF and receiving the data again.
  • Page 247 TMP89FM42 Table 16-10 Flag Judgments When No Receive Interrupt Is Used RBFL FERR/PERR OERR State Data has not been received yet. Some pieces of data could not be received during the previ- ous data receiving process (Receiving of next data is completed in the period from when UART0SR is read to when RD0BUF is read in the previous data receiving process.) Receiving has been completed properly.
  • Page 248 16. Asynchronous Serial Interface (UART) 16.14 AC Properties TMP89FM42 16.14AC Properties 16.14.1IrDA properties = 0 V, Topr = −40 to 85°C) Item Condition Typ. Unit Transfer baud rate = 2400 bps – 78.13 – Transfer baud rate = 9600 bps –...
  • Page 249 TMP89FM42 16.15Revision History Description Revised Table 16-6. "16.8.1.1 Bit width adjustment using UART0CR2" Changed example from fcgck=8MHz to fcgck=4MHz. RA001 "16.8.1.2 Calculation of set values of UART0CR2 and UART0DR" Changed example from fcgck=6MHz to fcgck=4MHz. "Figure 16-6 Example of UART0DR Calculation" Changed example from fcgck=6MHz to fcgck=4MHz. "Figure 16-1 Asynchronous Serial Interface (UART)"...
  • Page 250 16. Asynchronous Serial Interface (UART) 16.15 Revision History TMP89FM42...
  • Page 251 TMP89FM42 17. Synchronous Serial Interface (SIO) The TMP89FM42 contains 1 channel of high-speed 8-bit serial interfaces of the clock synchronization type. Table 17-1 SFR Address Assignment SIOxCR SIOxSR SIOxBUF (address) (address) (address) SIO0CR SIO0SR SIO0BUF Serial interface 0 (0x001F) (0x0020) (0x0021) Table 17-2 Pin Names Serial clock...
  • Page 252 17. Synchronous Serial Interface (SIO) 17.1 Configuration TMP89FM42 17.1 Configuration Internal bus INTSIO0 interrupt request SIO0CR SIO0SR SIO0BUF Shift register on transmitter Shift clock Port SO0 pin Control circuit Internal clock (Note) MSB/LSB selection Port SI0 pin (Note) Shift register on receiver SIO0BUF Port SCLK0 pin...
  • Page 253 TMP89FM42 17.2 Control The synchronous serial interface SIO0 is controlled by the low power consumption registers (POFFCR2), the serial interface data buffer register (SIO0BUF), the serial interface control register (SIO0CR) and the serial interface status register (SIO0SR). Low power consumption register 2 POFFCR2 (0x0F76) Bit Symbol...
  • Page 254 17. Synchronous Serial Interface (SIO) 17.2 Control TMP89FM42 Serial interface control register SIO0CR (0x001F) Bit Symbol SIOEDG SIOCKS SIODIR SIOS SIOM Read/Write After reset 0: Receive data at a rising edge and transmit data at a falling edge SIOEDG Transfer edge selection 1: Transmit data at a rising edge and receive data at a falling edge NORMAL1/2 or IDLE1/2 mode SLOW1/2 or SLEEP1 mode...
  • Page 255 TMP89FM42 Serial interface status register SIO0SR (0x0020) Bit Symbol SIOF OERR REND UERR TBFL Read/Write After reset Serial transfer operation status Transfer not in progress SIOF monitor Transfer in progress Shift operation not in progress Shift operation status monitor Shift operation in progress No overrun error has occurred OERR Receive overrun error flag...
  • Page 256 17. Synchronous Serial Interface (SIO) 17.3 Low Power Consumption Function TMP89FM42 17.3 Low Power Consumption Function Serial interface 0 has the low power consumption registers (POFFCR2) that save power when the serial interface is not being used. Setting POFFCR2 to "0" disables the basic clock supply to serial interface 0 to save power. Note that this renders the serial interface unusable.
  • Page 257 TMP89FM42 17.4 Functions 17.4.1 Transfer format The transfer format can be set to either MSB or LSB first by using SIO0CR. Setting SIO0CR to "0" selects LSB first as the transfer format. In this case, the serial data is transferred in sequence from the least significant bit.
  • Page 258 17. Synchronous Serial Interface (SIO) 17.4 Functions TMP89FM42 SLCK0 pin SO0 pin R2 R3 R4 R5 R6 R7 SI0 pin When SIOCR=“0” SCLK0 pin SO0 pin R2 R3 R4 R5 R6 R7 SI0 pin When SIOCR=“1” Figure 17-2 Transfer Edge Note:When an external clock input is used, 4/fcgck or longer is needed between the receive edge at the 8th bit and the transfer edge at the first bit of the next transfer.
  • Page 259 TMP89FM42 17.5 Transfer Modes 17.5.1 8-bit transmit mode The 8-bit transmit mode is selected by setting SIO0CR to "01". 17.5.1.1 Setting Before starting the transmit operation, select the transfer edges at SIO0CR, a transfer format at SIO0CR and a serial clock at SIO0CR. To use the internal clock as the serial clock, select an appropriate serial clock at SIO0CR.
  • Page 260 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 When the internal clock is used and SIO0SR is "0" When the data transmission is completed, the SCLK0 pin becomes the initial state and the SO0 pin becomes the "H" level. SIO0SR remains at "0". When the internal clock is used, the serial clock and data output is stopped until the next transmit data is written into SIO0BUF (automatic wait).
  • Page 261 TMP89FM42 Start operation Reserved stop SIO0CR SIO0CR SIO0SR Automatic wait SIO0SR SIO0SR Internal clock Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SO0 pin (output) SCLK0 pin (output) An interrupt is generated...
  • Page 262 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 Start operation Reserved stop SIO0CR SIO0CR SIO0SR SIO0SR Stopped while keeping the current level in the operation with an external clock SIO0SR Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SO0 pin (output)
  • Page 263 TMP89FM42 Start operation Reserved stop SIO0CR SIO0CR SIO0SR SIO0SR Stopped while keeping the current level in the operation with an external clock SIO0SR SIO0SR Data A Data A Data B Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6...
  • Page 264 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 17.5.2 8-bit Receive Mode The 8-bit receive mode is selected by setting SIO0CR to "10". 17.5.2.1 Setting As in the case of the transmit mode, before starting the receive operation, select the transfer edges at SIO0CR, a transfer format at SIO0CR...
  • Page 265 TMP89FM42 After the operation has stopped completely, SIO0SR are cleared to "0". Other SIO0SR registers keep their values. The receive operation can be forced to stop by setting SIO0CR to "00" during the operation. By setting SIO0CR to "00", SIO0CR and SIO0SR are cleared to "0" and the SIO stops the operation, regardless of the SIO0SR...
  • Page 266 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 Start operation Forced stop Start operation Reserved stop Forced stop SIO0CR SIO0CR Automatic SIO0SR wait SIO0SR SIO0SR Internal clock Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit0 Bit1 Bit2 Bit3 SI0 pin (input)
  • Page 267 TMP89FM42 Start operation Forced stop Start operation SIO0CR SIO0CR SIO0SR SIO0SR SIO0SR Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SI0 pin (input) SCLK0 pin (input) Data B is discarded...
  • Page 268 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 17.5.3 8-bit transmit/receive mode The 8-bit transmit/receive mode is selected by setting SIO0CR to "11". 17.5.3.1 Setting Before starting the transmit/receive operation, select the transfer edges at SIO0CR, a trans- fer format at SIO0CR and a serial clock at SIO0CR. To use the internal clock as the serial clock, select an appropriate serial clock at SIO0CR.
  • Page 269 TMP89FM42 When the internal clock is used If SIO0SR is "1", it is cleared to "0" and the transmit/receive operation continues. If SIO0SR is already "1", SIO0SR is set to "1". If SIO0SR is "0", the transmit/receive operation is aborted. The SCLK0 pin becomes the initial state and the SO0 pin becomes the "H"...
  • Page 270 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 Start operation Reserved stop SIO0CR SIO0SR Wait SIO0SR SIO0SR SIO0SR Internal clock Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SI0 pin (input) Data D...
  • Page 271 TMP89FM42 Start operation Reserved stop SIO0CR SIO0CR SIO0SR SIO0SR SIO0SR SIO0SR Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SI0 pin (input) Data D Data E...
  • Page 272 17. Synchronous Serial Interface (SIO) 17.5 Transfer Modes TMP89FM42 Start operation Reserved stop SIO0CR SIO0SR SIO0SR SIO0SR SIO0SR SIO0SR SIO0SR Data A Data B Data C Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SI0 pin (input) Data D...
  • Page 273 TMP89FM42 17.6 AC Characteristics SCYL SCYH SCLKH SCLK pin SCLKL SI pin SO pin Figure 17-16 AC Characteristics = 0 V, V = 4.5 V - 5.5 V, Topr = -40 to 85°C) Parameter Symbol Condition Typ. Unit SCLK cycle time 2 / fcgck 1 / fcgck SCLK "L"...
  • Page 274 17. Synchronous Serial Interface (SIO) 17.7 Revision History TMP89FM42 17.7 Revision History Description "Table 17-3 Transfer Baud Rate" Revised table (Add some fcgck condition). RA001 "17.6 AC Characteristics" Revised table (Add some fcgck condition).
  • Page 275 TMP89FM42 18. Serial Bus Interface (SBI) The TMP89FM42 contains 1 channels of serial bus interface (SBI). The serial bus interface supports serial communication conforming to the I C bus standards. It has clock synchro- nization and arbitration functions, and supports the multi-master in which multiple masters are connected on a bus. It also supports the unique free data format.
  • Page 276 18. Serial Bus Interface (SBI) 18.1 Communication Format TMP89FM42 (a) Addressing format 8 bits 1 to 8 bits 1 to 8 bits Data Data Slave address 1 or more (b) Addressing format (with restart) 8 bits 1 to 8 bits 8 bits 1 to 8 bits Data...
  • Page 277 TMP89FM42 18.2 Configuration INTSBI Interrupt request Noise canceller Transfer control circuit Clock Software Shift Data control circuit reset circuit register control Noise circuit canceller SBI0CR2 SBI0CR1 I2C0AR SBI0DBR SBI0SR2 Figure 18-4 Serial Bus Interface 0 (SBI0)
  • Page 278 18. Serial Bus Interface (SBI) 18.3 Control TMP89FM42 18.3 Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface control register 1 (SBI0CR1) • Serial bus interface control register 2 (SBI0CR2) •...
  • Page 279 TMP89FM42 ACK=0 ACK=1 Number of Number of data Number of clocks clocks for data Number of data bits bits for data transfer transfer 000: 001: Number of data bits 010: 011: 100: 101: 110: 111: Master mode Slave mode Not generating the clocks for an acknowledge signal.
  • Page 280 18. Serial Bus Interface (SBI) 18.3 Control TMP89FM42 0: Slave Master/slave selection 1: Master 0: Receiver Transmitter/receiver selection 1: Transmitter 0: Generate the stop condition (when MST, TRX and PIN are "1") Start/stop generation 1: Generate the start condition (when MST, TRX and PIN are "1") 0: - (Cannot clear this bit by the software) Cancel interrupt service request 1: Cancel interrupt service request...
  • Page 281 TMP89FM42 C bus address register I2C0AR (0x0024) Bit Symbol Read/Write After reset Slave address setting Slave address in the slave mode C bus mode 0: I Communication format selection 1: Free data format Note 1: Don't set I2C0AR to "0x00". If it is set to "0x00", the slave address is deemed to be matched when the I C bus stan- dard start byte ("0x01") is received in the slave mode.
  • Page 282 18. Serial Bus Interface (SBI) 18.4 Functions TMP89FM42 18.4.2 Selecting the slave address match detection and the GENERAL CALL detection SBI0CR1 enables and disables the slave address match detection and the GENERAL CALL detection in the slave mode. Clearing SBI0CR1 to "0" enables the slave address match detection and the GENERAL CALL detection.
  • Page 283 TMP89FM42 SBI0CR1="110", SBI0CR1="011", SBI0CR1="0" SBI0CR1="1" Figure 18-5 Number of Clocks for Data Transfer and SBI0CR1 and SBI0CR1 The relationship between the number of clocks for data transfer and SBI0CR1 and SBI0CR1 is shown in Table 18-1. Table 18-1 Relationship between the Number of Clocks for Data Transfer and SBI0CR1 and SBI0CR1...
  • Page 284 18. Serial Bus Interface (SBI) 18.4 Functions TMP89FM42 During the data transfer after the slave address match is detected or a "GENERAL CALL" is received in the transmitter mode, the SDA0 pin is released to receive an acknowledge signal from the receiver during the period of the clocks for an acknowledge signal. In the receiver mode, the SDA0 pin is pulled down to the low level and an acknowledge sig- nal is generated.
  • Page 285 TMP89FM42 SCL output 1/fscl HIGH = m / fcgck HIGH t LOW = n / fcgck fscl = 1/(t HIGH + t LOW Figure 18-6 SCL Output Note: There are cases where the HIGH period differs from t selected at SBI0CR1 when the rising HIGH edge of the SCL pin becomes blunt due to the load capacity of the bus.
  • Page 286 18. Serial Bus Interface (SBI) 18.4 Functions TMP89FM42 Count start SCL pin (Master 1) Wait Count reset SCL pin (Master 2) Count reset SCL (Bus) Figure 18-8 Example of Clock Synchronization As Master 1 pulls down the SCL pin to the low level at point "a", the SCL line of the bus becomes the low level.
  • Page 287 TMP89FM42 Table 18-3 SBI0CR1 Operation in Each Mode Mode Direction bit Changing condition TRX after changing "0" A received slave address is "0" Slave mode the same as the value set to "1" "1" I2C0AR "0" "1" Master ACK signal is returned mode "1"...
  • Page 288 18. Serial Bus Interface (SBI) 18.4 Functions TMP89FM42 18.4.8 Interrupt service request and release When a serial bus interface circuit is in the master mode and transferring a number of clocks set by SBI0CR1 and SBI0CR1 is complete, a serial bus interface interrupt request (INTSBI0) is gener- ated.
  • Page 289 TMP89FM42 A software reset is generated by writing "10" and then "01" to SBI0CR2. After a software reset is generated, the serial bus interface circuit is initialized and all the bits of SBI0CR2 register, except SBI0CR2 and the SBI0CR1, I2C0AR and SBI0SR2 registers, are initialized. 18.4.11Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple- mented in order to guarantee the contents of transferred data.
  • Page 290 18. Serial Bus Interface (SBI) 18.4 Functions TMP89FM42 SCL pin Master A D3A D2A D1A D0A D7A’ D6A’ D5A’ SDA pin SCL pin Stop clock output Master B SDA pin Releasing SDA pin and SCL pin to high level as losing arbitration. SBI0SR2...
  • Page 291 TMP89FM42 18.4.13GENERAL CALL detection monitor SBI0SR2 is set to "1" when SBI0CR1 is "0" and GENERAL CALL (all 8-bit received data is "0" immediately after a start condition) in a slave mode. Setting SBI0CR1 to "1" disables the subsequent slave address match and GENERAL CALL detections.
  • Page 292 18. Serial Bus Interface (SBI) 18.5 Data Transfer of I2C Bus TMP89FM42 18.5 Data Transfer of I C Bus 18.5.1 Device initialization Set POFFCR1 to "1". After confirming that the serial bus interface pin is high level, set SBI0CR2 to "1" to select the serial bus interface mode.
  • Page 293 TMP89FM42 Example :Generate the start condition CHK_BB: TEST (SBI0SR2).BB ; Confirms that the bus is free F, CHK_BB (SBI0DBR), 0xcb ; The transmission slave address 0x65 and the direction bit "1" (SBI0CR2), 0xf8 ; Write "1" to SBI0CR2, , and to "1" SCL0 pin SDA0 pin Acknowledgem...
  • Page 294 18. Serial Bus Interface (SBI) 18.5 Data Transfer of I2C Bus TMP89FM42 SCL0 pin Write to SBI0DBR SDA0 pin Acknowledge signal from the receiver SBI0CR2 INTSBI0 Interrupt request Figure 18-18 Example when SBI0CR1="000" and SBI0CR1="1" When SBI0SR2 is "0" (Receiver mode) When the data to be transmitted subsequently is other than 8 bits, set SBI0CR1...
  • Page 295 TMP89FM42 2. Clear SBI0CR1 to "0" and set SBI0CR1 to "001". 3. To set SBI0CR2 to "1", write a dummy data (0x00) to SBI0DBR. Transfer 1-bit data by setting SBI0CR1 to "1". In this case, since the master device is a receiver, the SDA line on a bus keeps the high level. The transmitter receives the high-level signal as a negative acknowledge signal.
  • Page 296 18. Serial Bus Interface (SBI) 18.5 Data Transfer of I2C Bus TMP89FM42 Table 18-4 The Behavior of an interrupt request and SBI0CR2 After Losing Arbitration When the Arbitration Lost Occurs during Transmis- When the Arbitration Lost Occurs during Transmis- sion of Slave Address as a Master sion of Data as Master Transmitter interrupt request An interrupt request is generated at the termination of word-data transfer.
  • Page 297 TMP89FM42 18.5.4 Stop condition generation When SBI0CR2 is "1", a sequence of generating a stop condition is started by setting "1" to SBI0CR2, SBI0CR2 and SBI0CR2 and clearing SBI0CR2 to "0". Do not modify the contents of SBI0CR2, SBI0CR2, SBI0CR2 and SBI0CR2 until a stop condi- tion is generated on a bus.
  • Page 298 18. Serial Bus Interface (SBI) 18.5 Data Transfer of I2C Bus TMP89FM42 Check SBI0SR2 until it becomes "1" to check that the SCL line on the bus is not pulled down to the low level by other devices. After confirming that the bus stays in a free state, generate a start condition in the procedure "18.5.2 Start condition and slave address generation".
  • Page 299 TMP89FM42 18.6 AC Specifications The AC specifications are as listed below. The operating mode (fast or standard) mode should be selected suitable for frequency of fcgck. For these operating mode, refer to the following table. Table 18-6 AC Specifications (Circuit Output Timing) Standard mode Fast mode Parameter...
  • Page 300 18. Serial Bus Interface (SBI) 18.6 AC Specifications TMP89FM42 SBICR2 SU;SCL Figure 18-24 Definition of Timing (No. 2)
  • Page 301 TMP89FM42 18.7 Revision History Description " Serial bus interface control register 1" Revised SCK description. Added Note5. "18.6 AC Specifications" Revised fcgck description. RA001 "Table 18-6 AC Specifications (Circuit Output Timing)" Revised value of "SCL clock frequency". Revised from "normal mode" to "standard mode".
  • Page 302 18. Serial Bus Interface (SBI) 18.7 Revision History TMP89FM42...
  • Page 303 TMP89FM42 19. Key-on Wakeup (KWU) The key-on wakeup is a function for releasing the STOP mode at the pin or at pins KWI7 through KWI0. STOP 19.1 Configuration SYSCR1 Rising edge STOP Port detection Stop mode release signal (to be released Selector if set to “1”) Port...
  • Page 304 19. Key-on Wakeup (KWU) 19.1 Configuration TMP89FM42 19.2 Control Key-on wakeup control registers (KWUCR0 and KWUCR1) can be configured to designate the key-on wakeup pins (KWI7 through KWI0) as STOP mode release pins and to specify the STOP mode release levels of each of these designated pins.
  • Page 305 TMP89FM42 19.3 Functions By using the key-on wakeup function, the STOP mode can be released at a pin or at KWIm pin (m: 0 STOP through 7). After resetting, the pin is the only STOP mode release pin. To designate the KWIm pin as a STOP STOP mode release pin, therefore, it is necessary to configure the key-on wakeup control register (KWUCRn) (n: 0 or 1).
  • Page 306 19. Key-on Wakeup (KWU) 19.1 Configuration TMP89FM42 Example :A case in which STOP mode is started with the release level of the pin set to a high level and the release STOP level of KWI0 set to a low level (connected to an internal pull-up resistor of the KWI0 pin) ;...
  • Page 307 TMP89FM42 20. 10-bit AD Converter (ADC) The TMP89FM42 has a 10-bit successive approximation type AD converter. 20.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 20-1. It consists of control registers ADCCR1 and ADCCR2, converted value registers ADCDRL and ADCDRH, a DA converter, a sample-hold circuit, a comparator, a successive comparison circuit, etc.
  • Page 308 20. 10-bit AD Converter (ADC) 20.2 Control TMP89FM42 20.2 Control The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCR1) This register selects an analog channel in which to perform AD conversion, selects an AD conversion operation mode, and controls the start of the AD converter.
  • Page 309 TMP89FM42 AD converter control register 1 ADCCR1 (0x0034) Bit Symbol ADRS AINEN SAIN Read/Write After reset ADRS AD conversion start AD conversion start AD operation disable, forcibly stop AD operation Single mode AD operating mode Reserved Repeat mode Analog input disable AINEN Analog input control Analog input enable...
  • Page 310 20. 10-bit AD Converter (ADC) 20.2 Control TMP89FM42 AD converter control register 2 ADCCR2 (0x0035) Bit Symbol EOCF ADBF "0" Read/Write After reset Before conversion or during conversion EOCF AD conversion end flag Conversion end AD conversion being halted ADBF AD conversion BUSY flag AD conversion being executed 000:...
  • Page 311 TMP89FM42 AD converted value register (lower side) ADCDRL (0x0036) Bit Symbol AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 Read/Write After reset AD converted value register (upper side) ADCDRH (0x0037) Bit Symbol AD09 AD08 Read/Write After reset Note 1: A read of ADCDRL or ADCDRH must be read after the INTADC interrupt is generated or after ADCCR2 becomes "1".
  • Page 312 20. 10-bit AD Converter (ADC) 20.3 Functions TMP89FM42 20.3 Functions The 10-bit AD converter operates in either single mode in which AD conversion is performed only once or repeat mode in which AD conversion is performed repeatedly. 20.3.1 Single mode In single mode, the voltage at a designated analog input pin is AD converted only once.
  • Page 313 TMP89FM42 The AD converted value registers (ADCDRL and ADDRH) should be read before the next AD conversion is finished. If the next AD conversion is finished in the interim between a read of ADCDRL and a read of ADCDRH, the previous converted value is retained without overwriting the AD converted value registers (ADCDRL and ADCDRH).
  • Page 314 20. 10-bit AD Converter (ADC) 20.4 Register Setting TMP89FM42 20.4 Register Setting 1. Set the AD converter control register 1 (ADCCR1) as described below: • From the AD input channel select (SAIN), select the channel in which AD conversion is to be per- formed.
  • Page 315 TMP89FM42 20.6 Analog Input Voltage and AD Conversion Result Analog input voltages correspond to AD-converted, 10-bit digital values, as shown in Figure 20-4. VAREF/AVDD − VSS 1024 1021 1022 1023 1024 Analog input voltage Figure 20-4 Relationships between Analog Input Voltages and AD-converted Values (typical values)
  • Page 316 20. 10-bit AD Converter (ADC) 20.7 Precautions about the AD Converter TMP89FM42 20.7 Precautions about the AD Converter 20.7.1 Analog input pin voltage range Analog input pins (AIN0 through AIN7) should be used at voltages from VAREF to VSS. If any voltage out- side this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain, and converted values on other pins will also be affected.
  • Page 317 High-speed access to the flash memory is available by control- ling address and data signals directly. To receive a support service for the program writer, please ask a Toshiba sales representative. In MCU and serial PROM modes, flash memory control registers (FLSCR1 and FLSCR2) are used to control the...
  • Page 318 21. Flash Memory TMP89FM42 21.1 Flash Memory Control The flash memory is controlled by the flash memory control register 1 (FLSCR1), flash memory control register 2 (FLSCR2), and flash memory standby control register (FLSSTB). Flash memory control register 1 FLSCR1 (0x0FD0) Bit Symbol FLSMD...
  • Page 319 TMP89FM42 Flash memory control register 1 monitor FLSCRM (0x0FD1) Bit Symbol FLSMDM BAREAM FAREAM ROMSELM Read/Write After reset Monitoring of FLSCR1 FLSCR1="101" setting disabled FLSMDM status FLSCR1="101" setting enabled BAREAM Monitoring of FLSCR1 status Value of currently enabled FLSCR1 FAREAM Monitoring of FLSCR1...
  • Page 320 21. Flash Memory TMP89FM42 Flash memory standby control register FLSSTB (0x0FD2) Bit Symbol FSTB Read/Write After reset Disable flash memory standby FSTB Flash memory standby control Enable flash memory standby Note 1: A value can be written to FSTB only by using a program that resides in RAM. A value written using a program residing in the flash memory will be invalidated.
  • Page 321 TMP89FM42 21.2 Functions 21.2.1 Flash memory command sequence execution and toggle control (FLSCR1 ) To prevent inadvertent writes to the flash memory due to program error or microcontroller malfunction, the execution of the flash memory command sequence and the toggle operation can be disabled (the flash memory can be write protected) by making an appropriate control register setting (write protect).
  • Page 322 21. Flash Memory TMP89FM42 21.2.2 Flash memory area switching (FLSCR1) To perform an erase or write on the flash memory, a memory transfer instruction (command sequence) must be executed. If a memory transfer instruction is used to read or write data, a read or write can be performed only on the data area.
  • Page 323 TMP89FM42 21.2.3 RAM area switching (SYSCR3) If "0xD4" is set on SYSCR4 after SYSCR3 is set to "1" in MCU mode, RAM is mapped to the code area. To restore the RAM area to the initial state of mapping, set SYSCR3 to "0", and then set "0xD4"...
  • Page 324 21. Flash Memory TMP89FM42 0x0000 0x0000 0x0000 0x0000 0x003F 0x003F 0x003F 0x0040 0x0040 0x0040 0xXXXX 0xXXXX 0xXXXX 0xXXXX+1 0x1000 0x1000 0xFFFF 0xFFFF 0xFFFF 0xFFFF Data area Code area Data area Code area If SYSSR4=“0” If SYSSR4=“1” FLSCR1=“0” FLSCR1=“0” 0x0000 0x0000 0x0000 0x0000 0x003F...
  • Page 325 TMP89FM42 If an interrupt occurs when the interrupt vector is assigned to the flash memory area (SYSCR3 = "0" is effective), FSTB is automatically initialized to "0", and then the interrupt vector of the flash memory area is read. If an interrupt occurs when the interrupt vector is assigned to the RAM area (SYSCR3 = "1"...
  • Page 326 21. Flash Memory TMP89FM42 21.3 Command Sequence In MCU and serial PROM modes, the command sequence consists of six commands (JEDEC compatible), as shown in Table 21-1. Table 21-1 Command Sequence 1st Bus Write 2nd Bus Write 3rd Bus Write 4th Bus Write 5th Bus Write 6th Bus Write...
  • Page 327 TMP89FM42 21.3.2 Sector erase (4-kbyte partial erase) This command erases the flash memory in units of 4 kbytes. The flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address. The range of addresses that can be specified is shown in Table 21-3.
  • Page 328 21. Flash Memory 21.4 Toggle Bit (D6) TMP89FM42 21.3.4 Product ID entry This command activates the product ID mode. If an instruction to read the flash memory is executed in Prod- uct ID mode, the vendor ID, flash ID and security status can be read from the flash memory. Table 21-4 Values to Be Read in Product ID Mode Address Meaning...
  • Page 329 TMP89FM42 21.5 Access to the Flash Memory Area A read or a program fetch cannot be performed on the whole of the flash memory area if data is being written to the flash memory, if data in flash memory is being erased or if a security setting is being made in the flash memory. When performing these operation on the flash memory area, the flash memory cannot be directly accessed by using a program in the flash memory;...
  • Page 330 21. Flash Memory 21.4 Toggle Bit (D6) TMP89FM42 10. Set FLSCR1 to "0y010", and then set "0xD5" on FLSCR2 (to disable the execution of the command sequence). Note 1: If the RAM loader is used in serial PROM mode, the BOOTROM disables (DI) a maskable interrupt, and the interrupt vector area is designated as a RAM area (SYSCR3="1").
  • Page 331 TMP89FM42 sAddConv: WA,IX SWAP C,0x10 SWAP W,0x08 C,0x08 SHRC C,0xA0 ; Enable the execution of command sequence. Make the (FLSCR1),C FAREA setting. (FLSCR2),0xD5 ; Reflect the FLSCR1 setting WA,IX TEST Z,sAddConvEnd W,0x80 IX,WA sAddConvEnd: ; Interrupt subrou- tine sINTWDT: ; Error processing RETN sINTSWI: ;...
  • Page 332 21. Flash Memory 21.4 Toggle Bit (D6) TMP89FM42 21.5.2 Flash memory control in MCU mode In MCU mode, a write can be performed on the flash memory by executing a control program in RAM or using a support program (API) provided inside BOOTROM. 21.5.2.1 How to write to the flash memory by transferring a control program to the RAM area This section describes how to execute a control program in RAM in MCU mode.
  • Page 333 TMP89FM42 Note 3: Before jumping from the flash memory to the RAM area, RAM must be allocated to the code area by making the appropriate SYSCR3 setting (setting made in step 4 in the procedure described on the previous page). Example: Case in which a program is transferred to RAM, a sector erase is performed on 0xE000 through 0xEFFF in the code area, and then 0x3F data is written to 0xE500.
  • Page 334 21. Flash Memory 21.4 Toggle Bit (D6) TMP89FM42 sLOOP1: A,(IX) ; (steps 8,14) A,(IX) NZ,sLOOP1 ; Loop until the read values become the same ; Disable the execution of command sequence (steps 9 and (FLSCR1),0x40 (FLSCR2),0xD5 ; Reflect the FLSCR1 setting ;...
  • Page 335 TMP89FM42 21.5.2.2 How to write to the flash memory by using a support program (API) of BOOTROM This section describes how to perform an erase and a write on the flash memory by using a support pro- gram (API) of BOOTROM in MCU mode. Example: Case in which a sector erase is performed on 0xE000 through 0xEFFF in the data area, and then data at 0x0100 through 0x01FF is written to 0xE000 through 0xE0FF in the data area.
  • Page 336 21. Flash Memory 21.4 Toggle Bit (D6) TMP89FM42 (FLSCR2),0xD5 Note 1: Make sure that you set the C register to "0x00".
  • Page 337 TMP89FM42 21.6 Revision History Description RA003 "Figure 21-2 Show/Hide Switching for BOOTROM and RAM" Revised from WDTCR1 to SYSSR4...
  • Page 338 21. Flash Memory 21.4 Toggle Bit (D6) TMP89FM42...
  • Page 339 TMP89FM42 22. Serial PROM Mode 22.1 Outline The TMP89FM42 has a 4K-byte BOOTROM (Mask ROM) for programming to flash memory. BOOTROM is available in serial PROM mode. The serial PROM mode is controlled by RXD0/SI0 pins, TXD0/SO0 pins, MODE pin, and pin.
  • Page 340 22. Serial PROM Mode 22.3 Serial PROM Mode Setting TMP89FM42 22.3 Serial PROM Mode Setting 22.3.1 Serial PROM mode control pins To execute on-board programming, activate the serial PROM mode. Table 22-2 shows the pin setting used to activate the serial PROM mode. Table 22-2 Serial PROM Mode Setting Setting RXD0 / SI0 / P21 pin...
  • Page 341 TMP89FM42 TMP89FM42 (4.5 V to 5.5 V) Pull-up resistors SCLK0 RXD0 (P21) External control XOUT TXD0 (P20) RESET MODE Figure 22-1 Serial PROM Mode Pin Setting Note 1: In the case of access using the UART, the control of the SCLK0 pin is unnecessary. Note 2: For information on other pin settings, refer to "Table 22-3 Pin Functions in Serial PROM Mode".
  • Page 342 22. Serial PROM Mode 22.4 Example Connection for On-board Writing TMP89FM42 22.4 Example Connection for On-board Writing Figure 22-2 shows example connections to perform on-board writing. (4.5 V to 5.5 V) Pull-up resistors RXD0 (P21) Level PC control converter TXD0 (P20) (Note 2) Other RESET...
  • Page 343 TMP89FM42 22.5 Activating the Serial PROM Mode Activate the serial PROM mode by performing the following procedure. For information on the detailed timing, refer to "22.14.1 Reset timing". 1. Supply power to the VDD pin. 2. Set the and MODE pins to low. RESET 3.
  • Page 344 22. Serial PROM Mode 22.6 Interface Specifications TMP89FM42 22.6 Interface Specifications The serial PROM mode supports two communication methods: UART and SIO. The communication method is selected based on the first serial data value received after a reset. To execute an on-board program, the communication format of the external controller (personal computer, micro- controller, etc.) must be set as described below.
  • Page 345 TMP89FM42 Table 22-4 Usable Baud Rates as a General Guideline 9600 bps 19200 bps 38400 bps 57600bps 115200 bps 128000 bps Ο Ο Ο Ο Ο Ο 10 MHz Ο Ο Ο Ο Ο Ο 8 MHz Ο Ο Ο Ο...
  • Page 346 22. Serial PROM Mode 22.7 Memory Mapping TMP89FM42 22.7 Memory Mapping Figure 22-3 shows memory maps in serial PROM and MCU modes. In serial PROM mode, the BOOTROM (mask ROM) is mapped to the 0x1000 through 0x17FF in the data area and 0x1000 through 0x1FFF in the code area respectively.
  • Page 347 TMP89FM42 Table 22-5 Operation Command in Serial PROM Mode Command data Operation command Description After a reset is released, the serial PROM mode always starts operation with this Setup command. 0x86 or 0x30 (matching data 1, 2) If matching data 1 is 0x86, communication starts in the UART format. If matching data 1 is 0x30, communication starts in the SIO format.
  • Page 348 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 4. RAM loader command The RAM loader transfers the Intel Hex format data sent by the external controller to the built-in RAM. If it completes the data transfer normally, it calculates the checksums, transmits the calculation results, jumps to the RAM address specified by the first data record, and starts to execute the user program.
  • Page 349 TMP89FM42 22.8.1 Flash memory erase command (0xF0) Table 22-6 shows the flash memory erase commands. Table 22-6 Flash Memory Erase Commands Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte Baud rate TMP89FM42 external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment...
  • Page 350 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.1.1 Specifying the erase area The flash memory erase command is used to specify an area in flash memory to be erased at n-th-2 byte; specifically, ERASEC is used to specify the address of an area to be erased. If data of less than 0x20 is specified, Sector Erase (erasing flash memory in 4K-byte units) is executed..
  • Page 351 TMP89FM42 Note 1: If Sector Erase is performed on an area where flash memory does not exist, the TMP89FM42 stops communication, and goes into an idle state. Note 2: If Reserved data is transmitted, the TMP89FM42 stops communication, and goes into an idle state.
  • Page 352 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.2 Flash memory write command (operation command: 0x30) Table 22-7 shows the transfer formats of flash memory write commands. Table 22-7 Transfer Formats of Flash Memory Write Commands Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte Baud rate...
  • Page 353 TMP89FM42 Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 4: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM42 stops communication, and goes into an idle state.
  • Page 354 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.3 Flash memory read command (operation command: 0x40) Table 22-8 shows the transfer formats of the flash memory read command. Table 22-8 Transfer Formats of the Flash Memory Read Command Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte Baud rate...
  • Page 355 TMP89FM42 Table 22-9 Transfer Formats of the Flash Memory Read Command Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte Baud rate TMP89FM42 external controller m-th + 13 byte Baud rate after adjustment Memory data n-th - 2 byte Baud rate after adjustment Memory data...
  • Page 356 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.4 RAM loader command (operation command: 0x60) Table 22-10 shows the transfer formats of the RAM loader command. Table 22-10 Transfer Formats of the RAM Loader Command Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte Baud rate...
  • Page 357 TMP89FM42 Note 4: After sending a password string, do not send the end record only. If the TMP89FM42 receives the end record after receiv- ing a password string, it may malfunction. Note 5: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM42 stops communication, and goes into an idle state.
  • Page 358 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.5 Flash memory SUM output command (operation command: 0x90) Table 22-11 shows the transfer formats of the flash memory SUM output command. Table 22-11 Transfer Formats of the Flash Memory SUM Output Command Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte...
  • Page 359 TMP89FM42 22.8.6 Product ID code output command (operation command: 0xC0) Table 22-12 shows the transfer formats of the product ID code output command. Table 22-12 Transfer Formats of the Product ID Code Output Command Transfer data from the external controller to Transfer data from TMP89FM42 to the external Transfer byte Baud rate...
  • Page 360 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 Note 4: 22nd through 27th bytes show the flash memory area and RAM area that can be used by the RAM loader. Because the range of addresses shown here does not include the work area used by BOOTROM, it is smaller than the size of a RAM built into an actual product.
  • Page 361 TMP89FM42 22.8.7 Flash memory status output command (0xC3) Table 22-14 shows the flash memory status output commands. Table 22-14 Flash Memory Status Output Commands Transfer data from the external controller to Transfer data from TMP89FM42 to the exter- Transfer byte Baud rate TMP89FM42 nal controller...
  • Page 362 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.7.1 Flash memory status code The flash memory status code is 7-byte data. It shows the status of the flash memory security program and that of the address from 0xFFE0 to 0xFFFF. Table 22-15 Flash Memory Status Code Data Description...
  • Page 363 TMP89FM42 Flash memory erase Flash memory overwrite Flash memory SUM out- command command, flash memory put command, product Flash memory security RPENA BLANK EPFC DAFC read command, and ID output command, and setting command Sector Chip erase RAM loader command status output command erase ×...
  • Page 364 22. Serial PROM Mode 22.8 Operation Commands TMP89FM42 22.8.8 Mask ROM emulation setting command (0xD0) Table 22-16 shows the mask ROM emulation setting command. This command is nonfunctional in the TMP89FM42. It becomes functional if used for a product with flash memory of more than 96Kbytes.
  • Page 365 TMP89FM42 22.8.9 Flash memory security setting command (0xFA) Table 22-17 shows the flash memory security setting command. Table 22-17 Flash Memory Security Setting Command Transfer data from the external controller to Transfer data from TMP89FM42 to the Transfer byte Baud rate TMP89FM42 external controller 1st byte...
  • Page 366 22. Serial PROM Mode 22.9 Error Code TMP89FM42 22.9 Error Code Table 22-18 shows the error codes that the TMP89FM42 transmits when it detects errors. Table 22-18 Error Codes Data transmitted Meaning of error data 0x63, 0x63, 0x63 Operation command error 0xA1, 0xA1, 0xA1 Framing error in the received data 0xA3, 0xA3, 0xA3...
  • Page 367 TMP89FM42 22.10Checksum (SUM) For the following operation commands, a checksum is returned to verify the appropriateness of the result of com- mand execution: - Flash memory erase command (0xF0) - Flash memory write command (0x30) - Flash memory SUM output command (0x30) - Flash memory read command (0x40) - RAM loader command (0x60) - Product ID code output command (0xC0)
  • Page 368 22. Serial PROM Mode 22.11 Intel Hex Format (Binary) TMP89FM42 22.11Intel Hex Format (Binary) For the following two commands, the Intel Hex format is used in part of the transfer format: - Flash memory write command (0x30) - RAM loader command (0x60) For information on the definition of the Intel Hex format, refer to Table 22-20.
  • Page 369 TMP89FM42 22.12Security In serial PROM mode, two security functions are provided to prohibit illegal memory access attempts by a third party: password and security program functions. 22.12.1Passwords A password is one of the security functions, and can be used when the TMP89FM42 operates in serial PROM mode or when the on-chip debugging function (hereafter called OCD) is used.
  • Page 370 22. Serial PROM Mode 22.12 Security TMP89FM42 RXD/SI pin 0x00 0xF0 0x12 0x00 0xF1 0x07 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Password string PNSA PCSA Flash memory 0xF012 0x08 0x08 is the number of passwords. Compare 0xF107 0x01 0xF108 0x02 0xF109...
  • Page 371 TMP89FM42 22.12.1.3Password setting, cancellation and authentication • Password setting Because a password is created by using part of a user program, a special password setting routine is unnecessary. A password can be set by simply writing a program to flash memory. •...
  • Page 372 22. Serial PROM Mode 22.12 Security TMP89FM42 Note 1: *: Don’t care. Note 2: When addresses from 0xFFE0 through 0xFFFF are filled with "0xFF", the product is recognized as a blank product. Note 3: The data including the same consecutive data (three or more bytes) cannot be used as a password. (A password error occurs during password authentication.
  • Page 373 TMP89FM42 22.12.2Security program The security program can be used in parallel and serial PROM modes and for OCD. It has a special memory for protection, and a special command is required to make this protection setting. If the security program is enabled, the reading or writing of flash memory in parallel PROM mode is prohibited.
  • Page 374 22. Serial PROM Mode 22.12 Security TMP89FM42 22.12.3Option codes If a specified option code is placed at a specified address inside the interrupt vector area, whether password string authentication is performed or not when executing the flash memory erase command and whether the security program is checked or not when starting OCD can be designated.
  • Page 375 TMP89FM42 Example :Case in which the password authentication and OCD security program authentication are disabled Vector Section romdata abs = 0xFFFA 0xFF ; Cancel the password string during the erase operation (EPFC_OP) 0xFF ; Permit access when the OCD is started (DAFC_OP)
  • Page 376 22. Serial PROM Mode 22.12 Security TMP89FM42 22.12.4Recommended settings Table 22-23 shows the option codes and recommended security program settings. Table 22-23 Option Codes and Recommended Security Program Settings Device status Serial PROM mode Parallel PROM mode EPFC_OP DAFC_OP Security Memory Memory Erase...
  • Page 377 TMP89FM42 22.13Flowchart Figure 22-5 Flowchart...
  • Page 378 22. Serial PROM Mode 22.14 AC Characteristics (UART) TMP89FM42 22.14AC Characteristics (UART) Table 22-24 UART Timing-1 Minimum required time Clock frequency Parameter Symbol (fcgck) At fcgck = 1 MHz At fcgck = 10 MHz 660 µs 66 µs Time from when MCU receives 0x86 to when it echoes back CMeb1 Approx.
  • Page 379 TMP89FM42 22.14.1Reset timing MODE RSsup RESET (0x86) (0x79) RXsup (0x86) (0x79) CMtr1 CMtr2 CMtr3 CMeb1 CMeb2 CMeb3 Operation command Figure 22-6 Reset Timing 22.14.2Flash memory erase command (0xF0) PNSA PCSA Password string Area to be erased [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] (0xF0) CMtr3...
  • Page 380 22. Serial PROM Mode 22.14 AC Characteristics (UART) TMP89FM42 22.14.3Flash memory write command (0x30) PNSA PCSA Password string IntelHex [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] (0x3A) (0x30) CMtr3 IntelHex(End Record) (0x00) (0x00) (0x01) (0xFF) Next command (0x55) or (0xAA) [15:8] [7:0] Checksum Overwrite CMwr...
  • Page 381 TMP89FM42 22.14.5RAM loader command (0x60) PNSA PCSA Password string IntelHex [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] (0x3A) (0x60) CMtr3 IntelHex(End Record) (0x00) (0x00) (0x01) (0xFF) Next command [15:8] [7:0] Checksum CMrsm CMnx Figure 22-10 RAM Loader Command 22.14.6Flash memory SUM output command (0x90) Next command (0x55) or (0xAA)
  • Page 382 22. Serial PROM Mode 22.14 AC Characteristics (UART) TMP89FM42 22.14.8Flash memory status output command (0xC3) Next command (0xC3) Status code CMnx Figure 22-13 Flash Memory Status Output Command 22.14.9Mask ROM emulation setting command (0xD0) Figure 22-14 Mask ROM Emulation Setting Command 22.14.10Flash memory security setting command (0xFA) PNSA PCSA...
  • Page 383 TMP89FM42 22.15Revision History Description Added P20 and P21 description to TXD0 and RXD0 pin. RA002 "Table 22-24 UART Timing-1", "Table 22-25 UART Timing-2" Deleted VDD and Topr condition. These condition is defined in Electrical Characteristics.
  • Page 384 22. Serial PROM Mode 22.15 Revision History TMP89FM42...
  • Page 385 TMP89FM42 23. On-chip Debug Function (OCD) The TMP89FM42 has an on-chip debug function. Using a combination of this function and the TOSHIBA on-chip debug emulator RTE870/C1, the user is able to perform software debugging in the on-board environment. This emu- lator can be operated from a debugger installed on a PC so that the emulation and debugging functions of an applica- tion program can be used to modify a program or for other purposes.
  • Page 386 The on-chip debug emulator RTE870/C1 can be connected to a target system via an interface control cable. TOSHIBA provides a connector for this interface control cable as an accessory tool. Mounting this connector on a target system will make it easier to use the on-chip debug function.
  • Page 387 TMP89FM42 24. Input/Output Circuit 24.1 Control Pins The input/output circuitries of the TMP89FM42 control pins are shown below. Control pin Circuitry Remarks Input Refer to the P0 ports in the chapter of Input/Output Ports. XOUT Output XTIN Input Refer to the P0 ports in the chapter of Input/Output Ports. XTOUT Output Input...
  • Page 388 24. Input/Output Circuit 24.1 Control Pins TMP89FM42...
  • Page 389 TMP89FM42 25. Electrical Characteristics 25.1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user.
  • Page 390 25. Electrical Characteristics 25.2 Operating Conditions TMP89FM42 25.2 Operating Conditions The operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur.
  • Page 391 TMP89FM42 25.2.2 MCU mode (Except Flash Programming or erasing) = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Unit fc = 10.0 MHz fc = 8.0 MHz NORMAL1, 2 modes fcgck = 10.0 MHz IDLE0, 1, 2 modes fcgck = 4.2 MHz Supply voltage fcgck = 2.0 MHz...
  • Page 392 25. Electrical Characteristics 25.2 Operating Conditions TMP89FM42 25.2.3 Serial PROM mode = 0 V, Topr = −10 to 40°C) Parameter Symbol Pins Condition Unit Supply voltage NORMAL1, 2 modes × 0.70 MODE pin ≥ 4.5 V Input high voltage × 0.75 Hysteresis input ×...
  • Page 393 TMP89FM42 25.3 DC Characteristics = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Typ. Unit − − Hysteresis voltage Hysteresis input MODE = 5.5 V P0, P1, P2, P4, P5, P7, P8, P9, = 5.5 V/0 V −...
  • Page 394 25. Electrical Characteristics 25.3 DC Characteristics TMP89FM42 = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Typ. Unit When a program − = 5.5 V operates on flash 14.5 20.0 Supply current in memory = 5.3 V/0.2 V NORMAL 1, 2 modes (Note 7) =5.3V/0.1V...
  • Page 395 TMP89FM42 1 machine cycle Program counter (PC) Momentary flash current DDP-P [mA] Sum of average momentary flash Maximum current current and Typical current MCU current MCU current Figure 25-4 Intermittent Operation of Flash Memory 1 machine cycle Program counter (PC) Internal data bus Internal write signal Last write cycle of each of the Byte Program,...
  • Page 396 25. Electrical Characteristics 25.4 AD Conversion Characteristics TMP89FM42 25.4 AD Conversion Characteristics = 0.0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Typ. Unit Analog reference voltage / Power sup- AREF ply voltage of analog control circuit −...
  • Page 397 TMP89FM42 25.5 Power-on Reset Circuit Characteristics Power supply voltage (V Operating voltage PROFF PRON PRON PROFF Power-on reset signal Warm-up counter start Warm-up counter clock PWUP CPU and peripheral circuit reset signal Figure 25-6 Power-on Reset Operation Timing Note: Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluc- tuations in the power supply voltage (V =0 V, Topr = −40 to 85°C) Symbol...
  • Page 398 25. Electrical Characteristics 25.6 Voltage Detecting Circuit Characteristics TMP89FM42 25.6 Voltage Detecting Circuit Characteristics Power supply voltage (V Operating voltage Level of detected voltage VLTPW VLTON VLTOFF Signal to request the voltage detection interrupt Voltage detection reset signal Figure 25-7 Operation Timing of the Voltage Detecting Circuit Note: Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluc- tuations in the power supply voltage (V = 0 V, Topr = −40 to 85°C)
  • Page 399 TMP89FM42 25.7 AC Characteristics 25.7.1 MCU mode (Flash programming or erasing) = 0 V, V = 4.5 V to 5.5 V, Topr = −10 to 40°C) Parameter Symbol Condition Typ. Unit NORMAL1, 2 modes − 0.100 IDLE0, 1, 2 modes µs Machine cycle time SLOW1, 2 modes...
  • Page 400 25. Electrical Characteristics 25.8 Flash Characteristics TMP89FM42 = 0 V, V = 2.2 V to 2.7 V, Topr = −40 to 85°C) Parameter Symbol Condition Typ. Unit NORMAL1, 2 modes − 0.500 IDLE0, 1, 2 modes µs Machine cycle time SLOW1, 2 modes −...
  • Page 401 TMP89FM42 25.9 Recommended Oscillating Condition- 1 TOUT (1) High-frequency oscillation (2) Low-frequency oscillation Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted.
  • Page 402 25. Electrical Characteristics 25.10 Handling Precaution TMP89FM42 25.10Handling Precaution - The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown below. 1. When using the Sn-37Pb solder bath Solder bath temperature = 230°C Dipping time = 5 seconds Number of times = once R-type flux used...
  • Page 403 TMP89FM42 25.11Revision History Description The maximum value of the operation frequency is changed from 8MHz to 10MHz. RA001 Added figure for "Clock gear (fcgck) and High-frequency clock (fc)". "25.4 AD Conversion Characteristics" Fixed spec. "25.5 Power-on Reset Circuit Characteristics" Revised table (I Unit) from "ms"...
  • Page 404 25. Electrical Characteristics 25.11 Revision History TMP89FM42...
  • Page 405 TMP89FM42 26. Package Dimensions LQFP44-P-1010-0.80B Rev 01 Unit: mm 12.0 0.2 10.0 0.2 0.08 0.37 1.0TYP 0.07 0.6 0.15...
  • Page 406 26. Package Dimensions TMP89FM42...
  • Page 407 This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C1 (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively.

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