Epson S1D13504 Manuals

Manuals and User Guides for Epson S1D13504. We have 2 Epson S1D13504 manuals available for free PDF download: Technical Manual

Epson S1D13504 Technical Manual (556 pages)

Color Graphics LCD/CRT Controller

Brand: Epson | Category: Controller | Size: 5.13 MB

This Page Left Blank

9
This Page Left Blank

143
- 1 Introduction
  
  147
- 2 Programming the S1D13504 Registers
  
  148
  - Registers Requiring Special Consideration
    148
    
    REG[01] Bit 0 - Memory Type
    148
    
    REG[02] Bit 1 - Dual/Single Panel Type
    148
    
    REG[22] Bits 7-2 - Performance Enhancement Register 0
    148
    
    REG[1B] Bit 0 - Half Frame Buffer Disable
    149
    
    REG[23] Display FIFO
    149
  - Register Initialization
    149
    
    Initialization Sequence
    149
    
    Initialization Example
    150
    
    Re-Programming Registers
    151
  - Disabling the Half Frame Buffer Sequence
    151
- 3 Display Buffer
  
  152
- 4 Advanced Techniques
  
  163
  - Virtual Display
    163
    
    Examples
    164
    
    Registers
    164
  - Panning and Scrolling
    165
    
    Registers
    166
    
    Examples
    167
  - Split Screen
    168
    
    Registers
    168
    
    Examples
    169
- 5 LCD Power Sequencing and Power Save Modes
  
  170
  - Introduction to LCD Power Sequencing
    170
  - Introduction to Power Save Modes
    170
  - Registers
    170
  - Suspend Sequencing
    171
    
    Suspend Enable Sequence
    171
    
    Suspend Disable Sequence
    172
  - LCD Enable/Disable Sequencing (Reg[0D] Bit 0)
    172
- 6 CRT Considerations
  
  173
  - Introduction
    173
    
    CRT Only
    173
    
    Simultaneous Display
    174
- 7 Identifying the S1D13504
  
  178
- 8 Hardware Abstraction Layer (HAL)
  
  179
  - Introduction
    179
  - Screen Manipulation
    181
  - Color Manipulation
    187
  - Drawing
    190
  - Register Manipulation
    192
  - Miscellaneous
    192
- 9 Sample Code
  
  194
  - Introduction
    194
    
    Sample Code Using 13504HAL API
    194
    
    Sample Code Without Using 13504HAL API
    195
- Appendix A Supported Panel Values
  
  201
This Page Left Blank

208
- 13504Cfg.exe
  
  212
- Program Requirements
  
  213
  - Installation
    213
  - Usage
    213
- Script Mode
  
  214
- Interactive Mode
  
  215
  - 13504CFG Menu Bar
    215
    
    Viewing 13504CFG Menu Contents
    215
    
    Making 13504CFG Menu Selections
    216
    
    Files Menu
    217
    
    View Menu
    218
    
    Device Menu
    220
    
    Panel
    221
    
    Crt
    223
    
    Advanced Memory
    225
    
    Power Management
    227
    
    Lookup Table (LUT)
    229
    
    Setup
    231
    
    Help Menu
    232
  - Comments
    233
  - Sample Program Messages
    233
13504Dcfg Menus

269
- 13504Dcfg
  271
- Installation
  272
- Usage
  272
- 13504DCFG Configuration Tabs
  273
  - General Tab
    273
  - Preferences Tab
    275
  - Memory Tab
    276
  - Clocks Tab
    279
  - Panel Tab
    281
  - CRT Tab
    285
  - Registers Tab
    286
- 13504DCFG Menus
  287
  - Export
    287
  - Enable Tooltips
    288
  - ERD on the Web
    288
  - Update Common Controls
    288
  - About 13504DCFG
    288
- Comments
  289
This Page Left Blank

353
- 1 Introduction
  
  357
  - Features
    357
- 2 Installation and Configuration
  
  358
- 3 LCD / RAMDAC Interface Pin Mapping
  
  359
- 4 CPU / BUS Interface Connector Pinouts
  
  360
- 5 Host Bus Interface Pin Mapping
  
  362
- 6 Technical Description
  
  363
  - ISA Bus Support
    363
  - Non-ISA Bus Support
    364
  - DRAM Support
    364
  - Decode Logic
    364
  - Clock Input Support
    364
  - Monochrome LCD Panel Support
    365
  - Color Passive LCD Panel Support
    365
  - Color TFT LCD Panel Support
    365
  - External CMOS RAMDAC Support
    365
  - Power Save Modes
    366
  - Core VDD Power Supply
    366
  - IO VDD Power Supply
    366
  - Adjustable LCD Panel Negative Power Supply
    366
  - Adjustable LCD Panel Positive Power Supply
    366
  - Cpu/Bus Interface Header Strips
    367
  - Schematic Notes
    367
- 7 Parts List
  
  368
- 8 Schematic Diagrams
  
  370
Table of Contents

379
- 2 Features
  
  384
- 3 Installation and Configuration
  
  385
  - Configuration Jumpers
    386
- 4 Technical Description
  
  390
  - PCI Bus Support
    390
  - Non-PCI Host Interface Support
    390
    
    CPU Interface Pin Mapping
    391
    
    CPU Bus Connector Pin Mapping
    392
  - LCD Support
    394
    
    LCD Interface Pin Mapping
    395
    
    Adjustable LCD Panel Positive Power Supply (VDDH)
    396
    
    Buffered LCD Connector
    396
    
    Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD)
    396
  - Current Consumption Measurement
    397
- 6 Parts List
  
  399
- 7 Schematics
  
  401
- 8 Board Layout
  
  406
- 9 Technical Support
  
  407
  - EPSON LCD/CRT Controllers (S1D13504)
    407
Table of Contents

411
- 1 Introduction
  
  415
- 2 Interfacing to the PR31500/PR31700
  
  416
- 3 S1D13504 Host Bus Interface
  
  417
  - Generic MPU Host Bus Interface Pin Mapping
    417
  - Generic MPU Host Bus Interface Signals
    418
- 4 Direct Connection to the Philips PR31500/PR31700
  
  419
  - Hardware Description
    419
  - Memory Mapping and Aliasing
    420
  - S1D13504 Configuration
    421
- 5 System Design Using the IT8368E PC Card Buffer
  
  422
  - Hardware Description-Using One IT8368E
    422
  - IT8368E Configuration
    426
  - Memory Mapping and Aliasing
    427
  - S1D13504 Configuration
    428
- 6 Software
  
  429
Table of Contents

439
- 1 Introduction
  
  443
- 2 Interfacing to the NEC VR4102
  
  444
  - The NEC VR4102 System Bus
    444
    
    Overview
    444
    
    LCD Memory Access Cycles
    445
- 3 S1D13504 Host Bus Interface
  
  446
  - Generic MPU Host Bus Interface Pin Mapping
    446
  - Generic MPU Host Bus Interface Signals
    447
- 4 VR4102 to S1D13504 Interface
  
  448
  - Hardware Description
    448
  - S1D13504 Hardware Configuration
    449
- 5 Software
  
  451
- 6 References
  
  452
  - Documents
    452
  - Document Sources
    452
- 7 Technical Support
  
  453
  - EPSON LCD/CRT Controllers (S1D13504)
    453
  - NEC Electronics Inc. (VR4102)
    453
This Page Left Blank

457
- 1 Introduction
  
  461
- 2 Interfacing to the MC68328
  
  462
  - The 68328 System Bus
    462
  - Chip-Select Module
    462
- 3 S1D13504 Host Bus Interface
  
  463
  - Generic MPU Host Bus Interface Pin Mapping
    463
  - Generic MPU Host Bus Interface Signals
    464
- 4 MC68328 to S1D13504 Interface
  
  465
  - Hardware Description
    465
  - S1D13504 Hardware Configuration
    467
  - MC68328 Chip Select Configuration
    468
- 5 Software
  
  469
- 6 References
  
  470
  - Documents
    470
  - Document Sources
    470
- 7 Technical Support
  
  471
  - EPSON LCD/CRT Controllers (S1D13504)
    471
  - Motorola MC68328 Processor
    471

Epson S1D13504 Technical Manual (504 pages)

Color Graphics LCD/CRT Controller

Brand: Epson | Category: Controller | Size: 4.73 MB

This Page Left Blank

9
This Page Left Blank

141
- 1 Introduction
  
  145
- 2 Programming the S1D13504 Registers
  
  146
  - Registers Requiring Special Consideration
    146
    
    REG[01] Bit 0 - Memory Type
    146
    
    REG[02] Bit 1 - Dual/Single Panel Type
    146
    
    REG[22] Bits 7-2 - Performance Enhancement Register 0
    146
    
    REG[1B] Bit 0 - Half Frame Buffer Disable
    147
    
    REG[23] Display FIFO
    147
  - Register Initialization
    147
    
    Initialization Sequence
    147
    
    Initialization Example
    148
    
    Re-Programming Registers
    149
  - Disabling the Half Frame Buffer Sequence
    149
- 3 Display Buffer
  
  150
- 4 Advanced Techniques
  
  161
  - Virtual Display
    161
    
    Examples
    162
    
    Registers
    162
  - Panning and Scrolling
    163
    
    Registers
    164
    
    Examples
    165
  - Split Screen
    166
    
    Registers
    166
    
    Examples
    167
- 5 LCD Power Sequencing and Power Save Modes
  
  168
  - Introduction to LCD Power Sequencing
    168
  - Introduction to Power Save Modes
    168
  - Registers
    168
  - Suspend Sequencing
    169
  - Suspend Enable Sequence
    169
  - Suspend Disable Sequence
    170
  - LCD Enable/Disable Sequencing (Reg[0D] Bit 0)
    170
- 6 CRT Considerations
  
  171
  - Introduction
    171
    
    CRT Only
    171
    
    Simultaneous Display
    172
- 7 Identifying the S1D13504
  
  176
- 8 Hardware Abstraction Layer (HAL)
  
  177
  - Introduction
    177
  - Api for 13504Hal
    177
    
    Screen Manipulation
    179
    
    Color Manipulation
    185
    
    Drawing
    188
    
    Miscellaneous
    190
    
    Register Manipulation
    190
- 9 Sample Code
  
  192
  - Introduction
    192
    
    Sample Code Using 13504HAL API
    192
    
    Sample Code Without Using 13504HAL API
    193
- Appendix A Supported Panel Values
  
  199
This Page Left Blank

206
- 13504Cfg.exe
  
  210
- Program Requirements
  
  211
  - Installation
    211
  - Usage
    211
- Script Mode
  
  212
- Interactive Mode
  
  213
  - 13504CFG Menu Bar
    213
    
    Viewing 13504CFG Menu Contents
    213
    
    Making 13504CFG Menu Selections
    214
    
    Files Menu
    215
    
    View Menu
    216
    
    Device Menu
    218
    
    Panel
    219
    
    Crt
    221
    
    Advanced Memory
    223
    
    Power Management
    225
    
    Lookup Table (LUT)
    227
    
    Setup
    229
    
    Help Menu
    230
  - Comments
    231
  - Sample Program Messages
    231
Table of Contents

267
- 13504Dcfg
  271
- Installation
  271
- Usage
  271
- 13504DCFG Configuration Tabs
  272
- General Tab
  273
- Memory Tab
  274
- Clocks Tab
  275
- Panel Tab
  277
- CRT Tab
  279
- Defaults Tab
  280
- Registers Tab
  281
- Miscellaneous Flags Tab
  282
- Saving to a File
  283
- Comments
  284
This Page Left Blank

309
- 1 Introduction
  
  313
  - Features
    313
- 2 Installation and Configuration
  
  314
- 3 LCD / RAMDAC Interface Pin Mapping
  
  315
- 4 CPU / BUS Interface Connector Pinouts
  
  316
- 5 Host Bus Interface Pin Mapping
  
  318
- 6 Technical Description
  
  319
  - ISA Bus Support
    319
  - Non-ISA Bus Support
    320
  - DRAM Support
    320
  - Decode Logic
    320
  - Clock Input Support
    320
  - Monochrome LCD Panel Support
    321
  - Color Passive LCD Panel Support
    321
  - Color TFT LCD Panel Support
    321
  - External CMOS RAMDAC Support
    321
  - Power Save Modes
    322
  - Core VDD Power Supply
    322
  - IO VDD Power Supply
    322
  - Adjustable LCD Panel Negative Power Supply
    322
  - Adjustable LCD Panel Positive Power Supply
    322
  - Cpu/Bus Interface Header Strips
    323
  - Schematic Notes
    323
- 7 Parts List
  
  324
- 8 Schematic Diagrams
  
  326
This Page Left Blank

335
- 1 Introduction
  
  339
- 2 Features
  
  340
  - S1D13504 Color Graphics LCD Controller
    340
    
    Display Buffer
    340
    
    LCD Display Support
    341
    
    LCD Interface Pin Mapping
    342
    
    Adjustable LCD BIAS Power Supply
    343
    
    CRT Support
    343
- 3 D9000 Specifics
  
  344
  - Interface Signals
    344
    
    Connector Pinout for Channel A6 and A7
    344
    
    Bus Interface Timing
    349
    
    Makefpga File
    349
    
    Memory Address (CS#, M/R#) Decode
    349
  - Board Dimensions
    349
  - Support Documentation Notes
    349
  - Parts List
    350
  - Schematic Diagrams
    351
    
    Component Placement
    355
    
    Pcb Layout
    355
    
    Perspective View
    356
Table of Contents

363
- 1 Introduction
  
  367
- 2 Interfacing to the PR31500/PR31700
  
  368
- 3 S1D13504 Host Bus Interface
  
  369
  - Generic MPU Host Bus Interface Pin Mapping
    369
  - Generic MPU Host Bus Interface Signals
    370
- 4 Direct Connection to the Philips PR31500/PR31700
  
  371
  - Hardware Description
    371
  - Memory Mapping and Aliasing
    372
  - S1D13504 Configuration
    373
- 5 System Design Using the IT8368E PC Card Buffer
  
  374
  - Hardware Description-Using One IT8368E
    374
  - Hardware Description-Using Two It8368E's
    377
  - IT8368E Configuration
    378
  - Memory Mapping and Aliasing
    379
  - S1D13504 Configuration
    380
- 6 Software
  
  381
- 7 References
  
  382
  - Documents
    382
  - Document Sources
    382
- 8 Technical Support
  
  383
  - EPSON LCD/CRT Controllers (S1D13504)
    383
  - Philips MIPS PR31500/PR31700 Processor
    383
  - Ite It8368E
    383
Table of Contents

387
- 1 Introduction
  
  391
- 2 Interfacing to the NEC VR4102
  
  392
  - The NEC VR4102 System Bus
    392
    
    Overview
    392
    
    LCD Memory Access Cycles
    393
- 3 S1D13504 Host Bus Interface
  
  394
  - Generic MPU Host Bus Interface Pin Mapping
    394
  - Generic MPU Host Bus Interface Signals
    395
- 4 VR4102 to S1D13504 Interface
  
  396
  - Hardware Description
    396
  - S1D13504 Hardware Configuration
    397
- 5 Software
  
  399
- 6 References
  
  400
  - Documents
    400
  - Document Sources
    400
- 7 Technical Support
  
  401
  - EPSON LCD/CRT Controllers (S1D13504)
    401
  - NEC Electronics Inc. (VR4102)
    401
Table of Contents

405
- 1 Introduction
  
  409
- 2 Interfacing to the MCF5307
  
  410
  - The MCF5307 System Bus
    410
    
    Normal (Non-Burst) Bus Transactions
    410
    
    Overview
    410
    
    Burst Cycles
    412
  - Chip-Select Module
    412
- 3 S1D13504 Bus Interface
  
  413
  - Generic MPU Host Bus Interface Pin Mapping
    413
  - Generic MPU Host Bus Interface Signals
    414
- 4 MCF5307 to S1D13504 Interface
  
  415
  - Hardware Connections
    415
  - S1D13504 Hardware Configuration
    416
  - Memory/Register Mapping
    417
  - MCF5307 Chip Select Configuration
    417
- 5 Software
  
  418
- 6 References
  
  419
  - Documents
    419
  - Document Sources
    419
- 7 Technical Support
  
  420
  - EPSON LCD/CRT Controllers (S1D13504)
    420
  - Motorola MCF5307 Processor
    420

Epson Categories

Printer

Projector

All in One Printer

Scanner Printer Accessories

More Epson Manuals

Epson S1D13504 Manuals

Epson S1D13504 Technical Manual (556 pages)

Table of Contents

This Page Left Blank

1 Introduction

2 Features

3 Typical System Implementation Diagrams

4 Block Description

5 Pin out

6 C. Characteristics

7 C. Characteristics

8 Registers

9 Display Buffer

10 Display Configuration

11 Clocking

12 Look-Up Table Architecture

13 Power Save Modes

14 Mechanical Data

15 References

16 Sales and Technical Support

This Page Left Blank

1 Introduction

2 Programming the S1D13504 Registers

3 Display Buffer

4 Advanced Techniques

5 LCD Power Sequencing and Power Save Modes

6 CRT Considerations

7 Identifying the S1D13504

8 Hardware Abstraction Layer (HAL)

9 Sample Code

Appendix A Supported Panel Values

This Page Left Blank

13504Cfg.exe

Program Requirements

Script Mode

Interactive Mode

13504Dcfg Menus

This Page Left Blank

1 Introduction

2 Installation and Configuration

3 LCD / RAMDAC Interface Pin Mapping

4 CPU / BUS Interface Connector Pinouts

5 Host Bus Interface Pin Mapping

6 Technical Description

7 Parts List

8 Schematic Diagrams

Table of Contents

2 Features

3 Installation and Configuration

4 Technical Description

6 Parts List

7 Schematics

8 Board Layout

9 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the PR31500/PR31700

3 S1D13504 Host Bus Interface

4 Direct Connection to the Philips PR31500/PR31700

5 System Design Using the IT8368E PC Card Buffer

6 Software

Table of Contents

1 Introduction

2 Interfacing to the NEC VR4102

3 S1D13504 Host Bus Interface

4 VR4102 to S1D13504 Interface

5 Software

6 References

7 Technical Support

This Page Left Blank

1 Introduction

2 Interfacing to the MC68328

3 S1D13504 Host Bus Interface

4 MC68328 to S1D13504 Interface

5 Software

6 References

7 Technical Support

Epson S1D13504 Technical Manual (504 pages)

Table of Contents

This Page Left Blank