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Epson S1D13506 manual available for free PDF download: Technical Manual
Epson S1D13506 Technical Manual (712 pages)
Color LCD/CRT/TV Controller
Brand:
Epson
| Category:
Controller
| Size: 6.51 MB
Table of Contents
Table of Contents
9
Millenia Tower Singapore
3
Riesstrasse
3
Issue Date: 02/03/26 Page
11
List of Tables
15
1 Introduction
23
Scope
23
Overview Description
23
2 Features
24
Memory Interface
24
CPU Interface
24
Display Support
25
Display Modes
25
Display Features
25
Clock Source
26
Acceleration
26
Mediaplug Interface
26
Miscellaneous
26
3 Typical System Implementation Diagrams
27
Figure 3-1: Typical System Diagram (Generic Bus)
27
Figure 3-2: Typical System Diagram (Hitachi SH-4 Bus)
28
Figure 3-3: Typical System Diagram (Hitachi SH-3 Bus)
28
Figure 3-4: Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000)
29
Figure 3-5: Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030)
29
Figure 3-6: Typical System Diagram (Motorola Powerpc Bus)
30
Figure 3-7: Typical System Diagram (Necvr41Xx MIPS Bus)
30
Figure 3-8: Typical System Diagram (PC Card Bus)
31
Figure 3-9: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)
31
Figure 3-10: Typical System Diagram (Toshiba MIPS TX3912 Bus)
32
4 Internal Description
33
Block Diagram Showing Pipelines
33
Figure 4-1: S1D13506 Block Diagram
33
5 Pins
34
Pinout Diagram
34
Figure 5-1: Pinout Diagram
34
Pin Description
35
Host Bus Interface
35
Table 5-1: Host Bus Interface Pin Descriptions
35
Memory Interface
41
Table 5-2: Memory Interface Pin Descriptions
41
LCD Interface
43
Table 5-3: LCD Interface Pin Descriptions
43
CRT Interface
44
Miscellaneous
44
Table 5-4: CRT Interface Pin Descriptions
44
Table 5-5: Miscellaneous Interface Pin Descriptions
44
Summary of Configuration Options
45
Table 5-6: Summary of Power-On/Reset Options
45
Multiple Function Pin Mapping
46
Table 5-7: CPU Interface Pin Mapping
46
Table 5-8: Memory Interface Pin Mapping
47
Table 5-9: LCD Interface Pin Mapping
48
Table 5-10: MA11, MA10, MA9, and DRDY Pin Mapping
49
Table 5-11: Mediaplug Interface Pin Mapping
49
CRT/TV Interface
50
Figure 5-2: External Circuitry for CRT/TV Interface
50
6 C. Characteristics
51
Table 6-1: Absolute Maximum Ratings
51
Table 6-2: Recommended Operating Conditions
51
Table 6-3: Electrical Characteristics for VDD = 5.0V Typical
51
Table 6-4: Electrical Characteristics for VDD = 3.3V Typical
52
Table 6-5: Electrical Characteristics for VDD = 3.0V Typical
53
7 C. Characteristics
54
CPU Interface Timing
54
Figure 7-1: Generic Timing
54
Generic Timing
54
Table 7-1: Generic Timing
55
Figure 7-2: Hitachi SH-4 Timing
56
Hitachi SH-4 Interface Timing
56
Table 7-2: Hitachi SH-4 Timing
57
Figure 7-3: Hitachi SH-3 Timing
58
Hitachi SH-3 Interface Timing
58
Table 7-3: Hitachi SH-3 Timing
59
Figure 7-4: MIPS/ISA Timing
60
MIPS/ISA Interface Timing (E.g. NEC Vr41Xx)
60
Table 7-4: MIPS/ISA Timing
61
Figure 7-5: Motorola MC68000 Timing
62
Motorola MC68K Bus 1 Interface Timing (E.g. MC68000)
62
Table 7-5: Motorola MC68000 Timing
63
Figure 7-6: Motorola MC68030 Timing
64
Motorola MC68K Bus 2 Interface Timing (E.g. MC68030)
64
Table 7-6: Motorola MC68030 Timing
65
Motorola Powerpc Interface Timing (E.g. Mpc8Xx, MC68040, Coldfire)
66
Figure 7-7: Motorola Powerpc Timing
66
Table 7-7: Motorola Powerpc Timing
67
PC Card Timing (E.g. Strongarm)
68
Figure 7-8: PC Card Timing
68
Table 7-8: PC Card Timing
69
Philips Interface Timing (E.g. PR31500/PR31700)
70
Figure 7-9: Philips Timing
70
Table 7-9: Philips Timing
71
Toshiba Interface Timing (E.g. Tx39Xx)
72
Figure 7-10: Toshiba Timing
72
Table 7-10: Toshiba Timing
73
Clock Timing
74
Figure 7-11: CLKI Clock Input Requirements
74
Input Clocks
74
Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK Divided down Internally
74
Table 7-12: Clock Input Requirements for CLKI or BUSCLK if Used Directly for MCLK1
74
Internal Clocks
75
Table 7-13: Internal Clock Requirements
75
Memory Interface Timing
76
EDO-DRAM Read, Write, Read-Write Timing
76
Figure 7-12: EDO-DRAM Page Mode Timing
76
Figure 7-13: EDO-DRAM Read-Write Timing
76
Table 7-14: EDO-DRAM Read, Write, Read-Write Timing
77
EDO-DRAM cas before RAS Refresh Timing
78
Figure 7-14: EDO-DRAM cas before RAS Refresh Timing
78
Table 7-15: EDO-DRAM cas before RAS Refresh Timing
78
EDO-DRAM Self-Refresh Timing
79
Figure 7-15: EDO - DRAM Self-Refresh Timing
79
Table 7-16: EDO - DRAM Self-Refresh Timing
79
Figure 7-16: FPM-DRAM Page Mode Timing
80
Figure 7-17: FPM-DRAM Read-Write Timing
80
FPM-DRAM Read, Write, Read-Write Timing
80
Table 7-17: FPM-DRAM Read, Write, Read-Write Timing
81
Figure 7-18: FPM-DRAM cas before RAS Refresh Timing
82
FPM-DRAM cas before RAS Refresh Timing
82
Table 7-18: FPM-DRAM cas before RAS Refresh Timing
82
Figure 7-19: FPM - DRAM Self-Refresh Timing
83
FPM-DRAM Self-Refresh Timing
83
Table 7-19: FPM-DRAM Self-Refresh Timing
83
Power Sequencing
84
Figure 7-20: LCD Panel Power-Off/Power-On Timing
84
LCD Power Sequencing
84
Table 7-20: LCD Panel Power-Off/Power-On Timing
84
Figure 7-21: Power Save Mode Timing
85
Power Save Mode
85
Table 7-21: Power Save Mode Timing
86
Display Interface
87
Figure 7-22: Single Monochrome 4-Bit Panel Timing
87
Single Monochrome 4-Bit Panel Timing
87
Figure 7-23: Single Monochrome 4-Bit Panel A.C. Timing
88
Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing
89
Figure 7-24: Single Monochrome 8-Bit Panel Timing
90
Single Monochrome 8-Bit Panel Timing
90
Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing
91
Table 7-23: Single Monochrome 8-Bit Panel A.C. Timing
92
Figure 7-26: Single Color 4-Bit Panel Timing
93
Single Color 4-Bit Panel Timing
93
Figure 7-27: Single Color 4-Bit Panel A.C. Timing
94
Table 7-24: Single Color 4-Bit Panel A.C. Timing
95
Figure 7-28: Single Color 8-Bit Panel Timing (Format 1)
96
Single Color 8-Bit Panel Timing (Format 1)
96
Figure 7-29: Single Color 8-Bit Panel A.C. Timing (Format 1)
97
Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1)
98
Figure 7-30: Single Color 8-Bit Panel Timing (Format 2)
99
Single Color 8-Bit Panel Timing (Format 2)
99
Figure 7-31: Single Color 8-Bit Panel A.C. Timing (Format 2)
100
Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2)
101
Figure 7-32: Single Color 16-Bit Panel Timing
102
Single Color 16-Bit Panel Timing
102
Figure 7-33: Single Color 16-Bit Panel A.C. Timing
103
Table 7-27: Single Color 16-Bit Panel A.C. Timing
104
Figure 7-34: 16-Bit Single Color Panel Timing with External Circuit
105
Single Color 16-Bit Panel Timing with External Circuit
105
Figure 7-35: External Circuit for Color Single 16-Bit Panel When the Media Plug Is Enabled
106
Figure 7-36: Single Color 16-Bit Panel (with External Circuit) A.C. Timing
106
Table 7-28: Single Color 16-Bit Panel (with External Circuit) A.C. Timing
107
Dual Monochrome 8-Bit Panel Timing
108
Figure 7-37: Dual Monochrome 8-Bit Panel Timing
108
Figure 7-38: Dual Monochrome 8-Bit Panel A.C. Timing
109
Table 7-29: Dual Monochrome 8-Bit Panel A.C. Timing
110
Dual Color 8-Bit Panel Timing
111
Figure 7-39: Dual Color 8-Bit Panel Timing
111
Figure 7-40: Dual Color 8-Bit Panel A.C. Timing
112
Table 7-30: Dual Color 8-Bit Panel A.C. Timing
113
Dual Color 16-Bit Panel Timing
114
Figure 7-41: Dual Color 16-Bit Panel Timing
114
Figure 7-42: Dual Color 16-Bit Panel A.C. Timing
115
Table 7-31: Dual Color 16-Bit Panel A.C. Timing
116
Dual Color 16-Bit Panel Timing with External Circuit
117
Figure 7-43: 16-Bit Dual Color Panel Timing with External Circuit
117
Figure 7-44: External Circuit for Color Dual 16-Bit Panel When the Media Plug Is Enabled
118
Figure 7-45: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
118
Table 7-32: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
119
Figure 7-46: TFT/D-TFD Panel Timing
120
TFT/D-TFD Panel Timing
120
Figure 7-47: TFT/D-TFD A.C. Timing
121
Table 7-33: TFT/D-TFD A.C. Timing
122
CRT Timing
123
Figure 7-48: CRT Timing
123
Figure 7-49: CRT A.C. Timing
124
Table 7-34: CRT A.C. Timing
124
TV Timing
125
Figure 7-50: NTSC Video Timing
125
TV Output Timing
125
Figure 7-51: PAL Video Timing
126
Figure 7-52: Horizontal Timing for NTSC/PAL
127
Table 7-35: Horizontal Timing for NTSC/PAL
127
Figure 7-53: Vertical Timing for NTSC/PAL
128
Table 7-36: Vertical Timing for NTSC/PAL
128
Mediaplug Interface Timing
129
Table 7-37: Mediaplug A.C. Timing
129
Figure 7-54: Mediaplug A.C. Timing
129
8 Registers
130
Initializing the S1D13506
130
Register/Memory Select Bit
130
Register Mapping
130
Table 8-1: Register Mapping with CS# = 0 and M/R# = 0
130
Register Descriptions
131
Basic Registers
131
General IO Pins Registers
132
Table 8-2: MA[11:9]/GPIO[1:3] Pin Functionality
132
Clock Configuration Registers
134
MD Configuration Readback Registers
134
Table 8-3: MCLK Source Select
134
Table 8-4: LCD PCLK Divide Selection
135
Table 8-5: LCD PCLK Source Selection
135
Table 8-6: CRT/TV PCLK Divide Selection
136
Table 8-7: CRT/TV PCLK Source Selection
136
Table 8-8: Mediaplug Clock Divide Selection
136
Table 8-10: Minimum Memory Timing Selection
137
Table 8-9: Video Clock Source Selection
137
Memory Configuration Registers
138
Table 8-11: Memory Type Selection
138
Table 8-12: Refresh Selection
138
Table 8-13: DRAM Refresh Rate Selection
139
Table 8-14: DRAM Timing Control Selection
140
Panel Configuration Registers
141
Table 8-15: Panel Data Width Selection
141
Table 8-16: Horizontal Display Width (Pixels)
142
Table 8-17: LCD FPLINE Polarity Selection
144
LCD Display Mode Registers
146
Table 8-18: LCD FPFRAME Polarity Selection
146
Table 8-19: Setting Swivelview Modes
147
Table 8-20: LCD Bit-Per-Pixel Selection
147
Table 8-21: LCD Pixel Panning Selection
150
CRT/TV Configuration Registers
151
Table 8-22: DAC Output Level Selection
155
CRT/TV Display Mode Registers
156
Table 8-23: CRT/TV Bit-Per-Pixel Selection
156
Table 8-24: CRT/TV Pixel Panning Selection
158
Table 8-25: LCD Ink/Cursor Selection
159
Table 8-26: LCD Ink/Cursor Start Address Encoding
160
Table 8-27: CRT/TV Ink/Cursor Selection
163
Table 8-28: CRT/TV Ink/Cursor Start Address Encoding
164
Bitblt Configuration Registers
167
Table 8-29: Bitblt Active Status
167
Table 8-30: Bitblt FIFO Data Available
168
Table 8-31: Bitblt ROP Code/Color Expansion Function Selection
169
Table 8-32: Bitblt Operation Selection
170
Table 8-33: Bitblt Source Start Address Selection
171
Look-Up Table Registers
175
Table 8-34: LUT Mode Selection
175
Power Save Configuration Registers
176
Miscellaneous Registers
177
Common Display Mode Register
178
Table 8-35: Setting Swivelview Modes
178
Table 8-36: Display Mode Selection
178
Mediaplug Register Descriptions
179
Table 8-37: Mediaplug LCMD Read/Write Descriptions
179
Table 8-38: Timeout Option Delay
179
Table 8-39: Cable Detect and Remote Powered Status
180
Table 8-40: Mediaplug CMD Read/Write Descriptions
181
Table 8-41: Mediaplug Commands
182
Bitblt Data Registers Descriptions
183
Bitblt Operations
184
D Bitblt Engine
184
Functional Description
184
Figure 10-1: Display Buffer Addressing
187
Table 10-1: S1D13506 Addressing
187
Dual Panel Buffer
188
Image Buffer
188
Ink Layer/Hardware Cursor Buffers
188
Display Configuration
189
Display Mode Data Format
189
Figure 11-1: 4/8/15/16 Bit-Per-Pixel Format Memory Organization
189
Figure 11-2: Image Manipulation
190
Figure 12-1: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
191
Look-Up Table Architecture
191
Monochrome Modes
191
Figure 12-2: 4 Bit-Per-Pixel Color Mode Data Output Path
192
Figure 12-3: 8 Bit-Per-Pixel Color Mode Data Output Path
193
Clock Source
194
NTSC/PAL Operation
194
Table 13-1: Required Clock Frequencies for NTSC/PAL
194
Anti-Flicker Filter (Reg[1Fch] Bits [2:1])
195
Chrominance Filter (Reg[05Bh] Bit)
195
Filters
195
Luminance Filter (Reg[05Bh] Bit)
195
Figure 13-1: NTSC/PAL Svideo-Y (Luminance) Output Levels
196
Table 13-2: NTSC/PAL Svideo-Y (Luminance) Output Levels
196
Figure 13-2: NTSC/PAL Svideo-C (Chrominance) Output Levels
197
Table 13-3: NTSC/PAL Svideo-C (Chrominance) Output Levels
197
Figure 13-3: NTSC/PAL Composite Output Levels
198
Table 13-4: NTSC/PAL Composite Output Levels
198
Table 13-5: Minimum and Maximum Values for NTSC/PAL
199
TV Image Display and Positioning
199
Figure 13-4: NTSC/PAL Image Positioning
200
Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL
201
Table 13-6: Register Values for Example NTSC/PAL Images
201
TV Cursor Operation
201
Ink Layer/Hardware Cursor Architecture
202
Ink Layer/Hardware Cursor Buffers
202
Table 14-1: Ink/Cursor Start Address Encoding
202
Figure 14-1: Ink/Cursor Data Format
203
Table 14-2: Ink/Cursor Color Select
203
Cursor Image
204
Figure 14-2: Unclipped Cursor Positioning
204
Ink Image
204
Ink/Cursor Image Manipulation
204
Figure 14-3: Clipped Cursor Positioning
205
Concept
206
Figure 15-1: Relationship between Screen Image and 90° Rotated Image in the Display Buffer
207
Register Programming
207
Physical Memory Requirement
209
Limitations
210
Table 15-1: Minimum DRAM Size Required for Swivelview
210
Register Programming
211
Limitations
212
Register Programming
212
Physical Memory Requirement
213
Limitations
214
Epson Independent Simultaneous Display (Eisd)
215
Introduction
215
Bandwidth Limitation
216
How to Enable the Mediaplug Slave
217
Revision Code
217
Table 17-1: Mediaplug Interface Pin Mapping
217
Clocking
218
Frame Rate Calculation
218
LCD Frame Rate Calculation
218
CRT Frame Rate Calculation
219
TV Frame Rate Calculation
220
Example Frame Rates
221
Table 18-1: Frame Rates for 640X480 with EISD Disabled
221
Table 18-2: Frame Rates for 800X600 with EISD Disabled
222
Table 18-3: Frame Rates for LCD and CRT (640X480) with EISD Enabled
223
Table 18-4: Frame Rates for LCD and CRT (800X600) with EISD Enabled
224
Table 18-5: Frame Rates for LCD and NTSC TV with EISD Enabled
225
Table 18-6: Frame Rates for LCD and PAL TV with EISD Enabled
226
Power Save Mode
227
Table 19-1: Power Save Mode Summary
228
Figure 20-1: Clock Selection
229
Clock Descriptions
230
Crt/Tv Pclk
230
Lcd Pclk
230
Mclk
230
Mediaplug Clock
230
Table 20-1: Clocks Vs. Functions
231
Figure 21-1: Mechanical Drawing QFP15
232
Mechanical Data
232
Sales and Technical Support
233
Temasek Avenue #36-00
233
Programming Notes and Examples
235
Table of Contents
237
3 Memory Models
250
Display Buffer Location
250
Memory Organization for 4 Bpp (16 Colors/16 Gray Shades)
250
Memory Organization for 15 Bpp (32768 Colors/32 Gray Shades)
251
Memory Organization for 8 Bpp (256 Colors/16 Gray Shades)
251
Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
252
4 Look-Up Table (LUT)
253
Registers
253
Look-Up Table Organization
254
Color Modes
255
Gray Shade Modes
258
5 Virtual Displays
260
Virtual Display
260
Registers
261
Examples
262
Panning and Scrolling
264
Registers
265
Examples
267
6 Power Save Mode
269
Overview
269
Registers
269
Enabling Power Save Mode
269
Power Save Status Bits
270
DRAM Refresh Selection
271
7 LCD Power Sequencing
272
Automatic Sequencing
272
Manual Sequencing
272
Disabling the LCD Panel
273
Enabling the LCD Panel
273
Registers
273
8 Hardware Cursor/Ink Layer
274
Introduction
274
Registers
275
Initialization
281
Memory Considerations
281
Examples
282
Writing Cursor/Ink Layer Images
284
Hardware Cursor/Ink Layer Data Format
284
Cursor Image
285
Ink Layer Image
286
Cursor Movement
287
Move Cursor in Landscape Mode (no Rotation)
287
Move Cursor in Swivelview 180° Rotation
288
Move Cursor in Swivelview 90° Rotation
288
Move Cursor in Swivelview 270° Rotation
289
9 Swivelview
290
S1D13506 Swivelview
290
Registers
290
Limitations
292
Examples
293
Simultaneous Display Considerations
294
Registers
295
Bitblt Descriptions
302
Write Blit with ROP
303
Color Expand Bitblt
305
Color Expand Bitblt with Transparency
310
Solid Fill Bitblt
310
Move Bitblt in a Positive Direction with ROP
311
Move Bitblt in Negative Direction with ROP
313
Transparent Write Blit
315
Transparent Move Bitblt in Positive Direction
317
Pattern Fill Bitblt with ROP
319
Pattern Fill Bitblt with Transparency
321
Move Bitblt with Color Expansion
322
Read Blit
324
Transparent Move Blit with Color Expansion
324
S1D13506 Bitblt Synchronization
326
S1D13506 Bitblt Known Limitations
328
Sample Code
328
11 CRT/TV Considerations
329
CRT Considerations
329
DAC Output Level Selection
329
Generating CRT Timings with 13506CFG
329
Examples
330
NTSC Timings
330
PAL Timings
330
TV Considerations
330
Examples
331
TV Filters
331
Simultaneous Display
332
12 Mediaplug
333
Programming
333
Considerations
333
13 Identifying the S1D13506
335
14 Hardware Abstraction Layer (HAL)
336
API for 13506HAL
336
Initialization
341
General HAL Support
344
Advance HAL Functions
349
Surface Support
351
Register Access
354
Memory Access
356
Color Manipulation
358
Virtual Display
362
Drawing
364
Hardware Cursor
370
Ink Layer
377
PCI Support
383
Porting LIBSE to a New Target Platform
384
Building a Complete Application for the Target Example
385
Building the LIBSE Library for SH3 Target Example
385
15 Sample Code
386
Table of Contents
393
13506Cfg
395
S1D13506 Supported Evaluation Platforms
395
Installation
396
Usage
396
13506CFG Configuration Tabs
397
General Tab
397
Preferences Tab
399
Memory Tab
400
Clocks Tab
402
Panel Tab
406
CRT/TV Tab
410
Registers Tab
412
13506CFG Menus
413
Open
413
Save
414
Save as
414
Configure Multiple
415
Export
416
Enable Tooltips
417
ERD on the Web
417
About 13506CFG
417
Comments
417
Installation Guide
513
User Manual
521
Table of Contents
523
List of Figures
525
List of Tables
525
1 Introduction
527
2 Features
528
3 Installation and Configuration
529
Configuration DIP Switches
529
Configuration Jumpers
530
4 Technical Description
531
PCI Bus Support
531
On-Board PCI Configuration Registers
532
Utility Software
532
Non-PCI Host Interface Support
533
CPU Interface Pin Mapping
533
CPU Bus Connector Pin Mapping
534
LCD Support
536
LCD Interface Pin Mapping
537
16-Bit Passive Color Panel Support with Mediaplug Enabled
538
Buffered LCD Connector
538
Adjustable LCD Panel Negative Power Supply
539
Adjustable LCD Panel Positive Power Supply
539
CRT/TV Support
540
CRT Support
540
CRT/TV Interface Pin Mapping
540
TV Support
540
Mediaplug Interface
541
Clock Synthesizer and Clock Options
542
Clock Programming
542
5 References
543
Documents
543
Document Sources
543
6 Parts List
544
7 Schematic Diagrams
546
8 Technical Support
553
EPSON Lcd/Crtcontrollers (S1D13506)
553
Table of Contents
557
1 Introduction
561
2 Interfacing to the PC Card Bus
562
The PC Card System Bus
562
Memory Access Cycles
562
PC Card Overview
562
3 S1D13506 Host Bus Interface
565
PC Card Host Bus Interface Pin Mapping
565
PC Card Host Bus Interface Signals
566
4 PC Card to S1D13506 Interface
567
Hardware Description
567
S1D13506 Hardware Configuration
569
Performance
569
Register/Memory Mapping
570
5 Software
571
6 References
572
Documents
572
Document Sources
572
7 Technical Support
573
Epson LCD/CRT Controllers (S1D13506)
573
PC Card Standard
573
Power Consumption
575
Host Bus Interface Signal Descriptions
583
1 Introduction
587
2 Interfacing to the VR4102/VR4111
588
The NEC VR4102/VR4111 System Bus
588
Overview
588
LCD Memory Access Cycles
589
3 S1D13506 Host Bus Interface
590
Host Bus Interface Pin Mapping
590
Host Bus Interface Signal Descriptions
591
4 VR4102/VR4111 to S1D13506 Interface
592
Hardware Description
592
S1D13506 Hardware Configuration
593
5 Software
594
6 References
595
Documents
595
Document Sources
595
7 Technical Support
596
EPSON LCD/CRT Controllers (S1D13506)
596
NEC Electronics Inc. (VR4102/VR4111)
596
Table of Contents
599
1 Introduction
603
2 Interfacing to the MPC821
604
The Mpc8Xx System Bus
604
MPC821 Bus Overview
604
Normal (Non-Burst) Bus Transactions
605
Burst Cycles
606
Memory Controller Module
607
General-Purpose Chip Select Module (GPCM)
607
User-Programmable Machine (UPM)
608
3 S1D13506 Host Bus Interface
609
Powerpc Host Bus Interface Pin Mapping
609
Powerpc Host Bus Interface Signals
610
4 MPC821 to S1D13506 Interface
611
Hardware Description
611
Hardware Connections
612
S1D13506 Hardware Configuration
614
Register/Memory Mapping
614
MPC821 Chip Select Configuration
615
Test Software
616
5 Software
617
6 References
618
Documents
618
Document Sources
618
7 Technical Support
619
EPSON LCD/CRT Controllers (S1D13506)
619
Motorola MPC821 Processor
619
Table of Contents
623
1 Introduction
627
2 Interfacing to the PR31500/PR31700
628
3 S1D13506 Host Bus Interface
629
PR31500/PR31700 Host Bus Interface Pin Mapping
629
PR31500/PR31700 Host Bus Interface Signals
630
4 Direct Connection to the Philips PR31500/PR31700
631
Hardware Description
631
S1D13506 Configuration
632
Memory Mapping and Aliasing
633
5 System Design Using the IT8368E PC Card Buffer
634
Hardware Description
634
IT8368E Configuration
635
S1D13506 Configuration
635
6 Software
636
7 References
637
Documents
637
Document Sources
637
8 Technical Support
638
EPSON LCD/CRT Controllers (S1D13506)
638
Philips MIPS PR31500/PR31700 Processor
638
Ite It8368E
638
Table of Contents
641
1 Introduction
645
2 Interfacing to the TX3912
646
3 S1D13506 Host Bus Interface
647
TX3912 Host Bus Interface Pin Mapping
647
TX3912 Host Bus Interface Signals
648
4 Direct Connection to the Toshiba TX3912
649
Hardware Description
649
S1D13506 Configuration
650
Memory Mapping and Aliasing
651
5 System Design Using the IT8368E PC Card Buffer
652
Hardware Description
652
IT8368E Configuration
653
S1D13506 Configuration
653
6 Software
654
7 References
655
Documents
655
Document Sources
655
8 Technical Support
656
EPSON LCD/CRT Controllers (S1D13506)
656
Toshiba MIPS TX3912 Processor
656
Ite It8368E
656
Table of Contents
659
1 Introduction
663
The NEC VR4121 System Bus
664
Overview
664
LCD Memory Access Cycles
665
3 S1D13506 Host Bus Interface
666
Host Bus Interface Pin Mapping
666
Host Bus Interface Signal Descriptions
667
4 VR4121 to S1D13506 Interface
668
Hardware Description
668
S1D13506 Configuration
669
Memory Mapping and Aliasing
670
5 Software
671
6 References
672
Documents
672
Document Sources
672
7 Technical Support
673
Epson LCD/CRT Controllers (S1D13506)
673
NEC Electronics Inc. (VR4121)
673
Table of Contents
677
1 Introduction
681
2 Interfacing to the NEC V832
682
The NEC V832 System Bus
682
Overview
682
Access Cycles
683
3 S1D13506 Host Bus Interface
684
Host Bus Interface Pin Mapping
684
Host Bus Interface Signal Descriptions
685
4 V832 to S1D13506 Interface
686
Hardware Description
686
S1D13506 Hardware Configuration
687
NEC V832 Configuration
688
Memory Mapping and Aliasing
689
5 Software
690
6 References
691
Documents
691
Document Sources
691
7 Technical Support
692
Epson LCD/CRT Controllers (S1D13506)
692
NEC Electronics Inc. (V832)
692
The Strongarm Sa-1110 System Bus/Host Bus Interface Signal Descriptions
695
1 Introduction
699
2 Interfacing to the Strongarm SA-1110 Bus
700
The Strongarm SA-1110 System Bus
700
Strongarm SA-1110 Overview
700
Variable-Latency IO Access Overview
700
Variable-Latency IO Access Cycles
701
3 S1D13506 Host Bus Interface
703
Host Bus Interface Pin Mapping
703
Host Bus Interface Signal Descriptions
704
4 Strongarm SA-1110 to S1D13506 Interface
705
Hardware Description
705
S1D13506 Hardware Configuration
706
Performance
706
Register/Memory Mapping
707
Strongarm SA-1110 Register Configuration
708
5 Software
709
6 References
710
Documents
710
Document Sources
710
7 Technical Support
711
EPSON LCD/CRT Controllers (S1D13506)
711
Intel Strongarm SA-1110 Micro-Processor
711
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